1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 41 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 42 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 43 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 44 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 45 46 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 47 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 48 49 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 50 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 51 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 52 53 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 54 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 55 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 56 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 57 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 58 59 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 60 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 61 62 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 63 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 64 65 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 66 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 67 68 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 69 #define SDHCI_AUTO_CAL_START BIT(31) 70 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 71 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 72 73 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 74 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 75 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 76 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 77 78 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 79 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 80 81 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 82 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 83 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 84 #define NVQUIRK_ENABLE_SDR50 BIT(3) 85 #define NVQUIRK_ENABLE_SDR104 BIT(4) 86 #define NVQUIRK_ENABLE_DDR50 BIT(5) 87 #define NVQUIRK_HAS_PADCALIB BIT(6) 88 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 89 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 90 91 struct sdhci_tegra_soc_data { 92 const struct sdhci_pltfm_data *pdata; 93 u32 nvquirks; 94 }; 95 96 /* Magic pull up and pull down pad calibration offsets */ 97 struct sdhci_tegra_autocal_offsets { 98 u32 pull_up_3v3; 99 u32 pull_down_3v3; 100 u32 pull_up_3v3_timeout; 101 u32 pull_down_3v3_timeout; 102 u32 pull_up_1v8; 103 u32 pull_down_1v8; 104 u32 pull_up_1v8_timeout; 105 u32 pull_down_1v8_timeout; 106 u32 pull_up_sdr104; 107 u32 pull_down_sdr104; 108 u32 pull_up_hs400; 109 u32 pull_down_hs400; 110 }; 111 112 struct sdhci_tegra { 113 const struct sdhci_tegra_soc_data *soc_data; 114 struct gpio_desc *power_gpio; 115 bool ddr_signaling; 116 bool pad_calib_required; 117 bool pad_control_available; 118 119 struct reset_control *rst; 120 struct pinctrl *pinctrl_sdmmc; 121 struct pinctrl_state *pinctrl_state_3v3; 122 struct pinctrl_state *pinctrl_state_1v8; 123 124 struct sdhci_tegra_autocal_offsets autocal_offsets; 125 126 u32 default_tap; 127 u32 default_trim; 128 u32 dqs_trim; 129 }; 130 131 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 132 { 133 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 134 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 135 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 136 137 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 138 (reg == SDHCI_HOST_VERSION))) { 139 /* Erratum: Version register is invalid in HW. */ 140 return SDHCI_SPEC_200; 141 } 142 143 return readw(host->ioaddr + reg); 144 } 145 146 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 147 { 148 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 149 150 switch (reg) { 151 case SDHCI_TRANSFER_MODE: 152 /* 153 * Postpone this write, we must do it together with a 154 * command write that is down below. 155 */ 156 pltfm_host->xfer_mode_shadow = val; 157 return; 158 case SDHCI_COMMAND: 159 writel((val << 16) | pltfm_host->xfer_mode_shadow, 160 host->ioaddr + SDHCI_TRANSFER_MODE); 161 return; 162 } 163 164 writew(val, host->ioaddr + reg); 165 } 166 167 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 168 { 169 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 170 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 171 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 172 173 /* Seems like we're getting spurious timeout and crc errors, so 174 * disable signalling of them. In case of real errors software 175 * timers should take care of eventually detecting them. 176 */ 177 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 178 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 179 180 writel(val, host->ioaddr + reg); 181 182 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 183 (reg == SDHCI_INT_ENABLE))) { 184 /* Erratum: Must enable block gap interrupt detection */ 185 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 186 if (val & SDHCI_INT_CARD_INT) 187 gap_ctrl |= 0x8; 188 else 189 gap_ctrl &= ~0x8; 190 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 191 } 192 } 193 194 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 195 { 196 bool status; 197 u32 reg; 198 199 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 200 status = !!(reg & SDHCI_CLOCK_CARD_EN); 201 202 if (status == enable) 203 return status; 204 205 if (enable) 206 reg |= SDHCI_CLOCK_CARD_EN; 207 else 208 reg &= ~SDHCI_CLOCK_CARD_EN; 209 210 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 211 212 return status; 213 } 214 215 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 216 { 217 bool is_tuning_cmd = 0; 218 bool clk_enabled; 219 u8 cmd; 220 221 if (reg == SDHCI_COMMAND) { 222 cmd = SDHCI_GET_CMD(val); 223 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 224 cmd == MMC_SEND_TUNING_BLOCK_HS200; 225 } 226 227 if (is_tuning_cmd) 228 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 229 230 writew(val, host->ioaddr + reg); 231 232 if (is_tuning_cmd) { 233 udelay(1); 234 tegra_sdhci_configure_card_clk(host, clk_enabled); 235 } 236 } 237 238 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 239 { 240 return mmc_gpio_get_ro(host->mmc); 241 } 242 243 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 244 { 245 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 246 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 247 int has_1v8, has_3v3; 248 249 /* 250 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 251 * voltage configuration in order to perform voltage switching. This 252 * means that valid pinctrl info is required on SDHCI instances capable 253 * of performing voltage switching. Whether or not an SDHCI instance is 254 * capable of voltage switching is determined based on the regulator. 255 */ 256 257 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 258 return true; 259 260 if (IS_ERR(host->mmc->supply.vqmmc)) 261 return false; 262 263 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 264 1700000, 1950000); 265 266 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 267 2700000, 3600000); 268 269 if (has_1v8 == 1 && has_3v3 == 1) 270 return tegra_host->pad_control_available; 271 272 /* Fixed voltage, no pad control required. */ 273 return true; 274 } 275 276 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 277 { 278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 279 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 280 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 281 bool card_clk_enabled = false; 282 u32 reg; 283 284 /* 285 * Touching the tap values is a bit tricky on some SoC generations. 286 * The quirk enables a workaround for a glitch that sometimes occurs if 287 * the tap values are changed. 288 */ 289 290 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 291 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 292 293 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 294 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 295 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 296 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 297 298 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 299 card_clk_enabled) { 300 udelay(1); 301 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 302 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 303 } 304 } 305 306 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 307 struct mmc_ios *ios) 308 { 309 struct sdhci_host *host = mmc_priv(mmc); 310 u32 val; 311 312 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 313 314 if (ios->enhanced_strobe) 315 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 316 else 317 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 318 319 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 320 321 } 322 323 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 324 { 325 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 326 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 327 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 328 u32 misc_ctrl, clk_ctrl, pad_ctrl; 329 330 sdhci_reset(host, mask); 331 332 if (!(mask & SDHCI_RESET_ALL)) 333 return; 334 335 tegra_sdhci_set_tap(host, tegra_host->default_tap); 336 337 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 338 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 339 340 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 341 SDHCI_MISC_CTRL_ENABLE_SDR50 | 342 SDHCI_MISC_CTRL_ENABLE_DDR50 | 343 SDHCI_MISC_CTRL_ENABLE_SDR104); 344 345 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 346 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 347 348 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 349 /* Erratum: Enable SDHCI spec v3.00 support */ 350 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 351 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 352 /* Advertise UHS modes as supported by host */ 353 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 354 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 355 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 356 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 357 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 358 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 359 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 360 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 361 } 362 363 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 364 365 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 366 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 367 368 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 369 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 370 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 371 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 372 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 373 374 tegra_host->pad_calib_required = true; 375 } 376 377 tegra_host->ddr_signaling = false; 378 } 379 380 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 381 { 382 u32 val; 383 384 /* 385 * Enable or disable the additional I/O pad used by the drive strength 386 * calibration process. 387 */ 388 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 389 390 if (enable) 391 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 392 else 393 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 394 395 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 396 397 if (enable) 398 usleep_range(1, 2); 399 } 400 401 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 402 u16 pdpu) 403 { 404 u32 reg; 405 406 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 407 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 408 reg |= pdpu; 409 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 410 } 411 412 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 413 { 414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 415 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 416 struct sdhci_tegra_autocal_offsets offsets = 417 tegra_host->autocal_offsets; 418 struct mmc_ios *ios = &host->mmc->ios; 419 bool card_clk_enabled; 420 u16 pdpu; 421 u32 reg; 422 int ret; 423 424 switch (ios->timing) { 425 case MMC_TIMING_UHS_SDR104: 426 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 427 break; 428 case MMC_TIMING_MMC_HS400: 429 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 430 break; 431 default: 432 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 433 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 434 else 435 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 436 } 437 438 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 439 440 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 441 442 tegra_sdhci_configure_cal_pad(host, true); 443 444 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 445 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 446 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 447 448 usleep_range(1, 2); 449 /* 10 ms timeout */ 450 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 451 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 452 1000, 10000); 453 454 tegra_sdhci_configure_cal_pad(host, false); 455 456 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 457 458 if (ret) { 459 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 460 461 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 462 pdpu = offsets.pull_down_1v8_timeout << 8 | 463 offsets.pull_up_1v8_timeout; 464 else 465 pdpu = offsets.pull_down_3v3_timeout << 8 | 466 offsets.pull_up_3v3_timeout; 467 468 /* Disable automatic calibration and use fixed offsets */ 469 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 470 reg &= ~SDHCI_AUTO_CAL_ENABLE; 471 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 472 473 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 474 } 475 } 476 477 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 478 { 479 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 480 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 481 struct sdhci_tegra_autocal_offsets *autocal = 482 &tegra_host->autocal_offsets; 483 int err; 484 485 err = device_property_read_u32(host->mmc->parent, 486 "nvidia,pad-autocal-pull-up-offset-3v3", 487 &autocal->pull_up_3v3); 488 if (err) 489 autocal->pull_up_3v3 = 0; 490 491 err = device_property_read_u32(host->mmc->parent, 492 "nvidia,pad-autocal-pull-down-offset-3v3", 493 &autocal->pull_down_3v3); 494 if (err) 495 autocal->pull_down_3v3 = 0; 496 497 err = device_property_read_u32(host->mmc->parent, 498 "nvidia,pad-autocal-pull-up-offset-1v8", 499 &autocal->pull_up_1v8); 500 if (err) 501 autocal->pull_up_1v8 = 0; 502 503 err = device_property_read_u32(host->mmc->parent, 504 "nvidia,pad-autocal-pull-down-offset-1v8", 505 &autocal->pull_down_1v8); 506 if (err) 507 autocal->pull_down_1v8 = 0; 508 509 err = device_property_read_u32(host->mmc->parent, 510 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 511 &autocal->pull_up_3v3); 512 if (err) 513 autocal->pull_up_3v3_timeout = 0; 514 515 err = device_property_read_u32(host->mmc->parent, 516 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 517 &autocal->pull_down_3v3); 518 if (err) 519 autocal->pull_down_3v3_timeout = 0; 520 521 err = device_property_read_u32(host->mmc->parent, 522 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 523 &autocal->pull_up_1v8); 524 if (err) 525 autocal->pull_up_1v8_timeout = 0; 526 527 err = device_property_read_u32(host->mmc->parent, 528 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 529 &autocal->pull_down_1v8); 530 if (err) 531 autocal->pull_down_1v8_timeout = 0; 532 533 err = device_property_read_u32(host->mmc->parent, 534 "nvidia,pad-autocal-pull-up-offset-sdr104", 535 &autocal->pull_up_sdr104); 536 if (err) 537 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 538 539 err = device_property_read_u32(host->mmc->parent, 540 "nvidia,pad-autocal-pull-down-offset-sdr104", 541 &autocal->pull_down_sdr104); 542 if (err) 543 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 544 545 err = device_property_read_u32(host->mmc->parent, 546 "nvidia,pad-autocal-pull-up-offset-hs400", 547 &autocal->pull_up_hs400); 548 if (err) 549 autocal->pull_up_hs400 = autocal->pull_up_1v8; 550 551 err = device_property_read_u32(host->mmc->parent, 552 "nvidia,pad-autocal-pull-down-offset-hs400", 553 &autocal->pull_down_hs400); 554 if (err) 555 autocal->pull_down_hs400 = autocal->pull_down_1v8; 556 } 557 558 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 559 { 560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 561 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 562 int err; 563 564 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 565 &tegra_host->default_tap); 566 if (err) 567 tegra_host->default_tap = 0; 568 569 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 570 &tegra_host->default_trim); 571 if (err) 572 tegra_host->default_trim = 0; 573 574 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 575 &tegra_host->dqs_trim); 576 if (err) 577 tegra_host->dqs_trim = 0x11; 578 } 579 580 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 581 { 582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 583 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 584 unsigned long host_clk; 585 586 if (!clock) 587 return sdhci_set_clock(host, clock); 588 589 /* 590 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 591 * divider to be configured to divided the host clock by two. The SDHCI 592 * clock divider is calculated as part of sdhci_set_clock() by 593 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 594 * the requested clock rate. 595 * 596 * By setting the host->max_clk to clock * 2 the divider calculation 597 * will always result in the correct value for DDR50/52 modes, 598 * regardless of clock rate rounding, which may happen if the value 599 * from clk_get_rate() is used. 600 */ 601 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 602 clk_set_rate(pltfm_host->clk, host_clk); 603 if (tegra_host->ddr_signaling) 604 host->max_clk = host_clk; 605 else 606 host->max_clk = clk_get_rate(pltfm_host->clk); 607 608 sdhci_set_clock(host, clock); 609 610 if (tegra_host->pad_calib_required) { 611 tegra_sdhci_pad_autocalib(host); 612 tegra_host->pad_calib_required = false; 613 } 614 } 615 616 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 617 { 618 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 619 620 return clk_round_rate(pltfm_host->clk, UINT_MAX); 621 } 622 623 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 624 { 625 u32 val; 626 627 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 628 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 629 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 630 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 631 } 632 633 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 634 { 635 u32 reg; 636 int err; 637 638 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 639 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 640 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 641 642 /* 1 ms sleep, 5 ms timeout */ 643 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 644 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 645 1000, 5000); 646 if (err) 647 dev_err(mmc_dev(host->mmc), 648 "HS400 delay line calibration timed out\n"); 649 } 650 651 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 652 unsigned timing) 653 { 654 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 655 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 656 bool set_default_tap = false; 657 bool set_dqs_trim = false; 658 bool do_hs400_dll_cal = false; 659 660 switch (timing) { 661 case MMC_TIMING_UHS_SDR50: 662 case MMC_TIMING_UHS_SDR104: 663 case MMC_TIMING_MMC_HS200: 664 /* Don't set default tap on tunable modes. */ 665 break; 666 case MMC_TIMING_MMC_HS400: 667 set_dqs_trim = true; 668 do_hs400_dll_cal = true; 669 break; 670 case MMC_TIMING_MMC_DDR52: 671 case MMC_TIMING_UHS_DDR50: 672 tegra_host->ddr_signaling = true; 673 set_default_tap = true; 674 break; 675 default: 676 set_default_tap = true; 677 break; 678 } 679 680 sdhci_set_uhs_signaling(host, timing); 681 682 tegra_sdhci_pad_autocalib(host); 683 684 if (set_default_tap) 685 tegra_sdhci_set_tap(host, tegra_host->default_tap); 686 687 if (set_dqs_trim) 688 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 689 690 if (do_hs400_dll_cal) 691 tegra_sdhci_hs400_dll_cal(host); 692 } 693 694 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 695 { 696 unsigned int min, max; 697 698 /* 699 * Start search for minimum tap value at 10, as smaller values are 700 * may wrongly be reported as working but fail at higher speeds, 701 * according to the TRM. 702 */ 703 min = 10; 704 while (min < 255) { 705 tegra_sdhci_set_tap(host, min); 706 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 707 break; 708 min++; 709 } 710 711 /* Find the maximum tap value that still passes. */ 712 max = min + 1; 713 while (max < 255) { 714 tegra_sdhci_set_tap(host, max); 715 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 716 max--; 717 break; 718 } 719 max++; 720 } 721 722 /* The TRM states the ideal tap value is at 75% in the passing range. */ 723 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 724 725 return mmc_send_tuning(host->mmc, opcode, NULL); 726 } 727 728 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 729 { 730 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 731 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 732 int ret; 733 734 if (!tegra_host->pad_control_available) 735 return 0; 736 737 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 738 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 739 tegra_host->pinctrl_state_1v8); 740 if (ret < 0) 741 dev_err(mmc_dev(host->mmc), 742 "setting 1.8V failed, ret: %d\n", ret); 743 } else { 744 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 745 tegra_host->pinctrl_state_3v3); 746 if (ret < 0) 747 dev_err(mmc_dev(host->mmc), 748 "setting 3.3V failed, ret: %d\n", ret); 749 } 750 751 return ret; 752 } 753 754 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 755 struct mmc_ios *ios) 756 { 757 struct sdhci_host *host = mmc_priv(mmc); 758 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 759 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 760 int ret = 0; 761 762 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 763 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 764 if (ret < 0) 765 return ret; 766 ret = sdhci_start_signal_voltage_switch(mmc, ios); 767 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 768 ret = sdhci_start_signal_voltage_switch(mmc, ios); 769 if (ret < 0) 770 return ret; 771 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 772 } 773 774 if (tegra_host->pad_calib_required) 775 tegra_sdhci_pad_autocalib(host); 776 777 return ret; 778 } 779 780 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 781 struct sdhci_tegra *tegra_host) 782 { 783 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 784 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 785 dev_dbg(dev, "No pinctrl info, err: %ld\n", 786 PTR_ERR(tegra_host->pinctrl_sdmmc)); 787 return -1; 788 } 789 790 tegra_host->pinctrl_state_3v3 = 791 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 792 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 793 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 794 PTR_ERR(tegra_host->pinctrl_state_3v3)); 795 return -1; 796 } 797 798 tegra_host->pinctrl_state_1v8 = 799 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 800 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 801 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 802 PTR_ERR(tegra_host->pinctrl_state_3v3)); 803 return -1; 804 } 805 806 tegra_host->pad_control_available = true; 807 808 return 0; 809 } 810 811 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 812 { 813 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 814 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 815 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 816 817 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 818 tegra_host->pad_calib_required = true; 819 } 820 821 static const struct sdhci_ops tegra_sdhci_ops = { 822 .get_ro = tegra_sdhci_get_ro, 823 .read_w = tegra_sdhci_readw, 824 .write_l = tegra_sdhci_writel, 825 .set_clock = tegra_sdhci_set_clock, 826 .set_bus_width = sdhci_set_bus_width, 827 .reset = tegra_sdhci_reset, 828 .platform_execute_tuning = tegra_sdhci_execute_tuning, 829 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 830 .voltage_switch = tegra_sdhci_voltage_switch, 831 .get_max_clock = tegra_sdhci_get_max_clock, 832 }; 833 834 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 835 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 836 SDHCI_QUIRK_SINGLE_POWER_WRITE | 837 SDHCI_QUIRK_NO_HISPD_BIT | 838 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 839 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 840 .ops = &tegra_sdhci_ops, 841 }; 842 843 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 844 .pdata = &sdhci_tegra20_pdata, 845 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 846 NVQUIRK_ENABLE_BLOCK_GAP_DET, 847 }; 848 849 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 850 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 851 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 852 SDHCI_QUIRK_SINGLE_POWER_WRITE | 853 SDHCI_QUIRK_NO_HISPD_BIT | 854 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 855 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 856 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 857 SDHCI_QUIRK2_BROKEN_HS200 | 858 /* 859 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 860 * though no command operation was in progress." 861 * 862 * The exact reason is unknown, as the same hardware seems 863 * to support Auto CMD23 on a downstream 3.1 kernel. 864 */ 865 SDHCI_QUIRK2_ACMD23_BROKEN, 866 .ops = &tegra_sdhci_ops, 867 }; 868 869 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 870 .pdata = &sdhci_tegra30_pdata, 871 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 872 NVQUIRK_ENABLE_SDR50 | 873 NVQUIRK_ENABLE_SDR104 | 874 NVQUIRK_HAS_PADCALIB, 875 }; 876 877 static const struct sdhci_ops tegra114_sdhci_ops = { 878 .get_ro = tegra_sdhci_get_ro, 879 .read_w = tegra_sdhci_readw, 880 .write_w = tegra_sdhci_writew, 881 .write_l = tegra_sdhci_writel, 882 .set_clock = tegra_sdhci_set_clock, 883 .set_bus_width = sdhci_set_bus_width, 884 .reset = tegra_sdhci_reset, 885 .platform_execute_tuning = tegra_sdhci_execute_tuning, 886 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 887 .voltage_switch = tegra_sdhci_voltage_switch, 888 .get_max_clock = tegra_sdhci_get_max_clock, 889 }; 890 891 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 892 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 893 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 894 SDHCI_QUIRK_SINGLE_POWER_WRITE | 895 SDHCI_QUIRK_NO_HISPD_BIT | 896 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 897 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 898 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 899 .ops = &tegra114_sdhci_ops, 900 }; 901 902 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 903 .pdata = &sdhci_tegra114_pdata, 904 }; 905 906 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 907 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 908 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 909 SDHCI_QUIRK_SINGLE_POWER_WRITE | 910 SDHCI_QUIRK_NO_HISPD_BIT | 911 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 912 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 913 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 914 /* 915 * The TRM states that the SD/MMC controller found on 916 * Tegra124 can address 34 bits (the maximum supported by 917 * the Tegra memory controller), but tests show that DMA 918 * to or from above 4 GiB doesn't work. This is possibly 919 * caused by missing programming, though it's not obvious 920 * what sequence is required. Mark 64-bit DMA broken for 921 * now to fix this for existing users (e.g. Nyan boards). 922 */ 923 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 924 .ops = &tegra114_sdhci_ops, 925 }; 926 927 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 928 .pdata = &sdhci_tegra124_pdata, 929 }; 930 931 static const struct sdhci_ops tegra210_sdhci_ops = { 932 .get_ro = tegra_sdhci_get_ro, 933 .read_w = tegra_sdhci_readw, 934 .write_w = tegra210_sdhci_writew, 935 .write_l = tegra_sdhci_writel, 936 .set_clock = tegra_sdhci_set_clock, 937 .set_bus_width = sdhci_set_bus_width, 938 .reset = tegra_sdhci_reset, 939 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 940 .voltage_switch = tegra_sdhci_voltage_switch, 941 .get_max_clock = tegra_sdhci_get_max_clock, 942 }; 943 944 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 945 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 946 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 947 SDHCI_QUIRK_SINGLE_POWER_WRITE | 948 SDHCI_QUIRK_NO_HISPD_BIT | 949 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 950 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 951 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 952 .ops = &tegra210_sdhci_ops, 953 }; 954 955 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 956 .pdata = &sdhci_tegra210_pdata, 957 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 958 NVQUIRK_HAS_PADCALIB | 959 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 960 NVQUIRK_ENABLE_SDR50 | 961 NVQUIRK_ENABLE_SDR104, 962 }; 963 964 static const struct sdhci_ops tegra186_sdhci_ops = { 965 .get_ro = tegra_sdhci_get_ro, 966 .read_w = tegra_sdhci_readw, 967 .write_l = tegra_sdhci_writel, 968 .set_clock = tegra_sdhci_set_clock, 969 .set_bus_width = sdhci_set_bus_width, 970 .reset = tegra_sdhci_reset, 971 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 972 .voltage_switch = tegra_sdhci_voltage_switch, 973 .get_max_clock = tegra_sdhci_get_max_clock, 974 }; 975 976 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 977 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 978 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 979 SDHCI_QUIRK_SINGLE_POWER_WRITE | 980 SDHCI_QUIRK_NO_HISPD_BIT | 981 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 982 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 983 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 984 /* SDHCI controllers on Tegra186 support 40-bit addressing. 985 * IOVA addresses are 48-bit wide on Tegra186. 986 * With 64-bit dma mask used for SDHCI, accesses can 987 * be broken. Disable 64-bit dma, which would fall back 988 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 989 * But it is not supported as of now. 990 */ 991 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 992 .ops = &tegra186_sdhci_ops, 993 }; 994 995 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 996 .pdata = &sdhci_tegra186_pdata, 997 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 998 NVQUIRK_HAS_PADCALIB | 999 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1000 NVQUIRK_ENABLE_SDR50 | 1001 NVQUIRK_ENABLE_SDR104, 1002 }; 1003 1004 static const struct of_device_id sdhci_tegra_dt_match[] = { 1005 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1006 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1007 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1008 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1009 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1010 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1011 {} 1012 }; 1013 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1014 1015 static int sdhci_tegra_probe(struct platform_device *pdev) 1016 { 1017 const struct of_device_id *match; 1018 const struct sdhci_tegra_soc_data *soc_data; 1019 struct sdhci_host *host; 1020 struct sdhci_pltfm_host *pltfm_host; 1021 struct sdhci_tegra *tegra_host; 1022 struct clk *clk; 1023 int rc; 1024 1025 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1026 if (!match) 1027 return -EINVAL; 1028 soc_data = match->data; 1029 1030 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1031 if (IS_ERR(host)) 1032 return PTR_ERR(host); 1033 pltfm_host = sdhci_priv(host); 1034 1035 tegra_host = sdhci_pltfm_priv(pltfm_host); 1036 tegra_host->ddr_signaling = false; 1037 tegra_host->pad_calib_required = false; 1038 tegra_host->pad_control_available = false; 1039 tegra_host->soc_data = soc_data; 1040 1041 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1042 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1043 if (rc == 0) 1044 host->mmc_host_ops.start_signal_voltage_switch = 1045 sdhci_tegra_start_signal_voltage_switch; 1046 } 1047 1048 host->mmc_host_ops.hs400_enhanced_strobe = 1049 tegra_sdhci_hs400_enhanced_strobe; 1050 1051 rc = mmc_of_parse(host->mmc); 1052 if (rc) 1053 goto err_parse_dt; 1054 1055 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1056 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1057 1058 tegra_sdhci_parse_pad_autocal_dt(host); 1059 1060 tegra_sdhci_parse_tap_and_trim(host); 1061 1062 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1063 GPIOD_OUT_HIGH); 1064 if (IS_ERR(tegra_host->power_gpio)) { 1065 rc = PTR_ERR(tegra_host->power_gpio); 1066 goto err_power_req; 1067 } 1068 1069 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1070 if (IS_ERR(clk)) { 1071 dev_err(mmc_dev(host->mmc), "clk err\n"); 1072 rc = PTR_ERR(clk); 1073 goto err_clk_get; 1074 } 1075 clk_prepare_enable(clk); 1076 pltfm_host->clk = clk; 1077 1078 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1079 "sdhci"); 1080 if (IS_ERR(tegra_host->rst)) { 1081 rc = PTR_ERR(tegra_host->rst); 1082 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1083 goto err_rst_get; 1084 } 1085 1086 rc = reset_control_assert(tegra_host->rst); 1087 if (rc) 1088 goto err_rst_get; 1089 1090 usleep_range(2000, 4000); 1091 1092 rc = reset_control_deassert(tegra_host->rst); 1093 if (rc) 1094 goto err_rst_get; 1095 1096 usleep_range(2000, 4000); 1097 1098 rc = sdhci_add_host(host); 1099 if (rc) 1100 goto err_add_host; 1101 1102 return 0; 1103 1104 err_add_host: 1105 reset_control_assert(tegra_host->rst); 1106 err_rst_get: 1107 clk_disable_unprepare(pltfm_host->clk); 1108 err_clk_get: 1109 err_power_req: 1110 err_parse_dt: 1111 sdhci_pltfm_free(pdev); 1112 return rc; 1113 } 1114 1115 static int sdhci_tegra_remove(struct platform_device *pdev) 1116 { 1117 struct sdhci_host *host = platform_get_drvdata(pdev); 1118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1119 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1120 1121 sdhci_remove_host(host, 0); 1122 1123 reset_control_assert(tegra_host->rst); 1124 usleep_range(2000, 4000); 1125 clk_disable_unprepare(pltfm_host->clk); 1126 1127 sdhci_pltfm_free(pdev); 1128 1129 return 0; 1130 } 1131 1132 static struct platform_driver sdhci_tegra_driver = { 1133 .driver = { 1134 .name = "sdhci-tegra", 1135 .of_match_table = sdhci_tegra_dt_match, 1136 .pm = &sdhci_pltfm_pmops, 1137 }, 1138 .probe = sdhci_tegra_probe, 1139 .remove = sdhci_tegra_remove, 1140 }; 1141 1142 module_platform_driver(sdhci_tegra_driver); 1143 1144 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1145 MODULE_AUTHOR("Google, Inc."); 1146 MODULE_LICENSE("GPL v2"); 1147