1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 51 #define SDHCI_AUTO_CAL_START BIT(31) 52 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 53 54 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 55 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 56 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 57 58 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 59 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 60 61 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 62 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 63 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 64 #define NVQUIRK_ENABLE_SDR50 BIT(3) 65 #define NVQUIRK_ENABLE_SDR104 BIT(4) 66 #define NVQUIRK_ENABLE_DDR50 BIT(5) 67 #define NVQUIRK_HAS_PADCALIB BIT(6) 68 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 69 70 struct sdhci_tegra_soc_data { 71 const struct sdhci_pltfm_data *pdata; 72 u32 nvquirks; 73 }; 74 75 struct sdhci_tegra { 76 const struct sdhci_tegra_soc_data *soc_data; 77 struct gpio_desc *power_gpio; 78 bool ddr_signaling; 79 bool pad_calib_required; 80 bool pad_control_available; 81 82 struct reset_control *rst; 83 struct pinctrl *pinctrl_sdmmc; 84 struct pinctrl_state *pinctrl_state_3v3; 85 struct pinctrl_state *pinctrl_state_1v8; 86 }; 87 88 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 89 { 90 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 91 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 92 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 93 94 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 95 (reg == SDHCI_HOST_VERSION))) { 96 /* Erratum: Version register is invalid in HW. */ 97 return SDHCI_SPEC_200; 98 } 99 100 return readw(host->ioaddr + reg); 101 } 102 103 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 104 { 105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 106 107 switch (reg) { 108 case SDHCI_TRANSFER_MODE: 109 /* 110 * Postpone this write, we must do it together with a 111 * command write that is down below. 112 */ 113 pltfm_host->xfer_mode_shadow = val; 114 return; 115 case SDHCI_COMMAND: 116 writel((val << 16) | pltfm_host->xfer_mode_shadow, 117 host->ioaddr + SDHCI_TRANSFER_MODE); 118 return; 119 } 120 121 writew(val, host->ioaddr + reg); 122 } 123 124 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 125 { 126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 127 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 128 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 129 130 /* Seems like we're getting spurious timeout and crc errors, so 131 * disable signalling of them. In case of real errors software 132 * timers should take care of eventually detecting them. 133 */ 134 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 135 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 136 137 writel(val, host->ioaddr + reg); 138 139 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 140 (reg == SDHCI_INT_ENABLE))) { 141 /* Erratum: Must enable block gap interrupt detection */ 142 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 143 if (val & SDHCI_INT_CARD_INT) 144 gap_ctrl |= 0x8; 145 else 146 gap_ctrl &= ~0x8; 147 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 148 } 149 } 150 151 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 152 { 153 return mmc_gpio_get_ro(host->mmc); 154 } 155 156 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 157 { 158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 160 int has_1v8, has_3v3; 161 162 /* 163 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 164 * voltage configuration in order to perform voltage switching. This 165 * means that valid pinctrl info is required on SDHCI instances capable 166 * of performing voltage switching. Whether or not an SDHCI instance is 167 * capable of voltage switching is determined based on the regulator. 168 */ 169 170 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 171 return true; 172 173 if (IS_ERR(host->mmc->supply.vqmmc)) 174 return false; 175 176 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 177 1700000, 1950000); 178 179 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 180 2700000, 3600000); 181 182 if (has_1v8 == 1 && has_3v3 == 1) 183 return tegra_host->pad_control_available; 184 185 /* Fixed voltage, no pad control required. */ 186 return true; 187 } 188 189 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 190 { 191 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 192 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 193 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 194 u32 misc_ctrl, clk_ctrl, pad_ctrl; 195 196 sdhci_reset(host, mask); 197 198 if (!(mask & SDHCI_RESET_ALL)) 199 return; 200 201 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 202 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 203 204 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 205 SDHCI_MISC_CTRL_ENABLE_SDR50 | 206 SDHCI_MISC_CTRL_ENABLE_DDR50 | 207 SDHCI_MISC_CTRL_ENABLE_SDR104); 208 209 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 210 211 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 212 /* Erratum: Enable SDHCI spec v3.00 support */ 213 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 214 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 215 /* Advertise UHS modes as supported by host */ 216 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 217 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 218 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 219 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 220 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 221 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 222 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 223 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 224 } 225 226 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 227 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 228 229 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 230 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 231 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 232 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 233 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 234 235 tegra_host->pad_calib_required = true; 236 } 237 238 tegra_host->ddr_signaling = false; 239 } 240 241 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 242 { 243 u32 reg; 244 int ret; 245 246 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 247 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 248 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 249 250 usleep_range(1, 2); 251 /* 10 ms timeout */ 252 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 253 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 254 1000, 10000); 255 256 if (ret) 257 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 258 } 259 260 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 261 { 262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 263 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 264 unsigned long host_clk; 265 266 if (!clock) 267 return sdhci_set_clock(host, clock); 268 269 /* 270 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 271 * divider to be configured to divided the host clock by two. The SDHCI 272 * clock divider is calculated as part of sdhci_set_clock() by 273 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 274 * the requested clock rate. 275 * 276 * By setting the host->max_clk to clock * 2 the divider calculation 277 * will always result in the correct value for DDR50/52 modes, 278 * regardless of clock rate rounding, which may happen if the value 279 * from clk_get_rate() is used. 280 */ 281 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 282 clk_set_rate(pltfm_host->clk, host_clk); 283 if (tegra_host->ddr_signaling) 284 host->max_clk = host_clk; 285 else 286 host->max_clk = clk_get_rate(pltfm_host->clk); 287 288 sdhci_set_clock(host, clock); 289 290 if (tegra_host->pad_calib_required) { 291 tegra_sdhci_pad_autocalib(host); 292 tegra_host->pad_calib_required = false; 293 } 294 } 295 296 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 297 unsigned timing) 298 { 299 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 300 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 301 302 if (timing == MMC_TIMING_UHS_DDR50 || 303 timing == MMC_TIMING_MMC_DDR52) 304 tegra_host->ddr_signaling = true; 305 306 sdhci_set_uhs_signaling(host, timing); 307 } 308 309 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 310 { 311 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 312 313 return clk_round_rate(pltfm_host->clk, UINT_MAX); 314 } 315 316 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 317 { 318 u32 reg; 319 320 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 321 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 322 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 323 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 324 } 325 326 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 327 { 328 unsigned int min, max; 329 330 /* 331 * Start search for minimum tap value at 10, as smaller values are 332 * may wrongly be reported as working but fail at higher speeds, 333 * according to the TRM. 334 */ 335 min = 10; 336 while (min < 255) { 337 tegra_sdhci_set_tap(host, min); 338 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 339 break; 340 min++; 341 } 342 343 /* Find the maximum tap value that still passes. */ 344 max = min + 1; 345 while (max < 255) { 346 tegra_sdhci_set_tap(host, max); 347 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 348 max--; 349 break; 350 } 351 max++; 352 } 353 354 /* The TRM states the ideal tap value is at 75% in the passing range. */ 355 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 356 357 return mmc_send_tuning(host->mmc, opcode, NULL); 358 } 359 360 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 361 { 362 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 363 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 364 int ret; 365 366 if (!tegra_host->pad_control_available) 367 return 0; 368 369 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 370 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 371 tegra_host->pinctrl_state_1v8); 372 if (ret < 0) 373 dev_err(mmc_dev(host->mmc), 374 "setting 1.8V failed, ret: %d\n", ret); 375 } else { 376 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 377 tegra_host->pinctrl_state_3v3); 378 if (ret < 0) 379 dev_err(mmc_dev(host->mmc), 380 "setting 3.3V failed, ret: %d\n", ret); 381 } 382 383 return ret; 384 } 385 386 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 387 struct mmc_ios *ios) 388 { 389 struct sdhci_host *host = mmc_priv(mmc); 390 int ret = 0; 391 392 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 393 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 394 if (ret < 0) 395 return ret; 396 ret = sdhci_start_signal_voltage_switch(mmc, ios); 397 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 398 ret = sdhci_start_signal_voltage_switch(mmc, ios); 399 if (ret < 0) 400 return ret; 401 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 402 } 403 404 return ret; 405 } 406 407 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 408 struct sdhci_tegra *tegra_host) 409 { 410 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 411 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 412 dev_dbg(dev, "No pinctrl info, err: %ld\n", 413 PTR_ERR(tegra_host->pinctrl_sdmmc)); 414 return -1; 415 } 416 417 tegra_host->pinctrl_state_3v3 = 418 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 419 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 420 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 421 PTR_ERR(tegra_host->pinctrl_state_3v3)); 422 return -1; 423 } 424 425 tegra_host->pinctrl_state_1v8 = 426 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 427 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 428 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 429 PTR_ERR(tegra_host->pinctrl_state_3v3)); 430 return -1; 431 } 432 433 tegra_host->pad_control_available = true; 434 435 return 0; 436 } 437 438 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 439 { 440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 441 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 442 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 443 444 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 445 tegra_host->pad_calib_required = true; 446 } 447 448 static const struct sdhci_ops tegra_sdhci_ops = { 449 .get_ro = tegra_sdhci_get_ro, 450 .read_w = tegra_sdhci_readw, 451 .write_l = tegra_sdhci_writel, 452 .set_clock = tegra_sdhci_set_clock, 453 .set_bus_width = sdhci_set_bus_width, 454 .reset = tegra_sdhci_reset, 455 .platform_execute_tuning = tegra_sdhci_execute_tuning, 456 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 457 .voltage_switch = tegra_sdhci_voltage_switch, 458 .get_max_clock = tegra_sdhci_get_max_clock, 459 }; 460 461 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 462 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 463 SDHCI_QUIRK_SINGLE_POWER_WRITE | 464 SDHCI_QUIRK_NO_HISPD_BIT | 465 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 466 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 467 .ops = &tegra_sdhci_ops, 468 }; 469 470 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 471 .pdata = &sdhci_tegra20_pdata, 472 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 473 NVQUIRK_ENABLE_BLOCK_GAP_DET, 474 }; 475 476 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 477 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 478 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 479 SDHCI_QUIRK_SINGLE_POWER_WRITE | 480 SDHCI_QUIRK_NO_HISPD_BIT | 481 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 482 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 483 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 484 SDHCI_QUIRK2_BROKEN_HS200 | 485 /* 486 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 487 * though no command operation was in progress." 488 * 489 * The exact reason is unknown, as the same hardware seems 490 * to support Auto CMD23 on a downstream 3.1 kernel. 491 */ 492 SDHCI_QUIRK2_ACMD23_BROKEN, 493 .ops = &tegra_sdhci_ops, 494 }; 495 496 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 497 .pdata = &sdhci_tegra30_pdata, 498 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 499 NVQUIRK_ENABLE_SDR50 | 500 NVQUIRK_ENABLE_SDR104 | 501 NVQUIRK_HAS_PADCALIB, 502 }; 503 504 static const struct sdhci_ops tegra114_sdhci_ops = { 505 .get_ro = tegra_sdhci_get_ro, 506 .read_w = tegra_sdhci_readw, 507 .write_w = tegra_sdhci_writew, 508 .write_l = tegra_sdhci_writel, 509 .set_clock = tegra_sdhci_set_clock, 510 .set_bus_width = sdhci_set_bus_width, 511 .reset = tegra_sdhci_reset, 512 .platform_execute_tuning = tegra_sdhci_execute_tuning, 513 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 514 .voltage_switch = tegra_sdhci_voltage_switch, 515 .get_max_clock = tegra_sdhci_get_max_clock, 516 }; 517 518 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 519 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 520 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 521 SDHCI_QUIRK_SINGLE_POWER_WRITE | 522 SDHCI_QUIRK_NO_HISPD_BIT | 523 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 524 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 525 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 526 .ops = &tegra114_sdhci_ops, 527 }; 528 529 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 530 .pdata = &sdhci_tegra114_pdata, 531 }; 532 533 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 534 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 535 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 536 SDHCI_QUIRK_SINGLE_POWER_WRITE | 537 SDHCI_QUIRK_NO_HISPD_BIT | 538 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 539 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 540 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 541 /* 542 * The TRM states that the SD/MMC controller found on 543 * Tegra124 can address 34 bits (the maximum supported by 544 * the Tegra memory controller), but tests show that DMA 545 * to or from above 4 GiB doesn't work. This is possibly 546 * caused by missing programming, though it's not obvious 547 * what sequence is required. Mark 64-bit DMA broken for 548 * now to fix this for existing users (e.g. Nyan boards). 549 */ 550 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 551 .ops = &tegra114_sdhci_ops, 552 }; 553 554 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 555 .pdata = &sdhci_tegra124_pdata, 556 }; 557 558 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 559 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 560 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 561 SDHCI_QUIRK_SINGLE_POWER_WRITE | 562 SDHCI_QUIRK_NO_HISPD_BIT | 563 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 564 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 565 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 566 .ops = &tegra114_sdhci_ops, 567 }; 568 569 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 570 .pdata = &sdhci_tegra210_pdata, 571 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 572 }; 573 574 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 575 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 576 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 577 SDHCI_QUIRK_SINGLE_POWER_WRITE | 578 SDHCI_QUIRK_NO_HISPD_BIT | 579 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 580 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 581 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 582 /* SDHCI controllers on Tegra186 support 40-bit addressing. 583 * IOVA addresses are 48-bit wide on Tegra186. 584 * With 64-bit dma mask used for SDHCI, accesses can 585 * be broken. Disable 64-bit dma, which would fall back 586 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 587 * But it is not supported as of now. 588 */ 589 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 590 .ops = &tegra114_sdhci_ops, 591 }; 592 593 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 594 .pdata = &sdhci_tegra186_pdata, 595 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 596 }; 597 598 static const struct of_device_id sdhci_tegra_dt_match[] = { 599 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 600 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 601 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 602 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 603 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 604 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 605 {} 606 }; 607 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 608 609 static int sdhci_tegra_probe(struct platform_device *pdev) 610 { 611 const struct of_device_id *match; 612 const struct sdhci_tegra_soc_data *soc_data; 613 struct sdhci_host *host; 614 struct sdhci_pltfm_host *pltfm_host; 615 struct sdhci_tegra *tegra_host; 616 struct clk *clk; 617 int rc; 618 619 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 620 if (!match) 621 return -EINVAL; 622 soc_data = match->data; 623 624 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 625 if (IS_ERR(host)) 626 return PTR_ERR(host); 627 pltfm_host = sdhci_priv(host); 628 629 tegra_host = sdhci_pltfm_priv(pltfm_host); 630 tegra_host->ddr_signaling = false; 631 tegra_host->pad_calib_required = false; 632 tegra_host->pad_control_available = false; 633 tegra_host->soc_data = soc_data; 634 635 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 636 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 637 if (rc == 0) 638 host->mmc_host_ops.start_signal_voltage_switch = 639 sdhci_tegra_start_signal_voltage_switch; 640 } 641 642 rc = mmc_of_parse(host->mmc); 643 if (rc) 644 goto err_parse_dt; 645 646 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 647 host->mmc->caps |= MMC_CAP_1_8V_DDR; 648 649 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 650 GPIOD_OUT_HIGH); 651 if (IS_ERR(tegra_host->power_gpio)) { 652 rc = PTR_ERR(tegra_host->power_gpio); 653 goto err_power_req; 654 } 655 656 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 657 if (IS_ERR(clk)) { 658 dev_err(mmc_dev(host->mmc), "clk err\n"); 659 rc = PTR_ERR(clk); 660 goto err_clk_get; 661 } 662 clk_prepare_enable(clk); 663 pltfm_host->clk = clk; 664 665 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 666 "sdhci"); 667 if (IS_ERR(tegra_host->rst)) { 668 rc = PTR_ERR(tegra_host->rst); 669 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 670 goto err_rst_get; 671 } 672 673 rc = reset_control_assert(tegra_host->rst); 674 if (rc) 675 goto err_rst_get; 676 677 usleep_range(2000, 4000); 678 679 rc = reset_control_deassert(tegra_host->rst); 680 if (rc) 681 goto err_rst_get; 682 683 usleep_range(2000, 4000); 684 685 rc = sdhci_add_host(host); 686 if (rc) 687 goto err_add_host; 688 689 return 0; 690 691 err_add_host: 692 reset_control_assert(tegra_host->rst); 693 err_rst_get: 694 clk_disable_unprepare(pltfm_host->clk); 695 err_clk_get: 696 err_power_req: 697 err_parse_dt: 698 sdhci_pltfm_free(pdev); 699 return rc; 700 } 701 702 static int sdhci_tegra_remove(struct platform_device *pdev) 703 { 704 struct sdhci_host *host = platform_get_drvdata(pdev); 705 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 706 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 707 708 sdhci_remove_host(host, 0); 709 710 reset_control_assert(tegra_host->rst); 711 usleep_range(2000, 4000); 712 clk_disable_unprepare(pltfm_host->clk); 713 714 sdhci_pltfm_free(pdev); 715 716 return 0; 717 } 718 719 static struct platform_driver sdhci_tegra_driver = { 720 .driver = { 721 .name = "sdhci-tegra", 722 .of_match_table = sdhci_tegra_dt_match, 723 .pm = &sdhci_pltfm_pmops, 724 }, 725 .probe = sdhci_tegra_probe, 726 .remove = sdhci_tegra_remove, 727 }; 728 729 module_platform_driver(sdhci_tegra_driver); 730 731 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 732 MODULE_AUTHOR("Google, Inc."); 733 MODULE_LICENSE("GPL v2"); 734