1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/slot-gpio.h> 28 29 #include <asm/gpio.h> 30 31 #include "sdhci-pltfm.h" 32 33 /* Tegra SDHOST controller vendor register definitions */ 34 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 35 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 36 37 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 38 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 39 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 40 41 struct sdhci_tegra_soc_data { 42 const struct sdhci_pltfm_data *pdata; 43 u32 nvquirks; 44 }; 45 46 struct sdhci_tegra { 47 const struct sdhci_tegra_soc_data *soc_data; 48 int power_gpio; 49 }; 50 51 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg) 52 { 53 u32 val; 54 55 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 56 /* Use wp_gpio here instead? */ 57 val = readl(host->ioaddr + reg); 58 return val | SDHCI_WRITE_PROTECT; 59 } 60 61 return readl(host->ioaddr + reg); 62 } 63 64 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 65 { 66 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 67 struct sdhci_tegra *tegra_host = pltfm_host->priv; 68 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 69 70 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 71 (reg == SDHCI_HOST_VERSION))) { 72 /* Erratum: Version register is invalid in HW. */ 73 return SDHCI_SPEC_200; 74 } 75 76 return readw(host->ioaddr + reg); 77 } 78 79 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 80 { 81 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 82 struct sdhci_tegra *tegra_host = pltfm_host->priv; 83 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 84 85 /* Seems like we're getting spurious timeout and crc errors, so 86 * disable signalling of them. In case of real errors software 87 * timers should take care of eventually detecting them. 88 */ 89 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 90 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 91 92 writel(val, host->ioaddr + reg); 93 94 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 95 (reg == SDHCI_INT_ENABLE))) { 96 /* Erratum: Must enable block gap interrupt detection */ 97 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 98 if (val & SDHCI_INT_CARD_INT) 99 gap_ctrl |= 0x8; 100 else 101 gap_ctrl &= ~0x8; 102 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 103 } 104 } 105 106 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 107 { 108 return mmc_gpio_get_ro(host->mmc); 109 } 110 111 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 112 { 113 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 114 struct sdhci_tegra *tegra_host = pltfm_host->priv; 115 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 116 117 sdhci_reset(host, mask); 118 119 if (!(mask & SDHCI_RESET_ALL)) 120 return; 121 122 /* Erratum: Enable SDHCI spec v3.00 support */ 123 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { 124 u32 misc_ctrl; 125 126 misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 127 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 128 sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 129 } 130 } 131 132 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 133 { 134 u32 ctrl; 135 136 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 137 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 138 (bus_width == MMC_BUS_WIDTH_8)) { 139 ctrl &= ~SDHCI_CTRL_4BITBUS; 140 ctrl |= SDHCI_CTRL_8BITBUS; 141 } else { 142 ctrl &= ~SDHCI_CTRL_8BITBUS; 143 if (bus_width == MMC_BUS_WIDTH_4) 144 ctrl |= SDHCI_CTRL_4BITBUS; 145 else 146 ctrl &= ~SDHCI_CTRL_4BITBUS; 147 } 148 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 149 } 150 151 static const struct sdhci_ops tegra_sdhci_ops = { 152 .get_ro = tegra_sdhci_get_ro, 153 .read_l = tegra_sdhci_readl, 154 .read_w = tegra_sdhci_readw, 155 .write_l = tegra_sdhci_writel, 156 .set_clock = sdhci_set_clock, 157 .set_bus_width = tegra_sdhci_set_bus_width, 158 .reset = tegra_sdhci_reset, 159 .set_uhs_signaling = sdhci_set_uhs_signaling, 160 }; 161 162 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 163 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 164 SDHCI_QUIRK_SINGLE_POWER_WRITE | 165 SDHCI_QUIRK_NO_HISPD_BIT | 166 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 167 .ops = &tegra_sdhci_ops, 168 }; 169 170 static struct sdhci_tegra_soc_data soc_data_tegra20 = { 171 .pdata = &sdhci_tegra20_pdata, 172 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 173 NVQUIRK_ENABLE_BLOCK_GAP_DET, 174 }; 175 176 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 177 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 178 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 179 SDHCI_QUIRK_SINGLE_POWER_WRITE | 180 SDHCI_QUIRK_NO_HISPD_BIT | 181 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 182 .ops = &tegra_sdhci_ops, 183 }; 184 185 static struct sdhci_tegra_soc_data soc_data_tegra30 = { 186 .pdata = &sdhci_tegra30_pdata, 187 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, 188 }; 189 190 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 191 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 192 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 193 SDHCI_QUIRK_SINGLE_POWER_WRITE | 194 SDHCI_QUIRK_NO_HISPD_BIT | 195 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 196 .ops = &tegra_sdhci_ops, 197 }; 198 199 static struct sdhci_tegra_soc_data soc_data_tegra114 = { 200 .pdata = &sdhci_tegra114_pdata, 201 }; 202 203 static const struct of_device_id sdhci_tegra_dt_match[] = { 204 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, 205 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 206 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 207 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 208 {} 209 }; 210 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 211 212 static int sdhci_tegra_parse_dt(struct device *dev) 213 { 214 struct device_node *np = dev->of_node; 215 struct sdhci_host *host = dev_get_drvdata(dev); 216 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 217 struct sdhci_tegra *tegra_host = pltfm_host->priv; 218 219 tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0); 220 return mmc_of_parse(host->mmc); 221 } 222 223 static int sdhci_tegra_probe(struct platform_device *pdev) 224 { 225 const struct of_device_id *match; 226 const struct sdhci_tegra_soc_data *soc_data; 227 struct sdhci_host *host; 228 struct sdhci_pltfm_host *pltfm_host; 229 struct sdhci_tegra *tegra_host; 230 struct clk *clk; 231 int rc; 232 233 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 234 if (!match) 235 return -EINVAL; 236 soc_data = match->data; 237 238 host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); 239 if (IS_ERR(host)) 240 return PTR_ERR(host); 241 pltfm_host = sdhci_priv(host); 242 243 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 244 if (!tegra_host) { 245 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 246 rc = -ENOMEM; 247 goto err_alloc_tegra_host; 248 } 249 tegra_host->soc_data = soc_data; 250 pltfm_host->priv = tegra_host; 251 252 rc = sdhci_tegra_parse_dt(&pdev->dev); 253 if (rc) 254 goto err_parse_dt; 255 256 if (gpio_is_valid(tegra_host->power_gpio)) { 257 rc = gpio_request(tegra_host->power_gpio, "sdhci_power"); 258 if (rc) { 259 dev_err(mmc_dev(host->mmc), 260 "failed to allocate power gpio\n"); 261 goto err_power_req; 262 } 263 gpio_direction_output(tegra_host->power_gpio, 1); 264 } 265 266 clk = clk_get(mmc_dev(host->mmc), NULL); 267 if (IS_ERR(clk)) { 268 dev_err(mmc_dev(host->mmc), "clk err\n"); 269 rc = PTR_ERR(clk); 270 goto err_clk_get; 271 } 272 clk_prepare_enable(clk); 273 pltfm_host->clk = clk; 274 275 rc = sdhci_add_host(host); 276 if (rc) 277 goto err_add_host; 278 279 return 0; 280 281 err_add_host: 282 clk_disable_unprepare(pltfm_host->clk); 283 clk_put(pltfm_host->clk); 284 err_clk_get: 285 if (gpio_is_valid(tegra_host->power_gpio)) 286 gpio_free(tegra_host->power_gpio); 287 err_power_req: 288 err_parse_dt: 289 err_alloc_tegra_host: 290 sdhci_pltfm_free(pdev); 291 return rc; 292 } 293 294 static int sdhci_tegra_remove(struct platform_device *pdev) 295 { 296 struct sdhci_host *host = platform_get_drvdata(pdev); 297 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 298 struct sdhci_tegra *tegra_host = pltfm_host->priv; 299 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 300 301 sdhci_remove_host(host, dead); 302 303 if (gpio_is_valid(tegra_host->power_gpio)) 304 gpio_free(tegra_host->power_gpio); 305 306 clk_disable_unprepare(pltfm_host->clk); 307 clk_put(pltfm_host->clk); 308 309 sdhci_pltfm_free(pdev); 310 311 return 0; 312 } 313 314 static struct platform_driver sdhci_tegra_driver = { 315 .driver = { 316 .name = "sdhci-tegra", 317 .owner = THIS_MODULE, 318 .of_match_table = sdhci_tegra_dt_match, 319 .pm = SDHCI_PLTFM_PMOPS, 320 }, 321 .probe = sdhci_tegra_probe, 322 .remove = sdhci_tegra_remove, 323 }; 324 325 module_platform_driver(sdhci_tegra_driver); 326 327 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 328 MODULE_AUTHOR("Google, Inc."); 329 MODULE_LICENSE("GPL v2"); 330