1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 51 #define SDHCI_AUTO_CAL_START BIT(31) 52 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 53 54 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 55 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 56 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 57 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 58 59 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 60 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 61 62 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 63 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 64 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 65 #define NVQUIRK_ENABLE_SDR50 BIT(3) 66 #define NVQUIRK_ENABLE_SDR104 BIT(4) 67 #define NVQUIRK_ENABLE_DDR50 BIT(5) 68 #define NVQUIRK_HAS_PADCALIB BIT(6) 69 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 70 71 struct sdhci_tegra_soc_data { 72 const struct sdhci_pltfm_data *pdata; 73 u32 nvquirks; 74 }; 75 76 struct sdhci_tegra { 77 const struct sdhci_tegra_soc_data *soc_data; 78 struct gpio_desc *power_gpio; 79 bool ddr_signaling; 80 bool pad_calib_required; 81 bool pad_control_available; 82 83 struct reset_control *rst; 84 struct pinctrl *pinctrl_sdmmc; 85 struct pinctrl_state *pinctrl_state_3v3; 86 struct pinctrl_state *pinctrl_state_1v8; 87 }; 88 89 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 90 { 91 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 92 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 93 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 94 95 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 96 (reg == SDHCI_HOST_VERSION))) { 97 /* Erratum: Version register is invalid in HW. */ 98 return SDHCI_SPEC_200; 99 } 100 101 return readw(host->ioaddr + reg); 102 } 103 104 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 105 { 106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 107 108 switch (reg) { 109 case SDHCI_TRANSFER_MODE: 110 /* 111 * Postpone this write, we must do it together with a 112 * command write that is down below. 113 */ 114 pltfm_host->xfer_mode_shadow = val; 115 return; 116 case SDHCI_COMMAND: 117 writel((val << 16) | pltfm_host->xfer_mode_shadow, 118 host->ioaddr + SDHCI_TRANSFER_MODE); 119 return; 120 } 121 122 writew(val, host->ioaddr + reg); 123 } 124 125 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 126 { 127 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 128 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 129 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 130 131 /* Seems like we're getting spurious timeout and crc errors, so 132 * disable signalling of them. In case of real errors software 133 * timers should take care of eventually detecting them. 134 */ 135 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 136 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 137 138 writel(val, host->ioaddr + reg); 139 140 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 141 (reg == SDHCI_INT_ENABLE))) { 142 /* Erratum: Must enable block gap interrupt detection */ 143 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 144 if (val & SDHCI_INT_CARD_INT) 145 gap_ctrl |= 0x8; 146 else 147 gap_ctrl &= ~0x8; 148 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 149 } 150 } 151 152 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 153 { 154 return mmc_gpio_get_ro(host->mmc); 155 } 156 157 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 158 { 159 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 160 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 161 int has_1v8, has_3v3; 162 163 /* 164 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 165 * voltage configuration in order to perform voltage switching. This 166 * means that valid pinctrl info is required on SDHCI instances capable 167 * of performing voltage switching. Whether or not an SDHCI instance is 168 * capable of voltage switching is determined based on the regulator. 169 */ 170 171 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 172 return true; 173 174 if (IS_ERR(host->mmc->supply.vqmmc)) 175 return false; 176 177 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 178 1700000, 1950000); 179 180 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 181 2700000, 3600000); 182 183 if (has_1v8 == 1 && has_3v3 == 1) 184 return tegra_host->pad_control_available; 185 186 /* Fixed voltage, no pad control required. */ 187 return true; 188 } 189 190 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 191 { 192 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 193 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 194 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 195 u32 misc_ctrl, clk_ctrl, pad_ctrl; 196 197 sdhci_reset(host, mask); 198 199 if (!(mask & SDHCI_RESET_ALL)) 200 return; 201 202 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 203 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 204 205 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 206 SDHCI_MISC_CTRL_ENABLE_SDR50 | 207 SDHCI_MISC_CTRL_ENABLE_DDR50 | 208 SDHCI_MISC_CTRL_ENABLE_SDR104); 209 210 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 211 212 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 213 /* Erratum: Enable SDHCI spec v3.00 support */ 214 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 215 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 216 /* Advertise UHS modes as supported by host */ 217 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 218 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 219 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 220 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 221 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 222 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 223 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 224 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 225 } 226 227 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 228 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 229 230 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 231 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 232 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 233 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 234 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 235 236 tegra_host->pad_calib_required = true; 237 } 238 239 tegra_host->ddr_signaling = false; 240 } 241 242 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 243 { 244 u32 val; 245 246 /* 247 * Enable or disable the additional I/O pad used by the drive strength 248 * calibration process. 249 */ 250 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 251 252 if (enable) 253 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 254 else 255 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 256 257 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 258 259 if (enable) 260 usleep_range(1, 2); 261 } 262 263 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 264 { 265 bool status; 266 u32 reg; 267 268 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 269 status = !!(reg & SDHCI_CLOCK_CARD_EN); 270 271 if (status == enable) 272 return status; 273 274 if (enable) 275 reg |= SDHCI_CLOCK_CARD_EN; 276 else 277 reg &= ~SDHCI_CLOCK_CARD_EN; 278 279 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 280 281 return status; 282 } 283 284 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 285 { 286 bool card_clk_enabled; 287 u32 reg; 288 int ret; 289 290 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 291 292 tegra_sdhci_configure_cal_pad(host, true); 293 294 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 295 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 296 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 297 298 usleep_range(1, 2); 299 /* 10 ms timeout */ 300 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 301 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 302 1000, 10000); 303 304 tegra_sdhci_configure_cal_pad(host, false); 305 306 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 307 308 if (ret) 309 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 310 } 311 312 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 313 { 314 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 315 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 316 unsigned long host_clk; 317 318 if (!clock) 319 return sdhci_set_clock(host, clock); 320 321 /* 322 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 323 * divider to be configured to divided the host clock by two. The SDHCI 324 * clock divider is calculated as part of sdhci_set_clock() by 325 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 326 * the requested clock rate. 327 * 328 * By setting the host->max_clk to clock * 2 the divider calculation 329 * will always result in the correct value for DDR50/52 modes, 330 * regardless of clock rate rounding, which may happen if the value 331 * from clk_get_rate() is used. 332 */ 333 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 334 clk_set_rate(pltfm_host->clk, host_clk); 335 if (tegra_host->ddr_signaling) 336 host->max_clk = host_clk; 337 else 338 host->max_clk = clk_get_rate(pltfm_host->clk); 339 340 sdhci_set_clock(host, clock); 341 342 if (tegra_host->pad_calib_required) { 343 tegra_sdhci_pad_autocalib(host); 344 tegra_host->pad_calib_required = false; 345 } 346 } 347 348 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 349 unsigned timing) 350 { 351 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 352 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 353 354 if (timing == MMC_TIMING_UHS_DDR50 || 355 timing == MMC_TIMING_MMC_DDR52) 356 tegra_host->ddr_signaling = true; 357 358 sdhci_set_uhs_signaling(host, timing); 359 } 360 361 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 362 { 363 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 364 365 return clk_round_rate(pltfm_host->clk, UINT_MAX); 366 } 367 368 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 369 { 370 u32 reg; 371 372 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 373 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 374 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 375 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 376 } 377 378 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 379 { 380 unsigned int min, max; 381 382 /* 383 * Start search for minimum tap value at 10, as smaller values are 384 * may wrongly be reported as working but fail at higher speeds, 385 * according to the TRM. 386 */ 387 min = 10; 388 while (min < 255) { 389 tegra_sdhci_set_tap(host, min); 390 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 391 break; 392 min++; 393 } 394 395 /* Find the maximum tap value that still passes. */ 396 max = min + 1; 397 while (max < 255) { 398 tegra_sdhci_set_tap(host, max); 399 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 400 max--; 401 break; 402 } 403 max++; 404 } 405 406 /* The TRM states the ideal tap value is at 75% in the passing range. */ 407 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 408 409 return mmc_send_tuning(host->mmc, opcode, NULL); 410 } 411 412 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 413 { 414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 415 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 416 int ret; 417 418 if (!tegra_host->pad_control_available) 419 return 0; 420 421 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 422 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 423 tegra_host->pinctrl_state_1v8); 424 if (ret < 0) 425 dev_err(mmc_dev(host->mmc), 426 "setting 1.8V failed, ret: %d\n", ret); 427 } else { 428 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 429 tegra_host->pinctrl_state_3v3); 430 if (ret < 0) 431 dev_err(mmc_dev(host->mmc), 432 "setting 3.3V failed, ret: %d\n", ret); 433 } 434 435 return ret; 436 } 437 438 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 439 struct mmc_ios *ios) 440 { 441 struct sdhci_host *host = mmc_priv(mmc); 442 int ret = 0; 443 444 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 445 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 446 if (ret < 0) 447 return ret; 448 ret = sdhci_start_signal_voltage_switch(mmc, ios); 449 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 450 ret = sdhci_start_signal_voltage_switch(mmc, ios); 451 if (ret < 0) 452 return ret; 453 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 454 } 455 456 return ret; 457 } 458 459 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 460 struct sdhci_tegra *tegra_host) 461 { 462 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 463 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 464 dev_dbg(dev, "No pinctrl info, err: %ld\n", 465 PTR_ERR(tegra_host->pinctrl_sdmmc)); 466 return -1; 467 } 468 469 tegra_host->pinctrl_state_3v3 = 470 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 471 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 472 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 473 PTR_ERR(tegra_host->pinctrl_state_3v3)); 474 return -1; 475 } 476 477 tegra_host->pinctrl_state_1v8 = 478 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 479 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 480 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 481 PTR_ERR(tegra_host->pinctrl_state_3v3)); 482 return -1; 483 } 484 485 tegra_host->pad_control_available = true; 486 487 return 0; 488 } 489 490 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 491 { 492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 493 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 494 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 495 496 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 497 tegra_host->pad_calib_required = true; 498 } 499 500 static const struct sdhci_ops tegra_sdhci_ops = { 501 .get_ro = tegra_sdhci_get_ro, 502 .read_w = tegra_sdhci_readw, 503 .write_l = tegra_sdhci_writel, 504 .set_clock = tegra_sdhci_set_clock, 505 .set_bus_width = sdhci_set_bus_width, 506 .reset = tegra_sdhci_reset, 507 .platform_execute_tuning = tegra_sdhci_execute_tuning, 508 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 509 .voltage_switch = tegra_sdhci_voltage_switch, 510 .get_max_clock = tegra_sdhci_get_max_clock, 511 }; 512 513 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 514 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 515 SDHCI_QUIRK_SINGLE_POWER_WRITE | 516 SDHCI_QUIRK_NO_HISPD_BIT | 517 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 518 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 519 .ops = &tegra_sdhci_ops, 520 }; 521 522 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 523 .pdata = &sdhci_tegra20_pdata, 524 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 525 NVQUIRK_ENABLE_BLOCK_GAP_DET, 526 }; 527 528 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 529 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 530 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 531 SDHCI_QUIRK_SINGLE_POWER_WRITE | 532 SDHCI_QUIRK_NO_HISPD_BIT | 533 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 534 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 535 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 536 SDHCI_QUIRK2_BROKEN_HS200 | 537 /* 538 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 539 * though no command operation was in progress." 540 * 541 * The exact reason is unknown, as the same hardware seems 542 * to support Auto CMD23 on a downstream 3.1 kernel. 543 */ 544 SDHCI_QUIRK2_ACMD23_BROKEN, 545 .ops = &tegra_sdhci_ops, 546 }; 547 548 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 549 .pdata = &sdhci_tegra30_pdata, 550 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 551 NVQUIRK_ENABLE_SDR50 | 552 NVQUIRK_ENABLE_SDR104 | 553 NVQUIRK_HAS_PADCALIB, 554 }; 555 556 static const struct sdhci_ops tegra114_sdhci_ops = { 557 .get_ro = tegra_sdhci_get_ro, 558 .read_w = tegra_sdhci_readw, 559 .write_w = tegra_sdhci_writew, 560 .write_l = tegra_sdhci_writel, 561 .set_clock = tegra_sdhci_set_clock, 562 .set_bus_width = sdhci_set_bus_width, 563 .reset = tegra_sdhci_reset, 564 .platform_execute_tuning = tegra_sdhci_execute_tuning, 565 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 566 .voltage_switch = tegra_sdhci_voltage_switch, 567 .get_max_clock = tegra_sdhci_get_max_clock, 568 }; 569 570 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 571 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 572 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 573 SDHCI_QUIRK_SINGLE_POWER_WRITE | 574 SDHCI_QUIRK_NO_HISPD_BIT | 575 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 576 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 577 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 578 .ops = &tegra114_sdhci_ops, 579 }; 580 581 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 582 .pdata = &sdhci_tegra114_pdata, 583 }; 584 585 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 586 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 587 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 588 SDHCI_QUIRK_SINGLE_POWER_WRITE | 589 SDHCI_QUIRK_NO_HISPD_BIT | 590 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 591 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 592 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 593 /* 594 * The TRM states that the SD/MMC controller found on 595 * Tegra124 can address 34 bits (the maximum supported by 596 * the Tegra memory controller), but tests show that DMA 597 * to or from above 4 GiB doesn't work. This is possibly 598 * caused by missing programming, though it's not obvious 599 * what sequence is required. Mark 64-bit DMA broken for 600 * now to fix this for existing users (e.g. Nyan boards). 601 */ 602 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 603 .ops = &tegra114_sdhci_ops, 604 }; 605 606 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 607 .pdata = &sdhci_tegra124_pdata, 608 }; 609 610 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 611 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 612 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 613 SDHCI_QUIRK_SINGLE_POWER_WRITE | 614 SDHCI_QUIRK_NO_HISPD_BIT | 615 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 616 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 617 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 618 .ops = &tegra114_sdhci_ops, 619 }; 620 621 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 622 .pdata = &sdhci_tegra210_pdata, 623 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 624 }; 625 626 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 627 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 628 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 629 SDHCI_QUIRK_SINGLE_POWER_WRITE | 630 SDHCI_QUIRK_NO_HISPD_BIT | 631 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 632 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 633 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 634 /* SDHCI controllers on Tegra186 support 40-bit addressing. 635 * IOVA addresses are 48-bit wide on Tegra186. 636 * With 64-bit dma mask used for SDHCI, accesses can 637 * be broken. Disable 64-bit dma, which would fall back 638 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 639 * But it is not supported as of now. 640 */ 641 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 642 .ops = &tegra114_sdhci_ops, 643 }; 644 645 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 646 .pdata = &sdhci_tegra186_pdata, 647 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 648 }; 649 650 static const struct of_device_id sdhci_tegra_dt_match[] = { 651 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 652 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 653 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 654 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 655 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 656 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 657 {} 658 }; 659 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 660 661 static int sdhci_tegra_probe(struct platform_device *pdev) 662 { 663 const struct of_device_id *match; 664 const struct sdhci_tegra_soc_data *soc_data; 665 struct sdhci_host *host; 666 struct sdhci_pltfm_host *pltfm_host; 667 struct sdhci_tegra *tegra_host; 668 struct clk *clk; 669 int rc; 670 671 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 672 if (!match) 673 return -EINVAL; 674 soc_data = match->data; 675 676 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 677 if (IS_ERR(host)) 678 return PTR_ERR(host); 679 pltfm_host = sdhci_priv(host); 680 681 tegra_host = sdhci_pltfm_priv(pltfm_host); 682 tegra_host->ddr_signaling = false; 683 tegra_host->pad_calib_required = false; 684 tegra_host->pad_control_available = false; 685 tegra_host->soc_data = soc_data; 686 687 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 688 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 689 if (rc == 0) 690 host->mmc_host_ops.start_signal_voltage_switch = 691 sdhci_tegra_start_signal_voltage_switch; 692 } 693 694 rc = mmc_of_parse(host->mmc); 695 if (rc) 696 goto err_parse_dt; 697 698 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 699 host->mmc->caps |= MMC_CAP_1_8V_DDR; 700 701 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 702 GPIOD_OUT_HIGH); 703 if (IS_ERR(tegra_host->power_gpio)) { 704 rc = PTR_ERR(tegra_host->power_gpio); 705 goto err_power_req; 706 } 707 708 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 709 if (IS_ERR(clk)) { 710 dev_err(mmc_dev(host->mmc), "clk err\n"); 711 rc = PTR_ERR(clk); 712 goto err_clk_get; 713 } 714 clk_prepare_enable(clk); 715 pltfm_host->clk = clk; 716 717 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 718 "sdhci"); 719 if (IS_ERR(tegra_host->rst)) { 720 rc = PTR_ERR(tegra_host->rst); 721 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 722 goto err_rst_get; 723 } 724 725 rc = reset_control_assert(tegra_host->rst); 726 if (rc) 727 goto err_rst_get; 728 729 usleep_range(2000, 4000); 730 731 rc = reset_control_deassert(tegra_host->rst); 732 if (rc) 733 goto err_rst_get; 734 735 usleep_range(2000, 4000); 736 737 rc = sdhci_add_host(host); 738 if (rc) 739 goto err_add_host; 740 741 return 0; 742 743 err_add_host: 744 reset_control_assert(tegra_host->rst); 745 err_rst_get: 746 clk_disable_unprepare(pltfm_host->clk); 747 err_clk_get: 748 err_power_req: 749 err_parse_dt: 750 sdhci_pltfm_free(pdev); 751 return rc; 752 } 753 754 static int sdhci_tegra_remove(struct platform_device *pdev) 755 { 756 struct sdhci_host *host = platform_get_drvdata(pdev); 757 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 758 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 759 760 sdhci_remove_host(host, 0); 761 762 reset_control_assert(tegra_host->rst); 763 usleep_range(2000, 4000); 764 clk_disable_unprepare(pltfm_host->clk); 765 766 sdhci_pltfm_free(pdev); 767 768 return 0; 769 } 770 771 static struct platform_driver sdhci_tegra_driver = { 772 .driver = { 773 .name = "sdhci-tegra", 774 .of_match_table = sdhci_tegra_dt_match, 775 .pm = &sdhci_pltfm_pmops, 776 }, 777 .probe = sdhci_tegra_probe, 778 .remove = sdhci_tegra_remove, 779 }; 780 781 module_platform_driver(sdhci_tegra_driver); 782 783 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 784 MODULE_AUTHOR("Google, Inc."); 785 MODULE_LICENSE("GPL v2"); 786