1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/slot-gpio.h> 31 #include <linux/gpio/consumer.h> 32 33 #include "sdhci-pltfm.h" 34 35 /* Tegra SDHOST controller vendor register definitions */ 36 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 37 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 38 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 39 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 40 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 41 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 42 43 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 44 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 45 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 46 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 47 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 48 49 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 50 #define SDHCI_AUTO_CAL_START BIT(31) 51 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 52 53 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 54 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 55 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 56 #define NVQUIRK_ENABLE_SDR50 BIT(3) 57 #define NVQUIRK_ENABLE_SDR104 BIT(4) 58 #define NVQUIRK_ENABLE_DDR50 BIT(5) 59 #define NVQUIRK_HAS_PADCALIB BIT(6) 60 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 61 62 struct sdhci_tegra_soc_data { 63 const struct sdhci_pltfm_data *pdata; 64 u32 nvquirks; 65 }; 66 67 struct sdhci_tegra { 68 const struct sdhci_tegra_soc_data *soc_data; 69 struct gpio_desc *power_gpio; 70 bool ddr_signaling; 71 bool pad_calib_required; 72 bool pad_control_available; 73 74 struct reset_control *rst; 75 struct pinctrl *pinctrl_sdmmc; 76 struct pinctrl_state *pinctrl_state_3v3; 77 struct pinctrl_state *pinctrl_state_1v8; 78 }; 79 80 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 81 { 82 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 83 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 84 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 85 86 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 87 (reg == SDHCI_HOST_VERSION))) { 88 /* Erratum: Version register is invalid in HW. */ 89 return SDHCI_SPEC_200; 90 } 91 92 return readw(host->ioaddr + reg); 93 } 94 95 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 96 { 97 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 98 99 switch (reg) { 100 case SDHCI_TRANSFER_MODE: 101 /* 102 * Postpone this write, we must do it together with a 103 * command write that is down below. 104 */ 105 pltfm_host->xfer_mode_shadow = val; 106 return; 107 case SDHCI_COMMAND: 108 writel((val << 16) | pltfm_host->xfer_mode_shadow, 109 host->ioaddr + SDHCI_TRANSFER_MODE); 110 return; 111 } 112 113 writew(val, host->ioaddr + reg); 114 } 115 116 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 117 { 118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 119 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 120 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 121 122 /* Seems like we're getting spurious timeout and crc errors, so 123 * disable signalling of them. In case of real errors software 124 * timers should take care of eventually detecting them. 125 */ 126 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 127 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 128 129 writel(val, host->ioaddr + reg); 130 131 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 132 (reg == SDHCI_INT_ENABLE))) { 133 /* Erratum: Must enable block gap interrupt detection */ 134 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 135 if (val & SDHCI_INT_CARD_INT) 136 gap_ctrl |= 0x8; 137 else 138 gap_ctrl &= ~0x8; 139 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 140 } 141 } 142 143 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 144 { 145 return mmc_gpio_get_ro(host->mmc); 146 } 147 148 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 149 { 150 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 151 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 152 int has_1v8, has_3v3; 153 154 /* 155 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 156 * voltage configuration in order to perform voltage switching. This 157 * means that valid pinctrl info is required on SDHCI instances capable 158 * of performing voltage switching. Whether or not an SDHCI instance is 159 * capable of voltage switching is determined based on the regulator. 160 */ 161 162 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 163 return true; 164 165 if (IS_ERR(host->mmc->supply.vqmmc)) 166 return false; 167 168 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 169 1700000, 1950000); 170 171 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 172 2700000, 3600000); 173 174 if (has_1v8 == 1 && has_3v3 == 1) 175 return tegra_host->pad_control_available; 176 177 /* Fixed voltage, no pad control required. */ 178 return true; 179 } 180 181 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 182 { 183 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 184 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 185 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 186 u32 misc_ctrl, clk_ctrl; 187 188 sdhci_reset(host, mask); 189 190 if (!(mask & SDHCI_RESET_ALL)) 191 return; 192 193 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 194 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 195 196 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 197 SDHCI_MISC_CTRL_ENABLE_SDR50 | 198 SDHCI_MISC_CTRL_ENABLE_DDR50 | 199 SDHCI_MISC_CTRL_ENABLE_SDR104); 200 201 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 202 203 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 204 /* Erratum: Enable SDHCI spec v3.00 support */ 205 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 206 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 207 /* Advertise UHS modes as supported by host */ 208 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 209 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 210 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 211 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 212 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 213 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 214 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 215 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 216 } 217 218 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 219 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 220 221 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 222 tegra_host->pad_calib_required = true; 223 224 tegra_host->ddr_signaling = false; 225 } 226 227 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 228 { 229 u32 val; 230 231 mdelay(1); 232 233 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 234 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 235 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); 236 } 237 238 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 239 { 240 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 241 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 242 unsigned long host_clk; 243 244 if (!clock) 245 return sdhci_set_clock(host, clock); 246 247 /* 248 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 249 * divider to be configured to divided the host clock by two. The SDHCI 250 * clock divider is calculated as part of sdhci_set_clock() by 251 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 252 * the requested clock rate. 253 * 254 * By setting the host->max_clk to clock * 2 the divider calculation 255 * will always result in the correct value for DDR50/52 modes, 256 * regardless of clock rate rounding, which may happen if the value 257 * from clk_get_rate() is used. 258 */ 259 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 260 clk_set_rate(pltfm_host->clk, host_clk); 261 if (tegra_host->ddr_signaling) 262 host->max_clk = host_clk; 263 else 264 host->max_clk = clk_get_rate(pltfm_host->clk); 265 266 sdhci_set_clock(host, clock); 267 268 if (tegra_host->pad_calib_required) { 269 tegra_sdhci_pad_autocalib(host); 270 tegra_host->pad_calib_required = false; 271 } 272 } 273 274 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 275 unsigned timing) 276 { 277 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 278 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 279 280 if (timing == MMC_TIMING_UHS_DDR50 || 281 timing == MMC_TIMING_MMC_DDR52) 282 tegra_host->ddr_signaling = true; 283 284 sdhci_set_uhs_signaling(host, timing); 285 } 286 287 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 288 { 289 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 290 291 return clk_round_rate(pltfm_host->clk, UINT_MAX); 292 } 293 294 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 295 { 296 u32 reg; 297 298 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 299 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 300 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 301 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 302 } 303 304 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 305 { 306 unsigned int min, max; 307 308 /* 309 * Start search for minimum tap value at 10, as smaller values are 310 * may wrongly be reported as working but fail at higher speeds, 311 * according to the TRM. 312 */ 313 min = 10; 314 while (min < 255) { 315 tegra_sdhci_set_tap(host, min); 316 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 317 break; 318 min++; 319 } 320 321 /* Find the maximum tap value that still passes. */ 322 max = min + 1; 323 while (max < 255) { 324 tegra_sdhci_set_tap(host, max); 325 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 326 max--; 327 break; 328 } 329 max++; 330 } 331 332 /* The TRM states the ideal tap value is at 75% in the passing range. */ 333 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 334 335 return mmc_send_tuning(host->mmc, opcode, NULL); 336 } 337 338 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 339 { 340 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 341 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 342 int ret; 343 344 if (!tegra_host->pad_control_available) 345 return 0; 346 347 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 348 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 349 tegra_host->pinctrl_state_1v8); 350 if (ret < 0) 351 dev_err(mmc_dev(host->mmc), 352 "setting 1.8V failed, ret: %d\n", ret); 353 } else { 354 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 355 tegra_host->pinctrl_state_3v3); 356 if (ret < 0) 357 dev_err(mmc_dev(host->mmc), 358 "setting 3.3V failed, ret: %d\n", ret); 359 } 360 361 return ret; 362 } 363 364 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 365 struct mmc_ios *ios) 366 { 367 struct sdhci_host *host = mmc_priv(mmc); 368 int ret = 0; 369 370 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 371 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 372 if (ret < 0) 373 return ret; 374 ret = sdhci_start_signal_voltage_switch(mmc, ios); 375 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 376 ret = sdhci_start_signal_voltage_switch(mmc, ios); 377 if (ret < 0) 378 return ret; 379 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 380 } 381 382 return ret; 383 } 384 385 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 386 struct sdhci_tegra *tegra_host) 387 { 388 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 389 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 390 dev_dbg(dev, "No pinctrl info, err: %ld\n", 391 PTR_ERR(tegra_host->pinctrl_sdmmc)); 392 return -1; 393 } 394 395 tegra_host->pinctrl_state_3v3 = 396 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 397 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 398 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 399 PTR_ERR(tegra_host->pinctrl_state_3v3)); 400 return -1; 401 } 402 403 tegra_host->pinctrl_state_1v8 = 404 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 405 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 406 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 407 PTR_ERR(tegra_host->pinctrl_state_3v3)); 408 return -1; 409 } 410 411 tegra_host->pad_control_available = true; 412 413 return 0; 414 } 415 416 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 417 { 418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 419 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 420 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 421 422 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 423 tegra_host->pad_calib_required = true; 424 } 425 426 static const struct sdhci_ops tegra_sdhci_ops = { 427 .get_ro = tegra_sdhci_get_ro, 428 .read_w = tegra_sdhci_readw, 429 .write_l = tegra_sdhci_writel, 430 .set_clock = tegra_sdhci_set_clock, 431 .set_bus_width = sdhci_set_bus_width, 432 .reset = tegra_sdhci_reset, 433 .platform_execute_tuning = tegra_sdhci_execute_tuning, 434 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 435 .voltage_switch = tegra_sdhci_voltage_switch, 436 .get_max_clock = tegra_sdhci_get_max_clock, 437 }; 438 439 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 440 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 441 SDHCI_QUIRK_SINGLE_POWER_WRITE | 442 SDHCI_QUIRK_NO_HISPD_BIT | 443 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 444 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 445 .ops = &tegra_sdhci_ops, 446 }; 447 448 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 449 .pdata = &sdhci_tegra20_pdata, 450 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 451 NVQUIRK_ENABLE_BLOCK_GAP_DET, 452 }; 453 454 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 455 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 456 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 457 SDHCI_QUIRK_SINGLE_POWER_WRITE | 458 SDHCI_QUIRK_NO_HISPD_BIT | 459 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 460 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 461 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 462 SDHCI_QUIRK2_BROKEN_HS200 | 463 /* 464 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 465 * though no command operation was in progress." 466 * 467 * The exact reason is unknown, as the same hardware seems 468 * to support Auto CMD23 on a downstream 3.1 kernel. 469 */ 470 SDHCI_QUIRK2_ACMD23_BROKEN, 471 .ops = &tegra_sdhci_ops, 472 }; 473 474 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 475 .pdata = &sdhci_tegra30_pdata, 476 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 477 NVQUIRK_ENABLE_SDR50 | 478 NVQUIRK_ENABLE_SDR104 | 479 NVQUIRK_HAS_PADCALIB, 480 }; 481 482 static const struct sdhci_ops tegra114_sdhci_ops = { 483 .get_ro = tegra_sdhci_get_ro, 484 .read_w = tegra_sdhci_readw, 485 .write_w = tegra_sdhci_writew, 486 .write_l = tegra_sdhci_writel, 487 .set_clock = tegra_sdhci_set_clock, 488 .set_bus_width = sdhci_set_bus_width, 489 .reset = tegra_sdhci_reset, 490 .platform_execute_tuning = tegra_sdhci_execute_tuning, 491 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 492 .voltage_switch = tegra_sdhci_voltage_switch, 493 .get_max_clock = tegra_sdhci_get_max_clock, 494 }; 495 496 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 497 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 498 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 499 SDHCI_QUIRK_SINGLE_POWER_WRITE | 500 SDHCI_QUIRK_NO_HISPD_BIT | 501 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 502 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 503 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 504 .ops = &tegra114_sdhci_ops, 505 }; 506 507 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 508 .pdata = &sdhci_tegra114_pdata, 509 }; 510 511 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 512 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 513 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 514 SDHCI_QUIRK_SINGLE_POWER_WRITE | 515 SDHCI_QUIRK_NO_HISPD_BIT | 516 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 517 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 518 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 519 /* 520 * The TRM states that the SD/MMC controller found on 521 * Tegra124 can address 34 bits (the maximum supported by 522 * the Tegra memory controller), but tests show that DMA 523 * to or from above 4 GiB doesn't work. This is possibly 524 * caused by missing programming, though it's not obvious 525 * what sequence is required. Mark 64-bit DMA broken for 526 * now to fix this for existing users (e.g. Nyan boards). 527 */ 528 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 529 .ops = &tegra114_sdhci_ops, 530 }; 531 532 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 533 .pdata = &sdhci_tegra124_pdata, 534 }; 535 536 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 537 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 538 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 539 SDHCI_QUIRK_SINGLE_POWER_WRITE | 540 SDHCI_QUIRK_NO_HISPD_BIT | 541 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 542 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 543 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 544 .ops = &tegra114_sdhci_ops, 545 }; 546 547 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 548 .pdata = &sdhci_tegra210_pdata, 549 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 550 }; 551 552 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 553 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 554 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 555 SDHCI_QUIRK_SINGLE_POWER_WRITE | 556 SDHCI_QUIRK_NO_HISPD_BIT | 557 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 558 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 559 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 560 /* SDHCI controllers on Tegra186 support 40-bit addressing. 561 * IOVA addresses are 48-bit wide on Tegra186. 562 * With 64-bit dma mask used for SDHCI, accesses can 563 * be broken. Disable 64-bit dma, which would fall back 564 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 565 * But it is not supported as of now. 566 */ 567 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 568 .ops = &tegra114_sdhci_ops, 569 }; 570 571 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 572 .pdata = &sdhci_tegra186_pdata, 573 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 574 }; 575 576 static const struct of_device_id sdhci_tegra_dt_match[] = { 577 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 578 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 579 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 580 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 581 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 582 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 583 {} 584 }; 585 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 586 587 static int sdhci_tegra_probe(struct platform_device *pdev) 588 { 589 const struct of_device_id *match; 590 const struct sdhci_tegra_soc_data *soc_data; 591 struct sdhci_host *host; 592 struct sdhci_pltfm_host *pltfm_host; 593 struct sdhci_tegra *tegra_host; 594 struct clk *clk; 595 int rc; 596 597 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 598 if (!match) 599 return -EINVAL; 600 soc_data = match->data; 601 602 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 603 if (IS_ERR(host)) 604 return PTR_ERR(host); 605 pltfm_host = sdhci_priv(host); 606 607 tegra_host = sdhci_pltfm_priv(pltfm_host); 608 tegra_host->ddr_signaling = false; 609 tegra_host->pad_calib_required = false; 610 tegra_host->pad_control_available = false; 611 tegra_host->soc_data = soc_data; 612 613 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 614 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 615 if (rc == 0) 616 host->mmc_host_ops.start_signal_voltage_switch = 617 sdhci_tegra_start_signal_voltage_switch; 618 } 619 620 rc = mmc_of_parse(host->mmc); 621 if (rc) 622 goto err_parse_dt; 623 624 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 625 host->mmc->caps |= MMC_CAP_1_8V_DDR; 626 627 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 628 GPIOD_OUT_HIGH); 629 if (IS_ERR(tegra_host->power_gpio)) { 630 rc = PTR_ERR(tegra_host->power_gpio); 631 goto err_power_req; 632 } 633 634 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 635 if (IS_ERR(clk)) { 636 dev_err(mmc_dev(host->mmc), "clk err\n"); 637 rc = PTR_ERR(clk); 638 goto err_clk_get; 639 } 640 clk_prepare_enable(clk); 641 pltfm_host->clk = clk; 642 643 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 644 "sdhci"); 645 if (IS_ERR(tegra_host->rst)) { 646 rc = PTR_ERR(tegra_host->rst); 647 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 648 goto err_rst_get; 649 } 650 651 rc = reset_control_assert(tegra_host->rst); 652 if (rc) 653 goto err_rst_get; 654 655 usleep_range(2000, 4000); 656 657 rc = reset_control_deassert(tegra_host->rst); 658 if (rc) 659 goto err_rst_get; 660 661 usleep_range(2000, 4000); 662 663 rc = sdhci_add_host(host); 664 if (rc) 665 goto err_add_host; 666 667 return 0; 668 669 err_add_host: 670 reset_control_assert(tegra_host->rst); 671 err_rst_get: 672 clk_disable_unprepare(pltfm_host->clk); 673 err_clk_get: 674 err_power_req: 675 err_parse_dt: 676 sdhci_pltfm_free(pdev); 677 return rc; 678 } 679 680 static int sdhci_tegra_remove(struct platform_device *pdev) 681 { 682 struct sdhci_host *host = platform_get_drvdata(pdev); 683 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 684 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 685 686 sdhci_remove_host(host, 0); 687 688 reset_control_assert(tegra_host->rst); 689 usleep_range(2000, 4000); 690 clk_disable_unprepare(pltfm_host->clk); 691 692 sdhci_pltfm_free(pdev); 693 694 return 0; 695 } 696 697 static struct platform_driver sdhci_tegra_driver = { 698 .driver = { 699 .name = "sdhci-tegra", 700 .of_match_table = sdhci_tegra_dt_match, 701 .pm = &sdhci_pltfm_pmops, 702 }, 703 .probe = sdhci_tegra_probe, 704 .remove = sdhci_tegra_remove, 705 }; 706 707 module_platform_driver(sdhci_tegra_driver); 708 709 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 710 MODULE_AUTHOR("Google, Inc."); 711 MODULE_LICENSE("GPL v2"); 712