1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 51 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 52 53 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 54 #define SDHCI_AUTO_CAL_START BIT(31) 55 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 56 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 57 58 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 59 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 60 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 61 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 62 63 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 64 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 65 66 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 67 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 68 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 69 #define NVQUIRK_ENABLE_SDR50 BIT(3) 70 #define NVQUIRK_ENABLE_SDR104 BIT(4) 71 #define NVQUIRK_ENABLE_DDR50 BIT(5) 72 #define NVQUIRK_HAS_PADCALIB BIT(6) 73 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 74 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 75 76 struct sdhci_tegra_soc_data { 77 const struct sdhci_pltfm_data *pdata; 78 u32 nvquirks; 79 }; 80 81 /* Magic pull up and pull down pad calibration offsets */ 82 struct sdhci_tegra_autocal_offsets { 83 u32 pull_up_3v3; 84 u32 pull_down_3v3; 85 u32 pull_up_3v3_timeout; 86 u32 pull_down_3v3_timeout; 87 u32 pull_up_1v8; 88 u32 pull_down_1v8; 89 u32 pull_up_1v8_timeout; 90 u32 pull_down_1v8_timeout; 91 u32 pull_up_sdr104; 92 u32 pull_down_sdr104; 93 u32 pull_up_hs400; 94 u32 pull_down_hs400; 95 }; 96 97 struct sdhci_tegra { 98 const struct sdhci_tegra_soc_data *soc_data; 99 struct gpio_desc *power_gpio; 100 bool ddr_signaling; 101 bool pad_calib_required; 102 bool pad_control_available; 103 104 struct reset_control *rst; 105 struct pinctrl *pinctrl_sdmmc; 106 struct pinctrl_state *pinctrl_state_3v3; 107 struct pinctrl_state *pinctrl_state_1v8; 108 109 struct sdhci_tegra_autocal_offsets autocal_offsets; 110 111 u32 default_tap; 112 u32 default_trim; 113 }; 114 115 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 116 { 117 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 118 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 119 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 120 121 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 122 (reg == SDHCI_HOST_VERSION))) { 123 /* Erratum: Version register is invalid in HW. */ 124 return SDHCI_SPEC_200; 125 } 126 127 return readw(host->ioaddr + reg); 128 } 129 130 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 131 { 132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 133 134 switch (reg) { 135 case SDHCI_TRANSFER_MODE: 136 /* 137 * Postpone this write, we must do it together with a 138 * command write that is down below. 139 */ 140 pltfm_host->xfer_mode_shadow = val; 141 return; 142 case SDHCI_COMMAND: 143 writel((val << 16) | pltfm_host->xfer_mode_shadow, 144 host->ioaddr + SDHCI_TRANSFER_MODE); 145 return; 146 } 147 148 writew(val, host->ioaddr + reg); 149 } 150 151 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 152 { 153 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 154 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 155 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 156 157 /* Seems like we're getting spurious timeout and crc errors, so 158 * disable signalling of them. In case of real errors software 159 * timers should take care of eventually detecting them. 160 */ 161 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 162 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 163 164 writel(val, host->ioaddr + reg); 165 166 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 167 (reg == SDHCI_INT_ENABLE))) { 168 /* Erratum: Must enable block gap interrupt detection */ 169 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 170 if (val & SDHCI_INT_CARD_INT) 171 gap_ctrl |= 0x8; 172 else 173 gap_ctrl &= ~0x8; 174 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 175 } 176 } 177 178 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 179 { 180 return mmc_gpio_get_ro(host->mmc); 181 } 182 183 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 187 int has_1v8, has_3v3; 188 189 /* 190 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 191 * voltage configuration in order to perform voltage switching. This 192 * means that valid pinctrl info is required on SDHCI instances capable 193 * of performing voltage switching. Whether or not an SDHCI instance is 194 * capable of voltage switching is determined based on the regulator. 195 */ 196 197 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 198 return true; 199 200 if (IS_ERR(host->mmc->supply.vqmmc)) 201 return false; 202 203 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 204 1700000, 1950000); 205 206 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 207 2700000, 3600000); 208 209 if (has_1v8 == 1 && has_3v3 == 1) 210 return tegra_host->pad_control_available; 211 212 /* Fixed voltage, no pad control required. */ 213 return true; 214 } 215 216 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 217 { 218 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 219 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 220 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 221 u32 misc_ctrl, clk_ctrl, pad_ctrl; 222 223 sdhci_reset(host, mask); 224 225 if (!(mask & SDHCI_RESET_ALL)) 226 return; 227 228 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 229 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 230 231 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 232 SDHCI_MISC_CTRL_ENABLE_SDR50 | 233 SDHCI_MISC_CTRL_ENABLE_DDR50 | 234 SDHCI_MISC_CTRL_ENABLE_SDR104); 235 236 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 237 238 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 239 /* Erratum: Enable SDHCI spec v3.00 support */ 240 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 241 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 242 /* Advertise UHS modes as supported by host */ 243 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 244 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 245 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 246 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 247 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 248 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 249 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 250 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 251 } 252 253 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 254 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 255 256 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 257 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 258 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 259 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 260 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 261 262 tegra_host->pad_calib_required = true; 263 } 264 265 tegra_host->ddr_signaling = false; 266 } 267 268 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 269 { 270 u32 val; 271 272 /* 273 * Enable or disable the additional I/O pad used by the drive strength 274 * calibration process. 275 */ 276 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 277 278 if (enable) 279 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 280 else 281 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 282 283 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 284 285 if (enable) 286 usleep_range(1, 2); 287 } 288 289 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 290 { 291 bool status; 292 u32 reg; 293 294 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 295 status = !!(reg & SDHCI_CLOCK_CARD_EN); 296 297 if (status == enable) 298 return status; 299 300 if (enable) 301 reg |= SDHCI_CLOCK_CARD_EN; 302 else 303 reg &= ~SDHCI_CLOCK_CARD_EN; 304 305 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 306 307 return status; 308 } 309 310 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 311 u16 pdpu) 312 { 313 u32 reg; 314 315 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 316 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 317 reg |= pdpu; 318 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 319 } 320 321 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 322 { 323 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 324 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 325 struct sdhci_tegra_autocal_offsets offsets = 326 tegra_host->autocal_offsets; 327 struct mmc_ios *ios = &host->mmc->ios; 328 bool card_clk_enabled; 329 u16 pdpu; 330 u32 reg; 331 int ret; 332 333 switch (ios->timing) { 334 case MMC_TIMING_UHS_SDR104: 335 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 336 break; 337 case MMC_TIMING_MMC_HS400: 338 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 339 break; 340 default: 341 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 342 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 343 else 344 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 345 } 346 347 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 348 349 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 350 351 tegra_sdhci_configure_cal_pad(host, true); 352 353 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 354 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 355 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 356 357 usleep_range(1, 2); 358 /* 10 ms timeout */ 359 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 360 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 361 1000, 10000); 362 363 tegra_sdhci_configure_cal_pad(host, false); 364 365 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 366 367 if (ret) { 368 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 369 370 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 371 pdpu = offsets.pull_down_1v8_timeout << 8 | 372 offsets.pull_up_1v8_timeout; 373 else 374 pdpu = offsets.pull_down_3v3_timeout << 8 | 375 offsets.pull_up_3v3_timeout; 376 377 /* Disable automatic calibration and use fixed offsets */ 378 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 379 reg &= ~SDHCI_AUTO_CAL_ENABLE; 380 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 381 382 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 383 } 384 } 385 386 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 387 { 388 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 389 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 390 struct sdhci_tegra_autocal_offsets *autocal = 391 &tegra_host->autocal_offsets; 392 int err; 393 394 err = device_property_read_u32(host->mmc->parent, 395 "nvidia,pad-autocal-pull-up-offset-3v3", 396 &autocal->pull_up_3v3); 397 if (err) 398 autocal->pull_up_3v3 = 0; 399 400 err = device_property_read_u32(host->mmc->parent, 401 "nvidia,pad-autocal-pull-down-offset-3v3", 402 &autocal->pull_down_3v3); 403 if (err) 404 autocal->pull_down_3v3 = 0; 405 406 err = device_property_read_u32(host->mmc->parent, 407 "nvidia,pad-autocal-pull-up-offset-1v8", 408 &autocal->pull_up_1v8); 409 if (err) 410 autocal->pull_up_1v8 = 0; 411 412 err = device_property_read_u32(host->mmc->parent, 413 "nvidia,pad-autocal-pull-down-offset-1v8", 414 &autocal->pull_down_1v8); 415 if (err) 416 autocal->pull_down_1v8 = 0; 417 418 err = device_property_read_u32(host->mmc->parent, 419 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 420 &autocal->pull_up_3v3); 421 if (err) 422 autocal->pull_up_3v3_timeout = 0; 423 424 err = device_property_read_u32(host->mmc->parent, 425 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 426 &autocal->pull_down_3v3); 427 if (err) 428 autocal->pull_down_3v3_timeout = 0; 429 430 err = device_property_read_u32(host->mmc->parent, 431 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 432 &autocal->pull_up_1v8); 433 if (err) 434 autocal->pull_up_1v8_timeout = 0; 435 436 err = device_property_read_u32(host->mmc->parent, 437 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 438 &autocal->pull_down_1v8); 439 if (err) 440 autocal->pull_down_1v8_timeout = 0; 441 442 err = device_property_read_u32(host->mmc->parent, 443 "nvidia,pad-autocal-pull-up-offset-sdr104", 444 &autocal->pull_up_sdr104); 445 if (err) 446 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 447 448 err = device_property_read_u32(host->mmc->parent, 449 "nvidia,pad-autocal-pull-down-offset-sdr104", 450 &autocal->pull_down_sdr104); 451 if (err) 452 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 453 454 err = device_property_read_u32(host->mmc->parent, 455 "nvidia,pad-autocal-pull-up-offset-hs400", 456 &autocal->pull_up_hs400); 457 if (err) 458 autocal->pull_up_hs400 = autocal->pull_up_1v8; 459 460 err = device_property_read_u32(host->mmc->parent, 461 "nvidia,pad-autocal-pull-down-offset-hs400", 462 &autocal->pull_down_hs400); 463 if (err) 464 autocal->pull_down_hs400 = autocal->pull_down_1v8; 465 } 466 467 static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host) 468 { 469 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 470 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 471 int err; 472 473 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 474 &tegra_host->default_tap); 475 if (err) 476 tegra_host->default_tap = 0; 477 478 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 479 &tegra_host->default_trim); 480 if (err) 481 tegra_host->default_trim = 0; 482 } 483 484 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 485 { 486 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 487 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 488 unsigned long host_clk; 489 490 if (!clock) 491 return sdhci_set_clock(host, clock); 492 493 /* 494 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 495 * divider to be configured to divided the host clock by two. The SDHCI 496 * clock divider is calculated as part of sdhci_set_clock() by 497 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 498 * the requested clock rate. 499 * 500 * By setting the host->max_clk to clock * 2 the divider calculation 501 * will always result in the correct value for DDR50/52 modes, 502 * regardless of clock rate rounding, which may happen if the value 503 * from clk_get_rate() is used. 504 */ 505 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 506 clk_set_rate(pltfm_host->clk, host_clk); 507 if (tegra_host->ddr_signaling) 508 host->max_clk = host_clk; 509 else 510 host->max_clk = clk_get_rate(pltfm_host->clk); 511 512 sdhci_set_clock(host, clock); 513 514 if (tegra_host->pad_calib_required) { 515 tegra_sdhci_pad_autocalib(host); 516 tegra_host->pad_calib_required = false; 517 } 518 } 519 520 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 521 unsigned timing) 522 { 523 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 524 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 525 526 if (timing == MMC_TIMING_UHS_DDR50 || 527 timing == MMC_TIMING_MMC_DDR52) 528 tegra_host->ddr_signaling = true; 529 530 sdhci_set_uhs_signaling(host, timing); 531 } 532 533 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 534 { 535 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 536 537 return clk_round_rate(pltfm_host->clk, UINT_MAX); 538 } 539 540 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 541 { 542 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 543 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 544 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 545 bool card_clk_enabled = false; 546 u32 reg; 547 548 /* 549 * Touching the tap values is a bit tricky on some SoC generations. 550 * The quirk enables a workaround for a glitch that sometimes occurs if 551 * the tap values are changed. 552 */ 553 554 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 555 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 556 557 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 558 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 559 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 560 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 561 562 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 563 card_clk_enabled) { 564 usleep_range(1, 2); 565 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 566 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 567 } 568 } 569 570 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 571 { 572 unsigned int min, max; 573 574 /* 575 * Start search for minimum tap value at 10, as smaller values are 576 * may wrongly be reported as working but fail at higher speeds, 577 * according to the TRM. 578 */ 579 min = 10; 580 while (min < 255) { 581 tegra_sdhci_set_tap(host, min); 582 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 583 break; 584 min++; 585 } 586 587 /* Find the maximum tap value that still passes. */ 588 max = min + 1; 589 while (max < 255) { 590 tegra_sdhci_set_tap(host, max); 591 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 592 max--; 593 break; 594 } 595 max++; 596 } 597 598 /* The TRM states the ideal tap value is at 75% in the passing range. */ 599 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 600 601 return mmc_send_tuning(host->mmc, opcode, NULL); 602 } 603 604 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 605 { 606 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 607 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 608 int ret; 609 610 if (!tegra_host->pad_control_available) 611 return 0; 612 613 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 614 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 615 tegra_host->pinctrl_state_1v8); 616 if (ret < 0) 617 dev_err(mmc_dev(host->mmc), 618 "setting 1.8V failed, ret: %d\n", ret); 619 } else { 620 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 621 tegra_host->pinctrl_state_3v3); 622 if (ret < 0) 623 dev_err(mmc_dev(host->mmc), 624 "setting 3.3V failed, ret: %d\n", ret); 625 } 626 627 return ret; 628 } 629 630 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 631 struct mmc_ios *ios) 632 { 633 struct sdhci_host *host = mmc_priv(mmc); 634 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 635 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 636 int ret = 0; 637 638 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 639 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 640 if (ret < 0) 641 return ret; 642 ret = sdhci_start_signal_voltage_switch(mmc, ios); 643 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 644 ret = sdhci_start_signal_voltage_switch(mmc, ios); 645 if (ret < 0) 646 return ret; 647 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 648 } 649 650 if (tegra_host->pad_calib_required) 651 tegra_sdhci_pad_autocalib(host); 652 653 return ret; 654 } 655 656 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 657 struct sdhci_tegra *tegra_host) 658 { 659 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 660 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 661 dev_dbg(dev, "No pinctrl info, err: %ld\n", 662 PTR_ERR(tegra_host->pinctrl_sdmmc)); 663 return -1; 664 } 665 666 tegra_host->pinctrl_state_3v3 = 667 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 668 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 669 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 670 PTR_ERR(tegra_host->pinctrl_state_3v3)); 671 return -1; 672 } 673 674 tegra_host->pinctrl_state_1v8 = 675 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 676 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 677 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 678 PTR_ERR(tegra_host->pinctrl_state_3v3)); 679 return -1; 680 } 681 682 tegra_host->pad_control_available = true; 683 684 return 0; 685 } 686 687 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 688 { 689 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 690 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 691 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 692 693 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 694 tegra_host->pad_calib_required = true; 695 } 696 697 static const struct sdhci_ops tegra_sdhci_ops = { 698 .get_ro = tegra_sdhci_get_ro, 699 .read_w = tegra_sdhci_readw, 700 .write_l = tegra_sdhci_writel, 701 .set_clock = tegra_sdhci_set_clock, 702 .set_bus_width = sdhci_set_bus_width, 703 .reset = tegra_sdhci_reset, 704 .platform_execute_tuning = tegra_sdhci_execute_tuning, 705 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 706 .voltage_switch = tegra_sdhci_voltage_switch, 707 .get_max_clock = tegra_sdhci_get_max_clock, 708 }; 709 710 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 711 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 712 SDHCI_QUIRK_SINGLE_POWER_WRITE | 713 SDHCI_QUIRK_NO_HISPD_BIT | 714 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 715 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 716 .ops = &tegra_sdhci_ops, 717 }; 718 719 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 720 .pdata = &sdhci_tegra20_pdata, 721 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 722 NVQUIRK_ENABLE_BLOCK_GAP_DET, 723 }; 724 725 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 726 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 727 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 728 SDHCI_QUIRK_SINGLE_POWER_WRITE | 729 SDHCI_QUIRK_NO_HISPD_BIT | 730 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 731 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 732 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 733 SDHCI_QUIRK2_BROKEN_HS200 | 734 /* 735 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 736 * though no command operation was in progress." 737 * 738 * The exact reason is unknown, as the same hardware seems 739 * to support Auto CMD23 on a downstream 3.1 kernel. 740 */ 741 SDHCI_QUIRK2_ACMD23_BROKEN, 742 .ops = &tegra_sdhci_ops, 743 }; 744 745 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 746 .pdata = &sdhci_tegra30_pdata, 747 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 748 NVQUIRK_ENABLE_SDR50 | 749 NVQUIRK_ENABLE_SDR104 | 750 NVQUIRK_HAS_PADCALIB, 751 }; 752 753 static const struct sdhci_ops tegra114_sdhci_ops = { 754 .get_ro = tegra_sdhci_get_ro, 755 .read_w = tegra_sdhci_readw, 756 .write_w = tegra_sdhci_writew, 757 .write_l = tegra_sdhci_writel, 758 .set_clock = tegra_sdhci_set_clock, 759 .set_bus_width = sdhci_set_bus_width, 760 .reset = tegra_sdhci_reset, 761 .platform_execute_tuning = tegra_sdhci_execute_tuning, 762 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 763 .voltage_switch = tegra_sdhci_voltage_switch, 764 .get_max_clock = tegra_sdhci_get_max_clock, 765 }; 766 767 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 768 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 769 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 770 SDHCI_QUIRK_SINGLE_POWER_WRITE | 771 SDHCI_QUIRK_NO_HISPD_BIT | 772 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 773 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 774 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 775 .ops = &tegra114_sdhci_ops, 776 }; 777 778 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 779 .pdata = &sdhci_tegra114_pdata, 780 }; 781 782 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 783 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 784 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 785 SDHCI_QUIRK_SINGLE_POWER_WRITE | 786 SDHCI_QUIRK_NO_HISPD_BIT | 787 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 788 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 789 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 790 /* 791 * The TRM states that the SD/MMC controller found on 792 * Tegra124 can address 34 bits (the maximum supported by 793 * the Tegra memory controller), but tests show that DMA 794 * to or from above 4 GiB doesn't work. This is possibly 795 * caused by missing programming, though it's not obvious 796 * what sequence is required. Mark 64-bit DMA broken for 797 * now to fix this for existing users (e.g. Nyan boards). 798 */ 799 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 800 .ops = &tegra114_sdhci_ops, 801 }; 802 803 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 804 .pdata = &sdhci_tegra124_pdata, 805 }; 806 807 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 808 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 809 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 810 SDHCI_QUIRK_SINGLE_POWER_WRITE | 811 SDHCI_QUIRK_NO_HISPD_BIT | 812 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 813 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 814 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 815 .ops = &tegra114_sdhci_ops, 816 }; 817 818 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 819 .pdata = &sdhci_tegra210_pdata, 820 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 821 NVQUIRK_HAS_PADCALIB | 822 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 823 }; 824 825 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 826 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 827 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 828 SDHCI_QUIRK_SINGLE_POWER_WRITE | 829 SDHCI_QUIRK_NO_HISPD_BIT | 830 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 831 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 832 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 833 /* SDHCI controllers on Tegra186 support 40-bit addressing. 834 * IOVA addresses are 48-bit wide on Tegra186. 835 * With 64-bit dma mask used for SDHCI, accesses can 836 * be broken. Disable 64-bit dma, which would fall back 837 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 838 * But it is not supported as of now. 839 */ 840 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 841 .ops = &tegra114_sdhci_ops, 842 }; 843 844 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 845 .pdata = &sdhci_tegra186_pdata, 846 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 847 NVQUIRK_HAS_PADCALIB | 848 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 849 }; 850 851 static const struct of_device_id sdhci_tegra_dt_match[] = { 852 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 853 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 854 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 855 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 856 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 857 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 858 {} 859 }; 860 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 861 862 static int sdhci_tegra_probe(struct platform_device *pdev) 863 { 864 const struct of_device_id *match; 865 const struct sdhci_tegra_soc_data *soc_data; 866 struct sdhci_host *host; 867 struct sdhci_pltfm_host *pltfm_host; 868 struct sdhci_tegra *tegra_host; 869 struct clk *clk; 870 int rc; 871 872 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 873 if (!match) 874 return -EINVAL; 875 soc_data = match->data; 876 877 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 878 if (IS_ERR(host)) 879 return PTR_ERR(host); 880 pltfm_host = sdhci_priv(host); 881 882 tegra_host = sdhci_pltfm_priv(pltfm_host); 883 tegra_host->ddr_signaling = false; 884 tegra_host->pad_calib_required = false; 885 tegra_host->pad_control_available = false; 886 tegra_host->soc_data = soc_data; 887 888 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 889 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 890 if (rc == 0) 891 host->mmc_host_ops.start_signal_voltage_switch = 892 sdhci_tegra_start_signal_voltage_switch; 893 } 894 895 rc = mmc_of_parse(host->mmc); 896 if (rc) 897 goto err_parse_dt; 898 899 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 900 host->mmc->caps |= MMC_CAP_1_8V_DDR; 901 902 tegra_sdhci_parse_pad_autocal_dt(host); 903 904 tegra_sdhci_parse_default_tap_and_trim(host); 905 906 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 907 GPIOD_OUT_HIGH); 908 if (IS_ERR(tegra_host->power_gpio)) { 909 rc = PTR_ERR(tegra_host->power_gpio); 910 goto err_power_req; 911 } 912 913 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 914 if (IS_ERR(clk)) { 915 dev_err(mmc_dev(host->mmc), "clk err\n"); 916 rc = PTR_ERR(clk); 917 goto err_clk_get; 918 } 919 clk_prepare_enable(clk); 920 pltfm_host->clk = clk; 921 922 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 923 "sdhci"); 924 if (IS_ERR(tegra_host->rst)) { 925 rc = PTR_ERR(tegra_host->rst); 926 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 927 goto err_rst_get; 928 } 929 930 rc = reset_control_assert(tegra_host->rst); 931 if (rc) 932 goto err_rst_get; 933 934 usleep_range(2000, 4000); 935 936 rc = reset_control_deassert(tegra_host->rst); 937 if (rc) 938 goto err_rst_get; 939 940 usleep_range(2000, 4000); 941 942 rc = sdhci_add_host(host); 943 if (rc) 944 goto err_add_host; 945 946 return 0; 947 948 err_add_host: 949 reset_control_assert(tegra_host->rst); 950 err_rst_get: 951 clk_disable_unprepare(pltfm_host->clk); 952 err_clk_get: 953 err_power_req: 954 err_parse_dt: 955 sdhci_pltfm_free(pdev); 956 return rc; 957 } 958 959 static int sdhci_tegra_remove(struct platform_device *pdev) 960 { 961 struct sdhci_host *host = platform_get_drvdata(pdev); 962 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 963 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 964 965 sdhci_remove_host(host, 0); 966 967 reset_control_assert(tegra_host->rst); 968 usleep_range(2000, 4000); 969 clk_disable_unprepare(pltfm_host->clk); 970 971 sdhci_pltfm_free(pdev); 972 973 return 0; 974 } 975 976 static struct platform_driver sdhci_tegra_driver = { 977 .driver = { 978 .name = "sdhci-tegra", 979 .of_match_table = sdhci_tegra_dt_match, 980 .pm = &sdhci_pltfm_pmops, 981 }, 982 .probe = sdhci_tegra_probe, 983 .remove = sdhci_tegra_remove, 984 }; 985 986 module_platform_driver(sdhci_tegra_driver); 987 988 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 989 MODULE_AUTHOR("Google, Inc."); 990 MODULE_LICENSE("GPL v2"); 991