1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/pm_opp.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/mmc/card.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/mmc/slot-gpio.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/ktime.h> 28 29 #include <soc/tegra/common.h> 30 31 #include "sdhci-cqhci.h" 32 #include "sdhci-pltfm.h" 33 #include "cqhci.h" 34 35 /* Tegra SDHOST controller vendor register definitions */ 36 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 37 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 38 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 39 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 40 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 41 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 42 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 43 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 44 45 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 46 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 47 48 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 49 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 50 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 51 52 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 53 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 54 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 55 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 56 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 57 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 58 59 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 60 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 61 62 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 63 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 64 65 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 66 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 67 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 68 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 69 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 70 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 71 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 72 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 73 #define TRIES_128 2 74 #define TRIES_256 4 75 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 76 77 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 78 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 79 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 80 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 81 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 82 #define TUNING_WORD_BIT_SIZE 32 83 84 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 85 #define SDHCI_AUTO_CAL_START BIT(31) 86 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 87 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 88 89 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 90 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 91 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 92 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 93 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 94 95 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 96 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 97 98 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 99 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 100 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 101 #define NVQUIRK_ENABLE_SDR50 BIT(3) 102 #define NVQUIRK_ENABLE_SDR104 BIT(4) 103 #define NVQUIRK_ENABLE_DDR50 BIT(5) 104 /* 105 * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads 106 * drive strength. 107 */ 108 #define NVQUIRK_HAS_PADCALIB BIT(6) 109 /* 110 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. 111 * 3V3/1V8 pad selection happens through pinctrl state selection depending 112 * on the signaling mode. 113 */ 114 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 115 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 116 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 117 118 /* 119 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra 120 * SDMMC hardware data timeout. 121 */ 122 #define NVQUIRK_HAS_TMCLK BIT(10) 123 124 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 125 126 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 127 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 128 129 #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 130 SDHCI_TRNS_BLK_CNT_EN | \ 131 SDHCI_TRNS_DMA) 132 133 struct sdhci_tegra_soc_data { 134 const struct sdhci_pltfm_data *pdata; 135 u64 dma_mask; 136 u32 nvquirks; 137 u8 min_tap_delay; 138 u8 max_tap_delay; 139 }; 140 141 /* Magic pull up and pull down pad calibration offsets */ 142 struct sdhci_tegra_autocal_offsets { 143 u32 pull_up_3v3; 144 u32 pull_down_3v3; 145 u32 pull_up_3v3_timeout; 146 u32 pull_down_3v3_timeout; 147 u32 pull_up_1v8; 148 u32 pull_down_1v8; 149 u32 pull_up_1v8_timeout; 150 u32 pull_down_1v8_timeout; 151 u32 pull_up_sdr104; 152 u32 pull_down_sdr104; 153 u32 pull_up_hs400; 154 u32 pull_down_hs400; 155 }; 156 157 struct sdhci_tegra { 158 const struct sdhci_tegra_soc_data *soc_data; 159 struct gpio_desc *power_gpio; 160 struct clk *tmclk; 161 bool ddr_signaling; 162 bool pad_calib_required; 163 bool pad_control_available; 164 165 struct reset_control *rst; 166 struct pinctrl *pinctrl_sdmmc; 167 struct pinctrl_state *pinctrl_state_3v3; 168 struct pinctrl_state *pinctrl_state_1v8; 169 struct pinctrl_state *pinctrl_state_3v3_drv; 170 struct pinctrl_state *pinctrl_state_1v8_drv; 171 172 struct sdhci_tegra_autocal_offsets autocal_offsets; 173 ktime_t last_calib; 174 175 u32 default_tap; 176 u32 default_trim; 177 u32 dqs_trim; 178 bool enable_hwcq; 179 unsigned long curr_clk_rate; 180 u8 tuned_tap_delay; 181 }; 182 183 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 187 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 188 189 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 190 (reg == SDHCI_HOST_VERSION))) { 191 /* Erratum: Version register is invalid in HW. */ 192 return SDHCI_SPEC_200; 193 } 194 195 return readw(host->ioaddr + reg); 196 } 197 198 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 199 { 200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 201 202 switch (reg) { 203 case SDHCI_TRANSFER_MODE: 204 /* 205 * Postpone this write, we must do it together with a 206 * command write that is down below. 207 */ 208 pltfm_host->xfer_mode_shadow = val; 209 return; 210 case SDHCI_COMMAND: 211 writel((val << 16) | pltfm_host->xfer_mode_shadow, 212 host->ioaddr + SDHCI_TRANSFER_MODE); 213 return; 214 } 215 216 writew(val, host->ioaddr + reg); 217 } 218 219 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 220 { 221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 223 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 224 225 /* Seems like we're getting spurious timeout and crc errors, so 226 * disable signalling of them. In case of real errors software 227 * timers should take care of eventually detecting them. 228 */ 229 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 230 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 231 232 writel(val, host->ioaddr + reg); 233 234 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 235 (reg == SDHCI_INT_ENABLE))) { 236 /* Erratum: Must enable block gap interrupt detection */ 237 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 238 if (val & SDHCI_INT_CARD_INT) 239 gap_ctrl |= 0x8; 240 else 241 gap_ctrl &= ~0x8; 242 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 243 } 244 } 245 246 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 247 { 248 bool status; 249 u32 reg; 250 251 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 252 status = !!(reg & SDHCI_CLOCK_CARD_EN); 253 254 if (status == enable) 255 return status; 256 257 if (enable) 258 reg |= SDHCI_CLOCK_CARD_EN; 259 else 260 reg &= ~SDHCI_CLOCK_CARD_EN; 261 262 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 263 264 return status; 265 } 266 267 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 268 { 269 bool is_tuning_cmd = 0; 270 bool clk_enabled; 271 u8 cmd; 272 273 if (reg == SDHCI_COMMAND) { 274 cmd = SDHCI_GET_CMD(val); 275 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 276 cmd == MMC_SEND_TUNING_BLOCK_HS200; 277 } 278 279 if (is_tuning_cmd) 280 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 281 282 writew(val, host->ioaddr + reg); 283 284 if (is_tuning_cmd) { 285 udelay(1); 286 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 287 tegra_sdhci_configure_card_clk(host, clk_enabled); 288 } 289 } 290 291 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 292 { 293 /* 294 * Write-enable shall be assumed if GPIO is missing in a board's 295 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 296 * Tegra. 297 */ 298 return mmc_gpio_get_ro(host->mmc); 299 } 300 301 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 302 { 303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 304 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 305 int has_1v8, has_3v3; 306 307 /* 308 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 309 * voltage configuration in order to perform voltage switching. This 310 * means that valid pinctrl info is required on SDHCI instances capable 311 * of performing voltage switching. Whether or not an SDHCI instance is 312 * capable of voltage switching is determined based on the regulator. 313 */ 314 315 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 316 return true; 317 318 if (IS_ERR(host->mmc->supply.vqmmc)) 319 return false; 320 321 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 322 1700000, 1950000); 323 324 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 325 2700000, 3600000); 326 327 if (has_1v8 == 1 && has_3v3 == 1) 328 return tegra_host->pad_control_available; 329 330 /* Fixed voltage, no pad control required. */ 331 return true; 332 } 333 334 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 335 { 336 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 337 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 338 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 339 bool card_clk_enabled = false; 340 u32 reg; 341 342 /* 343 * Touching the tap values is a bit tricky on some SoC generations. 344 * The quirk enables a workaround for a glitch that sometimes occurs if 345 * the tap values are changed. 346 */ 347 348 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 349 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 350 351 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 352 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 353 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 354 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 355 356 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 357 card_clk_enabled) { 358 udelay(1); 359 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 360 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 361 } 362 } 363 364 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 365 { 366 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 367 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 368 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 369 u32 misc_ctrl, clk_ctrl, pad_ctrl; 370 371 sdhci_and_cqhci_reset(host, mask); 372 373 if (!(mask & SDHCI_RESET_ALL)) 374 return; 375 376 tegra_sdhci_set_tap(host, tegra_host->default_tap); 377 378 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 379 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 380 381 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 382 SDHCI_MISC_CTRL_ENABLE_SDR50 | 383 SDHCI_MISC_CTRL_ENABLE_DDR50 | 384 SDHCI_MISC_CTRL_ENABLE_SDR104); 385 386 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 387 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 388 389 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 390 /* Erratum: Enable SDHCI spec v3.00 support */ 391 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 392 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 393 /* Advertise UHS modes as supported by host */ 394 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 395 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 396 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 397 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 398 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 399 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 400 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 401 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 402 } 403 404 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 405 406 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 407 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 408 409 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 410 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 411 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 412 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 413 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 414 415 tegra_host->pad_calib_required = true; 416 } 417 418 tegra_host->ddr_signaling = false; 419 } 420 421 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 422 { 423 u32 val; 424 425 /* 426 * Enable or disable the additional I/O pad used by the drive strength 427 * calibration process. 428 */ 429 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 430 431 if (enable) 432 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 433 else 434 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 435 436 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 437 438 if (enable) 439 usleep_range(1, 2); 440 } 441 442 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 443 u16 pdpu) 444 { 445 u32 reg; 446 447 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 448 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 449 reg |= pdpu; 450 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 451 } 452 453 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 454 bool state_drvupdn) 455 { 456 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 457 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 458 struct sdhci_tegra_autocal_offsets *offsets = 459 &tegra_host->autocal_offsets; 460 struct pinctrl_state *pinctrl_drvupdn = NULL; 461 int ret = 0; 462 u8 drvup = 0, drvdn = 0; 463 u32 reg; 464 465 if (!state_drvupdn) { 466 /* PADS Drive Strength */ 467 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 468 if (tegra_host->pinctrl_state_1v8_drv) { 469 pinctrl_drvupdn = 470 tegra_host->pinctrl_state_1v8_drv; 471 } else { 472 drvup = offsets->pull_up_1v8_timeout; 473 drvdn = offsets->pull_down_1v8_timeout; 474 } 475 } else { 476 if (tegra_host->pinctrl_state_3v3_drv) { 477 pinctrl_drvupdn = 478 tegra_host->pinctrl_state_3v3_drv; 479 } else { 480 drvup = offsets->pull_up_3v3_timeout; 481 drvdn = offsets->pull_down_3v3_timeout; 482 } 483 } 484 485 if (pinctrl_drvupdn != NULL) { 486 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 487 pinctrl_drvupdn); 488 if (ret < 0) 489 dev_err(mmc_dev(host->mmc), 490 "failed pads drvupdn, ret: %d\n", ret); 491 } else if ((drvup) || (drvdn)) { 492 reg = sdhci_readl(host, 493 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 494 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 495 reg |= (drvup << 20) | (drvdn << 12); 496 sdhci_writel(host, reg, 497 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 498 } 499 500 } else { 501 /* Dual Voltage PADS Voltage selection */ 502 if (!tegra_host->pad_control_available) 503 return 0; 504 505 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 506 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 507 tegra_host->pinctrl_state_1v8); 508 if (ret < 0) 509 dev_err(mmc_dev(host->mmc), 510 "setting 1.8V failed, ret: %d\n", ret); 511 } else { 512 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 513 tegra_host->pinctrl_state_3v3); 514 if (ret < 0) 515 dev_err(mmc_dev(host->mmc), 516 "setting 3.3V failed, ret: %d\n", ret); 517 } 518 } 519 520 return ret; 521 } 522 523 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 524 { 525 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 526 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 527 struct sdhci_tegra_autocal_offsets offsets = 528 tegra_host->autocal_offsets; 529 struct mmc_ios *ios = &host->mmc->ios; 530 bool card_clk_enabled; 531 u16 pdpu; 532 u32 reg; 533 int ret; 534 535 switch (ios->timing) { 536 case MMC_TIMING_UHS_SDR104: 537 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 538 break; 539 case MMC_TIMING_MMC_HS400: 540 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 541 break; 542 default: 543 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 544 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 545 else 546 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 547 } 548 549 /* Set initial offset before auto-calibration */ 550 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 551 552 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 553 554 tegra_sdhci_configure_cal_pad(host, true); 555 556 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 557 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 558 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 559 560 usleep_range(1, 2); 561 /* 10 ms timeout */ 562 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 563 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 564 1000, 10000); 565 566 tegra_sdhci_configure_cal_pad(host, false); 567 568 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 569 570 if (ret) { 571 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 572 573 /* Disable automatic cal and use fixed Drive Strengths */ 574 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 575 reg &= ~SDHCI_AUTO_CAL_ENABLE; 576 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 577 578 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 579 if (ret < 0) 580 dev_err(mmc_dev(host->mmc), 581 "Setting drive strengths failed: %d\n", ret); 582 } 583 } 584 585 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 586 { 587 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 588 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 589 struct sdhci_tegra_autocal_offsets *autocal = 590 &tegra_host->autocal_offsets; 591 int err; 592 593 err = device_property_read_u32(mmc_dev(host->mmc), 594 "nvidia,pad-autocal-pull-up-offset-3v3", 595 &autocal->pull_up_3v3); 596 if (err) 597 autocal->pull_up_3v3 = 0; 598 599 err = device_property_read_u32(mmc_dev(host->mmc), 600 "nvidia,pad-autocal-pull-down-offset-3v3", 601 &autocal->pull_down_3v3); 602 if (err) 603 autocal->pull_down_3v3 = 0; 604 605 err = device_property_read_u32(mmc_dev(host->mmc), 606 "nvidia,pad-autocal-pull-up-offset-1v8", 607 &autocal->pull_up_1v8); 608 if (err) 609 autocal->pull_up_1v8 = 0; 610 611 err = device_property_read_u32(mmc_dev(host->mmc), 612 "nvidia,pad-autocal-pull-down-offset-1v8", 613 &autocal->pull_down_1v8); 614 if (err) 615 autocal->pull_down_1v8 = 0; 616 617 err = device_property_read_u32(mmc_dev(host->mmc), 618 "nvidia,pad-autocal-pull-up-offset-sdr104", 619 &autocal->pull_up_sdr104); 620 if (err) 621 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 622 623 err = device_property_read_u32(mmc_dev(host->mmc), 624 "nvidia,pad-autocal-pull-down-offset-sdr104", 625 &autocal->pull_down_sdr104); 626 if (err) 627 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 628 629 err = device_property_read_u32(mmc_dev(host->mmc), 630 "nvidia,pad-autocal-pull-up-offset-hs400", 631 &autocal->pull_up_hs400); 632 if (err) 633 autocal->pull_up_hs400 = autocal->pull_up_1v8; 634 635 err = device_property_read_u32(mmc_dev(host->mmc), 636 "nvidia,pad-autocal-pull-down-offset-hs400", 637 &autocal->pull_down_hs400); 638 if (err) 639 autocal->pull_down_hs400 = autocal->pull_down_1v8; 640 641 /* 642 * Different fail-safe drive strength values based on the signaling 643 * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. 644 * So, avoid reading below device tree properties for SoCs that don't 645 * have NVQUIRK_NEEDS_PAD_CONTROL. 646 */ 647 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 648 return; 649 650 err = device_property_read_u32(mmc_dev(host->mmc), 651 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 652 &autocal->pull_up_3v3_timeout); 653 if (err) { 654 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 655 (tegra_host->pinctrl_state_3v3_drv == NULL)) 656 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 657 mmc_hostname(host->mmc)); 658 autocal->pull_up_3v3_timeout = 0; 659 } 660 661 err = device_property_read_u32(mmc_dev(host->mmc), 662 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 663 &autocal->pull_down_3v3_timeout); 664 if (err) { 665 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 666 (tegra_host->pinctrl_state_3v3_drv == NULL)) 667 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 668 mmc_hostname(host->mmc)); 669 autocal->pull_down_3v3_timeout = 0; 670 } 671 672 err = device_property_read_u32(mmc_dev(host->mmc), 673 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 674 &autocal->pull_up_1v8_timeout); 675 if (err) { 676 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 677 (tegra_host->pinctrl_state_1v8_drv == NULL)) 678 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 679 mmc_hostname(host->mmc)); 680 autocal->pull_up_1v8_timeout = 0; 681 } 682 683 err = device_property_read_u32(mmc_dev(host->mmc), 684 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 685 &autocal->pull_down_1v8_timeout); 686 if (err) { 687 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 688 (tegra_host->pinctrl_state_1v8_drv == NULL)) 689 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 690 mmc_hostname(host->mmc)); 691 autocal->pull_down_1v8_timeout = 0; 692 } 693 } 694 695 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 696 { 697 struct sdhci_host *host = mmc_priv(mmc); 698 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 699 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 700 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 701 702 /* 100 ms calibration interval is specified in the TRM */ 703 if (ktime_to_ms(since_calib) > 100) { 704 tegra_sdhci_pad_autocalib(host); 705 tegra_host->last_calib = ktime_get(); 706 } 707 708 sdhci_request(mmc, mrq); 709 } 710 711 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 712 { 713 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 714 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 715 int err; 716 717 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", 718 &tegra_host->default_tap); 719 if (err) 720 tegra_host->default_tap = 0; 721 722 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", 723 &tegra_host->default_trim); 724 if (err) 725 tegra_host->default_trim = 0; 726 727 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", 728 &tegra_host->dqs_trim); 729 if (err) 730 tegra_host->dqs_trim = 0x11; 731 } 732 733 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 734 { 735 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 736 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 737 738 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) 739 tegra_host->enable_hwcq = true; 740 else 741 tegra_host->enable_hwcq = false; 742 743 tegra_sdhci_parse_pad_autocal_dt(host); 744 tegra_sdhci_parse_tap_and_trim(host); 745 } 746 747 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 748 { 749 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 750 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 751 struct device *dev = mmc_dev(host->mmc); 752 unsigned long host_clk; 753 int err; 754 755 if (!clock) 756 return sdhci_set_clock(host, clock); 757 758 /* 759 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 760 * divider to be configured to divided the host clock by two. The SDHCI 761 * clock divider is calculated as part of sdhci_set_clock() by 762 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 763 * the requested clock rate. 764 * 765 * By setting the host->max_clk to clock * 2 the divider calculation 766 * will always result in the correct value for DDR50/52 modes, 767 * regardless of clock rate rounding, which may happen if the value 768 * from clk_get_rate() is used. 769 */ 770 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 771 772 err = dev_pm_opp_set_rate(dev, host_clk); 773 if (err) 774 dev_err(dev, "failed to set clk rate to %luHz: %d\n", 775 host_clk, err); 776 777 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); 778 if (tegra_host->ddr_signaling) 779 host->max_clk = host_clk; 780 else 781 host->max_clk = clk_get_rate(pltfm_host->clk); 782 783 sdhci_set_clock(host, clock); 784 785 if (tegra_host->pad_calib_required) { 786 tegra_sdhci_pad_autocalib(host); 787 tegra_host->pad_calib_required = false; 788 } 789 } 790 791 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 792 struct mmc_ios *ios) 793 { 794 struct sdhci_host *host = mmc_priv(mmc); 795 u32 val; 796 797 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 798 799 if (ios->enhanced_strobe) { 800 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 801 /* 802 * When CMD13 is sent from mmc_select_hs400es() after 803 * switching to HS400ES mode, the bus is operating at 804 * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. 805 * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI 806 * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host 807 * controller CAR clock and the interface clock are rate matched. 808 */ 809 tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); 810 } else { 811 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 812 } 813 814 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 815 } 816 817 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 818 { 819 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 820 821 return clk_round_rate(pltfm_host->clk, UINT_MAX); 822 } 823 824 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 825 { 826 u32 val; 827 828 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 829 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 830 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 831 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 832 } 833 834 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 835 { 836 u32 reg; 837 int err; 838 839 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 840 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 841 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 842 843 /* 1 ms sleep, 5 ms timeout */ 844 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 845 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 846 1000, 5000); 847 if (err) 848 dev_err(mmc_dev(host->mmc), 849 "HS400 delay line calibration timed out\n"); 850 } 851 852 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 853 u8 thd_low, u8 fixed_tap) 854 { 855 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 856 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 857 u32 val, tun_status; 858 u8 word, bit, edge1, tap, window; 859 bool tap_result; 860 bool start_fail = false; 861 bool start_pass = false; 862 bool end_pass = false; 863 bool first_fail = false; 864 bool first_pass = false; 865 u8 start_pass_tap = 0; 866 u8 end_pass_tap = 0; 867 u8 first_fail_tap = 0; 868 u8 first_pass_tap = 0; 869 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 870 871 /* 872 * Read auto-tuned results and extract good valid passing window by 873 * filtering out un-wanted bubble/partial/merged windows. 874 */ 875 for (word = 0; word < total_tuning_words; word++) { 876 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 877 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 878 val |= word; 879 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 880 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 881 bit = 0; 882 while (bit < TUNING_WORD_BIT_SIZE) { 883 tap = word * TUNING_WORD_BIT_SIZE + bit; 884 tap_result = tun_status & (1 << bit); 885 if (!tap_result && !start_fail) { 886 start_fail = true; 887 if (!first_fail) { 888 first_fail_tap = tap; 889 first_fail = true; 890 } 891 892 } else if (tap_result && start_fail && !start_pass) { 893 start_pass_tap = tap; 894 start_pass = true; 895 if (!first_pass) { 896 first_pass_tap = tap; 897 first_pass = true; 898 } 899 900 } else if (!tap_result && start_fail && start_pass && 901 !end_pass) { 902 end_pass_tap = tap - 1; 903 end_pass = true; 904 } else if (tap_result && start_pass && start_fail && 905 end_pass) { 906 window = end_pass_tap - start_pass_tap; 907 /* discard merged window and bubble window */ 908 if (window >= thd_up || window < thd_low) { 909 start_pass_tap = tap; 910 end_pass = false; 911 } else { 912 /* set tap at middle of valid window */ 913 tap = start_pass_tap + window / 2; 914 tegra_host->tuned_tap_delay = tap; 915 return; 916 } 917 } 918 919 bit++; 920 } 921 } 922 923 if (!first_fail) { 924 WARN(1, "no edge detected, continue with hw tuned delay.\n"); 925 } else if (first_pass) { 926 /* set tap location at fixed tap relative to the first edge */ 927 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 928 if (edge1 - 1 > fixed_tap) 929 tegra_host->tuned_tap_delay = edge1 - fixed_tap; 930 else 931 tegra_host->tuned_tap_delay = edge1 + fixed_tap; 932 } 933 } 934 935 static void tegra_sdhci_post_tuning(struct sdhci_host *host) 936 { 937 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 938 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 939 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 940 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 941 u8 fixed_tap, start_tap, end_tap, window_width; 942 u8 thdupper, thdlower; 943 u8 num_iter; 944 u32 clk_rate_mhz, period_ps, bestcase, worstcase; 945 946 /* retain HW tuned tap to use incase if no correction is needed */ 947 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 948 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 949 SDHCI_CLOCK_CTRL_TAP_SHIFT; 950 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 951 min_tap_dly = soc_data->min_tap_delay; 952 max_tap_dly = soc_data->max_tap_delay; 953 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 954 period_ps = USEC_PER_SEC / clk_rate_mhz; 955 bestcase = period_ps / min_tap_dly; 956 worstcase = period_ps / max_tap_dly; 957 /* 958 * Upper and Lower bound thresholds used to detect merged and 959 * bubble windows 960 */ 961 thdupper = (2 * worstcase + bestcase) / 2; 962 thdlower = worstcase / 4; 963 /* 964 * fixed tap is used when HW tuning result contains single edge 965 * and tap is set at fixed tap delay relative to the first edge 966 */ 967 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 968 fixed_tap = avg_tap_dly / 2; 969 970 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 971 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 972 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 973 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 974 window_width = end_tap - start_tap; 975 num_iter = host->tuning_loop_count; 976 /* 977 * partial window includes edges of the tuning range. 978 * merged window includes more taps so window width is higher 979 * than upper threshold. 980 */ 981 if (start_tap == 0 || (end_tap == (num_iter - 1)) || 982 (end_tap == num_iter - 2) || window_width >= thdupper) { 983 pr_debug("%s: Apply tuning correction\n", 984 mmc_hostname(host->mmc)); 985 tegra_sdhci_tap_correction(host, thdupper, thdlower, 986 fixed_tap); 987 } 988 } 989 990 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 991 } 992 993 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 994 { 995 struct sdhci_host *host = mmc_priv(mmc); 996 int err; 997 998 err = sdhci_execute_tuning(mmc, opcode); 999 if (!err && !host->tuning_err) 1000 tegra_sdhci_post_tuning(host); 1001 1002 return err; 1003 } 1004 1005 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 1006 unsigned timing) 1007 { 1008 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1009 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1010 bool set_default_tap = false; 1011 bool set_dqs_trim = false; 1012 bool do_hs400_dll_cal = false; 1013 u8 iter = TRIES_256; 1014 u32 val; 1015 1016 tegra_host->ddr_signaling = false; 1017 switch (timing) { 1018 case MMC_TIMING_UHS_SDR50: 1019 break; 1020 case MMC_TIMING_UHS_SDR104: 1021 case MMC_TIMING_MMC_HS200: 1022 /* Don't set default tap on tunable modes. */ 1023 iter = TRIES_128; 1024 break; 1025 case MMC_TIMING_MMC_HS400: 1026 set_dqs_trim = true; 1027 do_hs400_dll_cal = true; 1028 iter = TRIES_128; 1029 break; 1030 case MMC_TIMING_MMC_DDR52: 1031 case MMC_TIMING_UHS_DDR50: 1032 tegra_host->ddr_signaling = true; 1033 set_default_tap = true; 1034 break; 1035 default: 1036 set_default_tap = true; 1037 break; 1038 } 1039 1040 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 1041 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 1042 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 1043 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 1044 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 1045 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 1046 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 1047 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 1048 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 1049 1050 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 1051 1052 sdhci_set_uhs_signaling(host, timing); 1053 1054 tegra_sdhci_pad_autocalib(host); 1055 1056 if (tegra_host->tuned_tap_delay && !set_default_tap) 1057 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1058 else 1059 tegra_sdhci_set_tap(host, tegra_host->default_tap); 1060 1061 if (set_dqs_trim) 1062 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1063 1064 if (do_hs400_dll_cal) 1065 tegra_sdhci_hs400_dll_cal(host); 1066 } 1067 1068 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1069 { 1070 unsigned int min, max; 1071 1072 /* 1073 * Start search for minimum tap value at 10, as smaller values are 1074 * may wrongly be reported as working but fail at higher speeds, 1075 * according to the TRM. 1076 */ 1077 min = 10; 1078 while (min < 255) { 1079 tegra_sdhci_set_tap(host, min); 1080 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1081 break; 1082 min++; 1083 } 1084 1085 /* Find the maximum tap value that still passes. */ 1086 max = min + 1; 1087 while (max < 255) { 1088 tegra_sdhci_set_tap(host, max); 1089 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1090 max--; 1091 break; 1092 } 1093 max++; 1094 } 1095 1096 /* The TRM states the ideal tap value is at 75% in the passing range. */ 1097 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1098 1099 return mmc_send_tuning(host->mmc, opcode, NULL); 1100 } 1101 1102 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 1103 struct mmc_ios *ios) 1104 { 1105 struct sdhci_host *host = mmc_priv(mmc); 1106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1107 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1108 int ret = 0; 1109 1110 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1111 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1112 if (ret < 0) 1113 return ret; 1114 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1115 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 1116 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1117 if (ret < 0) 1118 return ret; 1119 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1120 } 1121 1122 if (tegra_host->pad_calib_required) 1123 tegra_sdhci_pad_autocalib(host); 1124 1125 return ret; 1126 } 1127 1128 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 1129 struct sdhci_tegra *tegra_host) 1130 { 1131 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 1132 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 1133 dev_dbg(dev, "No pinctrl info, err: %ld\n", 1134 PTR_ERR(tegra_host->pinctrl_sdmmc)); 1135 return -1; 1136 } 1137 1138 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1139 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1140 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1141 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1142 tegra_host->pinctrl_state_1v8_drv = NULL; 1143 } 1144 1145 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1146 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1147 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1148 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1149 tegra_host->pinctrl_state_3v3_drv = NULL; 1150 } 1151 1152 tegra_host->pinctrl_state_3v3 = 1153 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 1154 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 1155 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 1156 PTR_ERR(tegra_host->pinctrl_state_3v3)); 1157 return -1; 1158 } 1159 1160 tegra_host->pinctrl_state_1v8 = 1161 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 1162 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 1163 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1164 PTR_ERR(tegra_host->pinctrl_state_1v8)); 1165 return -1; 1166 } 1167 1168 tegra_host->pad_control_available = true; 1169 1170 return 0; 1171 } 1172 1173 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1174 { 1175 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1176 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1177 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1178 1179 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1180 tegra_host->pad_calib_required = true; 1181 } 1182 1183 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1184 { 1185 struct mmc_host *mmc = cq_host->mmc; 1186 struct sdhci_host *host = mmc_priv(mmc); 1187 u8 ctrl; 1188 ktime_t timeout; 1189 bool timed_out; 1190 1191 /* 1192 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1193 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1194 * to be re-configured. 1195 * Tegra CQHCI/SDHCI prevents write access to block size register when 1196 * CQE is unhalted. So handling CQE resume sequence here to configure 1197 * SDHCI block registers prior to exiting CQE halt state. 1198 */ 1199 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1200 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 1201 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1202 sdhci_cqe_enable(mmc); 1203 writel(val, cq_host->mmio + reg); 1204 timeout = ktime_add_us(ktime_get(), 50); 1205 while (1) { 1206 timed_out = ktime_compare(ktime_get(), timeout) > 0; 1207 ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1208 if (!(ctrl & CQHCI_HALT) || timed_out) 1209 break; 1210 } 1211 /* 1212 * CQE usually resumes very quick, but incase if Tegra CQE 1213 * doesn't resume retry unhalt. 1214 */ 1215 if (timed_out) 1216 writel(val, cq_host->mmio + reg); 1217 } else { 1218 writel(val, cq_host->mmio + reg); 1219 } 1220 } 1221 1222 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1223 struct mmc_request *mrq, u64 *data) 1224 { 1225 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1226 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1227 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1228 1229 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1230 mrq->cmd->flags & MMC_RSP_R1B) 1231 *data |= CQHCI_CMD_TIMING(1); 1232 } 1233 1234 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 1235 { 1236 struct cqhci_host *cq_host = mmc->cqe_private; 1237 struct sdhci_host *host = mmc_priv(mmc); 1238 u32 val; 1239 1240 /* 1241 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1242 * register when CQE is enabled and unhalted. 1243 * CQHCI driver enables CQE prior to activation, so disable CQE before 1244 * programming block size in sdhci controller and enable it back. 1245 */ 1246 if (!cq_host->activated) { 1247 val = cqhci_readl(cq_host, CQHCI_CFG); 1248 if (val & CQHCI_ENABLE) 1249 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1250 CQHCI_CFG); 1251 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1252 sdhci_cqe_enable(mmc); 1253 if (val & CQHCI_ENABLE) 1254 cqhci_writel(cq_host, val, CQHCI_CFG); 1255 } 1256 1257 /* 1258 * CMD CRC errors are seen sometimes with some eMMC devices when status 1259 * command is sent during transfer of last data block which is the 1260 * default case as send status command block counter (CBC) is 1. 1261 * Recommended fix to set CBC to 0 allowing send status command only 1262 * when data lines are idle. 1263 */ 1264 val = cqhci_readl(cq_host, CQHCI_SSC1); 1265 val &= ~CQHCI_SSC1_CBC_MASK; 1266 cqhci_writel(cq_host, val, CQHCI_SSC1); 1267 } 1268 1269 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 1270 { 1271 sdhci_dumpregs(mmc_priv(mmc)); 1272 } 1273 1274 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 1275 { 1276 int cmd_error = 0; 1277 int data_error = 0; 1278 1279 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1280 return intmask; 1281 1282 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1283 1284 return 0; 1285 } 1286 1287 static void tegra_sdhci_set_timeout(struct sdhci_host *host, 1288 struct mmc_command *cmd) 1289 { 1290 u32 val; 1291 1292 /* 1293 * HW busy detection timeout is based on programmed data timeout 1294 * counter and maximum supported timeout is 11s which may not be 1295 * enough for long operations like cache flush, sleep awake, erase. 1296 * 1297 * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 1298 * host controller to wait for busy state until the card is busy 1299 * without HW timeout. 1300 * 1301 * So, use infinite busy wait mode for operations that may take 1302 * more than maximum HW busy timeout of 11s otherwise use finite 1303 * busy wait mode. 1304 */ 1305 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1306 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) 1307 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1308 else 1309 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1310 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1311 1312 __sdhci_set_timeout(host, cmd); 1313 } 1314 1315 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc) 1316 { 1317 struct cqhci_host *cq_host = mmc->cqe_private; 1318 u32 reg; 1319 1320 reg = cqhci_readl(cq_host, CQHCI_CFG); 1321 reg |= CQHCI_ENABLE; 1322 cqhci_writel(cq_host, reg, CQHCI_CFG); 1323 } 1324 1325 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc) 1326 { 1327 struct cqhci_host *cq_host = mmc->cqe_private; 1328 struct sdhci_host *host = mmc_priv(mmc); 1329 u32 reg; 1330 1331 reg = cqhci_readl(cq_host, CQHCI_CFG); 1332 reg &= ~CQHCI_ENABLE; 1333 cqhci_writel(cq_host, reg, CQHCI_CFG); 1334 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1335 } 1336 1337 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1338 .write_l = tegra_cqhci_writel, 1339 .enable = sdhci_tegra_cqe_enable, 1340 .disable = sdhci_cqe_disable, 1341 .dumpregs = sdhci_tegra_dumpregs, 1342 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 1343 .pre_enable = sdhci_tegra_cqe_pre_enable, 1344 .post_disable = sdhci_tegra_cqe_post_disable, 1345 }; 1346 1347 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1348 { 1349 struct sdhci_pltfm_host *platform = sdhci_priv(host); 1350 struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1351 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1352 struct device *dev = mmc_dev(host->mmc); 1353 1354 if (soc->dma_mask) 1355 return dma_set_mask_and_coherent(dev, soc->dma_mask); 1356 1357 return 0; 1358 } 1359 1360 static const struct sdhci_ops tegra_sdhci_ops = { 1361 .get_ro = tegra_sdhci_get_ro, 1362 .read_w = tegra_sdhci_readw, 1363 .write_l = tegra_sdhci_writel, 1364 .set_clock = tegra_sdhci_set_clock, 1365 .set_dma_mask = tegra_sdhci_set_dma_mask, 1366 .set_bus_width = sdhci_set_bus_width, 1367 .reset = tegra_sdhci_reset, 1368 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1369 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1370 .voltage_switch = tegra_sdhci_voltage_switch, 1371 .get_max_clock = tegra_sdhci_get_max_clock, 1372 }; 1373 1374 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 1375 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1376 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1377 SDHCI_QUIRK_NO_HISPD_BIT | 1378 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1379 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1380 .ops = &tegra_sdhci_ops, 1381 }; 1382 1383 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1384 .pdata = &sdhci_tegra20_pdata, 1385 .dma_mask = DMA_BIT_MASK(32), 1386 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1387 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1388 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1389 }; 1390 1391 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1392 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1393 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1394 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1395 SDHCI_QUIRK_NO_HISPD_BIT | 1396 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1397 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1398 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1399 SDHCI_QUIRK2_BROKEN_HS200 | 1400 /* 1401 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1402 * though no command operation was in progress." 1403 * 1404 * The exact reason is unknown, as the same hardware seems 1405 * to support Auto CMD23 on a downstream 3.1 kernel. 1406 */ 1407 SDHCI_QUIRK2_ACMD23_BROKEN, 1408 .ops = &tegra_sdhci_ops, 1409 }; 1410 1411 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1412 .pdata = &sdhci_tegra30_pdata, 1413 .dma_mask = DMA_BIT_MASK(32), 1414 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1415 NVQUIRK_ENABLE_SDR50 | 1416 NVQUIRK_ENABLE_SDR104 | 1417 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1418 NVQUIRK_HAS_PADCALIB, 1419 }; 1420 1421 static const struct sdhci_ops tegra114_sdhci_ops = { 1422 .get_ro = tegra_sdhci_get_ro, 1423 .read_w = tegra_sdhci_readw, 1424 .write_w = tegra_sdhci_writew, 1425 .write_l = tegra_sdhci_writel, 1426 .set_clock = tegra_sdhci_set_clock, 1427 .set_dma_mask = tegra_sdhci_set_dma_mask, 1428 .set_bus_width = sdhci_set_bus_width, 1429 .reset = tegra_sdhci_reset, 1430 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1431 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1432 .voltage_switch = tegra_sdhci_voltage_switch, 1433 .get_max_clock = tegra_sdhci_get_max_clock, 1434 }; 1435 1436 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1437 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1438 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1439 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1440 SDHCI_QUIRK_NO_HISPD_BIT | 1441 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1442 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1443 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1444 .ops = &tegra114_sdhci_ops, 1445 }; 1446 1447 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1448 .pdata = &sdhci_tegra114_pdata, 1449 .dma_mask = DMA_BIT_MASK(32), 1450 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1451 }; 1452 1453 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1454 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1455 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1456 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1457 SDHCI_QUIRK_NO_HISPD_BIT | 1458 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1459 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1460 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1461 .ops = &tegra114_sdhci_ops, 1462 }; 1463 1464 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1465 .pdata = &sdhci_tegra124_pdata, 1466 .dma_mask = DMA_BIT_MASK(34), 1467 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1468 }; 1469 1470 static const struct sdhci_ops tegra210_sdhci_ops = { 1471 .get_ro = tegra_sdhci_get_ro, 1472 .read_w = tegra_sdhci_readw, 1473 .write_w = tegra210_sdhci_writew, 1474 .write_l = tegra_sdhci_writel, 1475 .set_clock = tegra_sdhci_set_clock, 1476 .set_dma_mask = tegra_sdhci_set_dma_mask, 1477 .set_bus_width = sdhci_set_bus_width, 1478 .reset = tegra_sdhci_reset, 1479 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1480 .voltage_switch = tegra_sdhci_voltage_switch, 1481 .get_max_clock = tegra_sdhci_get_max_clock, 1482 .set_timeout = tegra_sdhci_set_timeout, 1483 }; 1484 1485 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1486 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1487 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1488 SDHCI_QUIRK_NO_HISPD_BIT | 1489 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1490 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1491 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1492 .ops = &tegra210_sdhci_ops, 1493 }; 1494 1495 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1496 .pdata = &sdhci_tegra210_pdata, 1497 .dma_mask = DMA_BIT_MASK(34), 1498 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1499 NVQUIRK_HAS_PADCALIB | 1500 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1501 NVQUIRK_ENABLE_SDR50 | 1502 NVQUIRK_ENABLE_SDR104 | 1503 NVQUIRK_HAS_TMCLK, 1504 .min_tap_delay = 106, 1505 .max_tap_delay = 185, 1506 }; 1507 1508 static const struct sdhci_ops tegra186_sdhci_ops = { 1509 .get_ro = tegra_sdhci_get_ro, 1510 .read_w = tegra_sdhci_readw, 1511 .write_l = tegra_sdhci_writel, 1512 .set_clock = tegra_sdhci_set_clock, 1513 .set_dma_mask = tegra_sdhci_set_dma_mask, 1514 .set_bus_width = sdhci_set_bus_width, 1515 .reset = tegra_sdhci_reset, 1516 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1517 .voltage_switch = tegra_sdhci_voltage_switch, 1518 .get_max_clock = tegra_sdhci_get_max_clock, 1519 .irq = sdhci_tegra_cqhci_irq, 1520 .set_timeout = tegra_sdhci_set_timeout, 1521 }; 1522 1523 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1524 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1525 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1526 SDHCI_QUIRK_NO_HISPD_BIT | 1527 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1528 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1529 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1530 .ops = &tegra186_sdhci_ops, 1531 }; 1532 1533 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1534 .pdata = &sdhci_tegra186_pdata, 1535 .dma_mask = DMA_BIT_MASK(40), 1536 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1537 NVQUIRK_HAS_PADCALIB | 1538 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1539 NVQUIRK_ENABLE_SDR50 | 1540 NVQUIRK_ENABLE_SDR104 | 1541 NVQUIRK_HAS_TMCLK | 1542 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1543 .min_tap_delay = 84, 1544 .max_tap_delay = 136, 1545 }; 1546 1547 static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1548 .pdata = &sdhci_tegra186_pdata, 1549 .dma_mask = DMA_BIT_MASK(39), 1550 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1551 NVQUIRK_HAS_PADCALIB | 1552 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1553 NVQUIRK_ENABLE_SDR50 | 1554 NVQUIRK_ENABLE_SDR104 | 1555 NVQUIRK_HAS_TMCLK, 1556 .min_tap_delay = 96, 1557 .max_tap_delay = 139, 1558 }; 1559 1560 static const struct of_device_id sdhci_tegra_dt_match[] = { 1561 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1562 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1563 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1564 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1565 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1566 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1567 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1568 {} 1569 }; 1570 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1571 1572 static int sdhci_tegra_add_host(struct sdhci_host *host) 1573 { 1574 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1575 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1576 struct cqhci_host *cq_host; 1577 bool dma64; 1578 int ret; 1579 1580 if (!tegra_host->enable_hwcq) 1581 return sdhci_add_host(host); 1582 1583 sdhci_enable_v4_mode(host); 1584 1585 ret = sdhci_setup_host(host); 1586 if (ret) 1587 return ret; 1588 1589 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1590 1591 cq_host = devm_kzalloc(mmc_dev(host->mmc), 1592 sizeof(*cq_host), GFP_KERNEL); 1593 if (!cq_host) { 1594 ret = -ENOMEM; 1595 goto cleanup; 1596 } 1597 1598 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1599 cq_host->ops = &sdhci_tegra_cqhci_ops; 1600 1601 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1602 if (dma64) 1603 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1604 1605 ret = cqhci_init(cq_host, host->mmc, dma64); 1606 if (ret) 1607 goto cleanup; 1608 1609 ret = __sdhci_add_host(host); 1610 if (ret) 1611 goto cleanup; 1612 1613 return 0; 1614 1615 cleanup: 1616 sdhci_cleanup_host(host); 1617 return ret; 1618 } 1619 1620 static int sdhci_tegra_probe(struct platform_device *pdev) 1621 { 1622 const struct sdhci_tegra_soc_data *soc_data; 1623 struct sdhci_host *host; 1624 struct sdhci_pltfm_host *pltfm_host; 1625 struct sdhci_tegra *tegra_host; 1626 struct clk *clk; 1627 int rc; 1628 1629 soc_data = of_device_get_match_data(&pdev->dev); 1630 if (!soc_data) 1631 return -EINVAL; 1632 1633 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1634 if (IS_ERR(host)) 1635 return PTR_ERR(host); 1636 pltfm_host = sdhci_priv(host); 1637 1638 tegra_host = sdhci_pltfm_priv(pltfm_host); 1639 tegra_host->ddr_signaling = false; 1640 tegra_host->pad_calib_required = false; 1641 tegra_host->pad_control_available = false; 1642 tegra_host->soc_data = soc_data; 1643 1644 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) 1645 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; 1646 1647 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1648 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1649 if (rc == 0) 1650 host->mmc_host_ops.start_signal_voltage_switch = 1651 sdhci_tegra_start_signal_voltage_switch; 1652 } 1653 1654 /* Hook to periodically rerun pad calibration */ 1655 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1656 host->mmc_host_ops.request = tegra_sdhci_request; 1657 1658 host->mmc_host_ops.hs400_enhanced_strobe = 1659 tegra_sdhci_hs400_enhanced_strobe; 1660 1661 if (!host->ops->platform_execute_tuning) 1662 host->mmc_host_ops.execute_tuning = 1663 tegra_sdhci_execute_hw_tuning; 1664 1665 rc = mmc_of_parse(host->mmc); 1666 if (rc) 1667 goto err_parse_dt; 1668 1669 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1670 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1671 1672 /* HW busy detection is supported, but R1B responses are required. */ 1673 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1674 1675 /* GPIO CD can be set as a wakeup source */ 1676 host->mmc->caps |= MMC_CAP_CD_WAKE; 1677 1678 tegra_sdhci_parse_dt(host); 1679 1680 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1681 GPIOD_OUT_HIGH); 1682 if (IS_ERR(tegra_host->power_gpio)) { 1683 rc = PTR_ERR(tegra_host->power_gpio); 1684 goto err_power_req; 1685 } 1686 1687 /* 1688 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host 1689 * timeout clock and SW can choose TMCLK or SDCLK for hardware 1690 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of 1691 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL. 1692 * 1693 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses 1694 * 12Mhz TMCLK which is advertised in host capability register. 1695 * With TMCLK of 12Mhz provides maximum data timeout period that can 1696 * be achieved is 11s better than using SDCLK for data timeout. 1697 * 1698 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's 1699 * supporting separate TMCLK. 1700 */ 1701 1702 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { 1703 clk = devm_clk_get(&pdev->dev, "tmclk"); 1704 if (IS_ERR(clk)) { 1705 rc = PTR_ERR(clk); 1706 if (rc == -EPROBE_DEFER) 1707 goto err_power_req; 1708 1709 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 1710 clk = NULL; 1711 } 1712 1713 clk_set_rate(clk, 12000000); 1714 rc = clk_prepare_enable(clk); 1715 if (rc) { 1716 dev_err(&pdev->dev, 1717 "failed to enable tmclk: %d\n", rc); 1718 goto err_power_req; 1719 } 1720 1721 tegra_host->tmclk = clk; 1722 } 1723 1724 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1725 if (IS_ERR(clk)) { 1726 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), 1727 "failed to get clock\n"); 1728 goto err_clk_get; 1729 } 1730 pltfm_host->clk = clk; 1731 1732 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1733 "sdhci"); 1734 if (IS_ERR(tegra_host->rst)) { 1735 rc = PTR_ERR(tegra_host->rst); 1736 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1737 goto err_rst_get; 1738 } 1739 1740 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1741 if (rc) 1742 goto err_rst_get; 1743 1744 pm_runtime_enable(&pdev->dev); 1745 rc = pm_runtime_resume_and_get(&pdev->dev); 1746 if (rc) 1747 goto err_pm_get; 1748 1749 rc = reset_control_assert(tegra_host->rst); 1750 if (rc) 1751 goto err_rst_assert; 1752 1753 usleep_range(2000, 4000); 1754 1755 rc = reset_control_deassert(tegra_host->rst); 1756 if (rc) 1757 goto err_rst_assert; 1758 1759 usleep_range(2000, 4000); 1760 1761 rc = sdhci_tegra_add_host(host); 1762 if (rc) 1763 goto err_add_host; 1764 1765 return 0; 1766 1767 err_add_host: 1768 reset_control_assert(tegra_host->rst); 1769 err_rst_assert: 1770 pm_runtime_put_sync_suspend(&pdev->dev); 1771 err_pm_get: 1772 pm_runtime_disable(&pdev->dev); 1773 err_rst_get: 1774 err_clk_get: 1775 clk_disable_unprepare(tegra_host->tmclk); 1776 err_power_req: 1777 err_parse_dt: 1778 sdhci_pltfm_free(pdev); 1779 return rc; 1780 } 1781 1782 static int sdhci_tegra_remove(struct platform_device *pdev) 1783 { 1784 struct sdhci_host *host = platform_get_drvdata(pdev); 1785 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1786 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1787 1788 sdhci_remove_host(host, 0); 1789 1790 reset_control_assert(tegra_host->rst); 1791 usleep_range(2000, 4000); 1792 1793 pm_runtime_put_sync_suspend(&pdev->dev); 1794 pm_runtime_force_suspend(&pdev->dev); 1795 1796 clk_disable_unprepare(tegra_host->tmclk); 1797 sdhci_pltfm_free(pdev); 1798 1799 return 0; 1800 } 1801 1802 static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev) 1803 { 1804 struct sdhci_host *host = dev_get_drvdata(dev); 1805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1806 1807 clk_disable_unprepare(pltfm_host->clk); 1808 1809 return 0; 1810 } 1811 1812 static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev) 1813 { 1814 struct sdhci_host *host = dev_get_drvdata(dev); 1815 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1816 1817 return clk_prepare_enable(pltfm_host->clk); 1818 } 1819 1820 #ifdef CONFIG_PM_SLEEP 1821 static int sdhci_tegra_suspend(struct device *dev) 1822 { 1823 struct sdhci_host *host = dev_get_drvdata(dev); 1824 int ret; 1825 1826 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1827 ret = cqhci_suspend(host->mmc); 1828 if (ret) 1829 return ret; 1830 } 1831 1832 ret = sdhci_suspend_host(host); 1833 if (ret) { 1834 cqhci_resume(host->mmc); 1835 return ret; 1836 } 1837 1838 ret = pm_runtime_force_suspend(dev); 1839 if (ret) { 1840 sdhci_resume_host(host); 1841 cqhci_resume(host->mmc); 1842 return ret; 1843 } 1844 1845 return mmc_gpio_set_cd_wake(host->mmc, true); 1846 } 1847 1848 static int sdhci_tegra_resume(struct device *dev) 1849 { 1850 struct sdhci_host *host = dev_get_drvdata(dev); 1851 int ret; 1852 1853 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1854 if (ret) 1855 return ret; 1856 1857 ret = pm_runtime_force_resume(dev); 1858 if (ret) 1859 return ret; 1860 1861 ret = sdhci_resume_host(host); 1862 if (ret) 1863 goto disable_clk; 1864 1865 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1866 ret = cqhci_resume(host->mmc); 1867 if (ret) 1868 goto suspend_host; 1869 } 1870 1871 return 0; 1872 1873 suspend_host: 1874 sdhci_suspend_host(host); 1875 disable_clk: 1876 pm_runtime_force_suspend(dev); 1877 return ret; 1878 } 1879 #endif 1880 1881 static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = { 1882 SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume, 1883 NULL) 1884 SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume) 1885 }; 1886 1887 static struct platform_driver sdhci_tegra_driver = { 1888 .driver = { 1889 .name = "sdhci-tegra", 1890 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1891 .of_match_table = sdhci_tegra_dt_match, 1892 .pm = &sdhci_tegra_dev_pm_ops, 1893 }, 1894 .probe = sdhci_tegra_probe, 1895 .remove = sdhci_tegra_remove, 1896 }; 1897 1898 module_platform_driver(sdhci_tegra_driver); 1899 1900 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1901 MODULE_AUTHOR("Google, Inc."); 1902 MODULE_LICENSE("GPL v2"); 1903