1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/ktime.h> 34 35 #include "sdhci-pltfm.h" 36 #include "cqhci.h" 37 38 /* Tegra SDHOST controller vendor register definitions */ 39 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 40 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 41 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 42 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 43 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 44 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 45 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 46 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 47 48 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 49 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 50 51 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 52 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 53 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 54 55 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 56 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 57 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 58 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 59 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 60 61 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 62 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 63 64 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 65 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 66 67 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 68 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 69 70 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 71 #define SDHCI_AUTO_CAL_START BIT(31) 72 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 73 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 74 75 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 76 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 77 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 78 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 79 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 80 81 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 82 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 83 84 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 85 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 86 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 87 #define NVQUIRK_ENABLE_SDR50 BIT(3) 88 #define NVQUIRK_ENABLE_SDR104 BIT(4) 89 #define NVQUIRK_ENABLE_DDR50 BIT(5) 90 #define NVQUIRK_HAS_PADCALIB BIT(6) 91 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 92 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 93 94 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 95 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 96 97 struct sdhci_tegra_soc_data { 98 const struct sdhci_pltfm_data *pdata; 99 u32 nvquirks; 100 }; 101 102 /* Magic pull up and pull down pad calibration offsets */ 103 struct sdhci_tegra_autocal_offsets { 104 u32 pull_up_3v3; 105 u32 pull_down_3v3; 106 u32 pull_up_3v3_timeout; 107 u32 pull_down_3v3_timeout; 108 u32 pull_up_1v8; 109 u32 pull_down_1v8; 110 u32 pull_up_1v8_timeout; 111 u32 pull_down_1v8_timeout; 112 u32 pull_up_sdr104; 113 u32 pull_down_sdr104; 114 u32 pull_up_hs400; 115 u32 pull_down_hs400; 116 }; 117 118 struct sdhci_tegra { 119 const struct sdhci_tegra_soc_data *soc_data; 120 struct gpio_desc *power_gpio; 121 bool ddr_signaling; 122 bool pad_calib_required; 123 bool pad_control_available; 124 125 struct reset_control *rst; 126 struct pinctrl *pinctrl_sdmmc; 127 struct pinctrl_state *pinctrl_state_3v3; 128 struct pinctrl_state *pinctrl_state_1v8; 129 struct pinctrl_state *pinctrl_state_3v3_drv; 130 struct pinctrl_state *pinctrl_state_1v8_drv; 131 132 struct sdhci_tegra_autocal_offsets autocal_offsets; 133 ktime_t last_calib; 134 135 u32 default_tap; 136 u32 default_trim; 137 u32 dqs_trim; 138 bool enable_hwcq; 139 }; 140 141 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 142 { 143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 144 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 145 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 146 147 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 148 (reg == SDHCI_HOST_VERSION))) { 149 /* Erratum: Version register is invalid in HW. */ 150 return SDHCI_SPEC_200; 151 } 152 153 return readw(host->ioaddr + reg); 154 } 155 156 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 157 { 158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159 160 switch (reg) { 161 case SDHCI_TRANSFER_MODE: 162 /* 163 * Postpone this write, we must do it together with a 164 * command write that is down below. 165 */ 166 pltfm_host->xfer_mode_shadow = val; 167 return; 168 case SDHCI_COMMAND: 169 writel((val << 16) | pltfm_host->xfer_mode_shadow, 170 host->ioaddr + SDHCI_TRANSFER_MODE); 171 return; 172 } 173 174 writew(val, host->ioaddr + reg); 175 } 176 177 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 178 { 179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 180 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 181 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 182 183 /* Seems like we're getting spurious timeout and crc errors, so 184 * disable signalling of them. In case of real errors software 185 * timers should take care of eventually detecting them. 186 */ 187 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 188 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 189 190 writel(val, host->ioaddr + reg); 191 192 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 193 (reg == SDHCI_INT_ENABLE))) { 194 /* Erratum: Must enable block gap interrupt detection */ 195 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 196 if (val & SDHCI_INT_CARD_INT) 197 gap_ctrl |= 0x8; 198 else 199 gap_ctrl &= ~0x8; 200 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 201 } 202 } 203 204 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 205 { 206 bool status; 207 u32 reg; 208 209 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 210 status = !!(reg & SDHCI_CLOCK_CARD_EN); 211 212 if (status == enable) 213 return status; 214 215 if (enable) 216 reg |= SDHCI_CLOCK_CARD_EN; 217 else 218 reg &= ~SDHCI_CLOCK_CARD_EN; 219 220 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 221 222 return status; 223 } 224 225 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 226 { 227 bool is_tuning_cmd = 0; 228 bool clk_enabled; 229 u8 cmd; 230 231 if (reg == SDHCI_COMMAND) { 232 cmd = SDHCI_GET_CMD(val); 233 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 234 cmd == MMC_SEND_TUNING_BLOCK_HS200; 235 } 236 237 if (is_tuning_cmd) 238 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 239 240 writew(val, host->ioaddr + reg); 241 242 if (is_tuning_cmd) { 243 udelay(1); 244 tegra_sdhci_configure_card_clk(host, clk_enabled); 245 } 246 } 247 248 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 249 { 250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 251 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 252 int has_1v8, has_3v3; 253 254 /* 255 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 256 * voltage configuration in order to perform voltage switching. This 257 * means that valid pinctrl info is required on SDHCI instances capable 258 * of performing voltage switching. Whether or not an SDHCI instance is 259 * capable of voltage switching is determined based on the regulator. 260 */ 261 262 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 263 return true; 264 265 if (IS_ERR(host->mmc->supply.vqmmc)) 266 return false; 267 268 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 269 1700000, 1950000); 270 271 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 272 2700000, 3600000); 273 274 if (has_1v8 == 1 && has_3v3 == 1) 275 return tegra_host->pad_control_available; 276 277 /* Fixed voltage, no pad control required. */ 278 return true; 279 } 280 281 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 282 { 283 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 284 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 285 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 286 bool card_clk_enabled = false; 287 u32 reg; 288 289 /* 290 * Touching the tap values is a bit tricky on some SoC generations. 291 * The quirk enables a workaround for a glitch that sometimes occurs if 292 * the tap values are changed. 293 */ 294 295 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 296 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 297 298 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 299 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 300 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 301 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 302 303 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 304 card_clk_enabled) { 305 udelay(1); 306 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 307 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 308 } 309 } 310 311 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 312 struct mmc_ios *ios) 313 { 314 struct sdhci_host *host = mmc_priv(mmc); 315 u32 val; 316 317 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 318 319 if (ios->enhanced_strobe) 320 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 321 else 322 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 323 324 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 325 326 } 327 328 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 329 { 330 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 331 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 332 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 333 u32 misc_ctrl, clk_ctrl, pad_ctrl; 334 335 sdhci_reset(host, mask); 336 337 if (!(mask & SDHCI_RESET_ALL)) 338 return; 339 340 tegra_sdhci_set_tap(host, tegra_host->default_tap); 341 342 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 343 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 344 345 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 346 SDHCI_MISC_CTRL_ENABLE_SDR50 | 347 SDHCI_MISC_CTRL_ENABLE_DDR50 | 348 SDHCI_MISC_CTRL_ENABLE_SDR104); 349 350 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 351 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 352 353 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 354 /* Erratum: Enable SDHCI spec v3.00 support */ 355 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 356 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 357 /* Advertise UHS modes as supported by host */ 358 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 359 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 360 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 361 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 362 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 363 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 364 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 365 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 366 } 367 368 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 369 370 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 371 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 372 373 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 374 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 375 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 376 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 377 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 378 379 tegra_host->pad_calib_required = true; 380 } 381 382 tegra_host->ddr_signaling = false; 383 } 384 385 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 386 { 387 u32 val; 388 389 /* 390 * Enable or disable the additional I/O pad used by the drive strength 391 * calibration process. 392 */ 393 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 394 395 if (enable) 396 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 397 else 398 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 399 400 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 401 402 if (enable) 403 usleep_range(1, 2); 404 } 405 406 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 407 u16 pdpu) 408 { 409 u32 reg; 410 411 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 412 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 413 reg |= pdpu; 414 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 415 } 416 417 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 418 bool state_drvupdn) 419 { 420 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 421 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 422 struct sdhci_tegra_autocal_offsets *offsets = 423 &tegra_host->autocal_offsets; 424 struct pinctrl_state *pinctrl_drvupdn = NULL; 425 int ret = 0; 426 u8 drvup = 0, drvdn = 0; 427 u32 reg; 428 429 if (!state_drvupdn) { 430 /* PADS Drive Strength */ 431 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 432 if (tegra_host->pinctrl_state_1v8_drv) { 433 pinctrl_drvupdn = 434 tegra_host->pinctrl_state_1v8_drv; 435 } else { 436 drvup = offsets->pull_up_1v8_timeout; 437 drvdn = offsets->pull_down_1v8_timeout; 438 } 439 } else { 440 if (tegra_host->pinctrl_state_3v3_drv) { 441 pinctrl_drvupdn = 442 tegra_host->pinctrl_state_3v3_drv; 443 } else { 444 drvup = offsets->pull_up_3v3_timeout; 445 drvdn = offsets->pull_down_3v3_timeout; 446 } 447 } 448 449 if (pinctrl_drvupdn != NULL) { 450 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 451 pinctrl_drvupdn); 452 if (ret < 0) 453 dev_err(mmc_dev(host->mmc), 454 "failed pads drvupdn, ret: %d\n", ret); 455 } else if ((drvup) || (drvdn)) { 456 reg = sdhci_readl(host, 457 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 458 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 459 reg |= (drvup << 20) | (drvdn << 12); 460 sdhci_writel(host, reg, 461 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 462 } 463 464 } else { 465 /* Dual Voltage PADS Voltage selection */ 466 if (!tegra_host->pad_control_available) 467 return 0; 468 469 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 470 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 471 tegra_host->pinctrl_state_1v8); 472 if (ret < 0) 473 dev_err(mmc_dev(host->mmc), 474 "setting 1.8V failed, ret: %d\n", ret); 475 } else { 476 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 477 tegra_host->pinctrl_state_3v3); 478 if (ret < 0) 479 dev_err(mmc_dev(host->mmc), 480 "setting 3.3V failed, ret: %d\n", ret); 481 } 482 } 483 484 return ret; 485 } 486 487 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 488 { 489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 490 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 491 struct sdhci_tegra_autocal_offsets offsets = 492 tegra_host->autocal_offsets; 493 struct mmc_ios *ios = &host->mmc->ios; 494 bool card_clk_enabled; 495 u16 pdpu; 496 u32 reg; 497 int ret; 498 499 switch (ios->timing) { 500 case MMC_TIMING_UHS_SDR104: 501 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 502 break; 503 case MMC_TIMING_MMC_HS400: 504 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 505 break; 506 default: 507 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 508 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 509 else 510 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 511 } 512 513 /* Set initial offset before auto-calibration */ 514 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 515 516 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 517 518 tegra_sdhci_configure_cal_pad(host, true); 519 520 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 521 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 522 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 523 524 usleep_range(1, 2); 525 /* 10 ms timeout */ 526 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 527 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 528 1000, 10000); 529 530 tegra_sdhci_configure_cal_pad(host, false); 531 532 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 533 534 if (ret) { 535 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 536 537 /* Disable automatic cal and use fixed Drive Strengths */ 538 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 539 reg &= ~SDHCI_AUTO_CAL_ENABLE; 540 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 541 542 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 543 if (ret < 0) 544 dev_err(mmc_dev(host->mmc), 545 "Setting drive strengths failed: %d\n", ret); 546 } 547 } 548 549 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 550 { 551 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 552 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 553 struct sdhci_tegra_autocal_offsets *autocal = 554 &tegra_host->autocal_offsets; 555 int err; 556 557 err = device_property_read_u32(host->mmc->parent, 558 "nvidia,pad-autocal-pull-up-offset-3v3", 559 &autocal->pull_up_3v3); 560 if (err) 561 autocal->pull_up_3v3 = 0; 562 563 err = device_property_read_u32(host->mmc->parent, 564 "nvidia,pad-autocal-pull-down-offset-3v3", 565 &autocal->pull_down_3v3); 566 if (err) 567 autocal->pull_down_3v3 = 0; 568 569 err = device_property_read_u32(host->mmc->parent, 570 "nvidia,pad-autocal-pull-up-offset-1v8", 571 &autocal->pull_up_1v8); 572 if (err) 573 autocal->pull_up_1v8 = 0; 574 575 err = device_property_read_u32(host->mmc->parent, 576 "nvidia,pad-autocal-pull-down-offset-1v8", 577 &autocal->pull_down_1v8); 578 if (err) 579 autocal->pull_down_1v8 = 0; 580 581 err = device_property_read_u32(host->mmc->parent, 582 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 583 &autocal->pull_up_3v3_timeout); 584 if (err) { 585 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 586 (tegra_host->pinctrl_state_3v3_drv == NULL)) 587 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 588 mmc_hostname(host->mmc)); 589 autocal->pull_up_3v3_timeout = 0; 590 } 591 592 err = device_property_read_u32(host->mmc->parent, 593 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 594 &autocal->pull_down_3v3_timeout); 595 if (err) { 596 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 597 (tegra_host->pinctrl_state_3v3_drv == NULL)) 598 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 599 mmc_hostname(host->mmc)); 600 autocal->pull_down_3v3_timeout = 0; 601 } 602 603 err = device_property_read_u32(host->mmc->parent, 604 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 605 &autocal->pull_up_1v8_timeout); 606 if (err) { 607 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 608 (tegra_host->pinctrl_state_1v8_drv == NULL)) 609 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 610 mmc_hostname(host->mmc)); 611 autocal->pull_up_1v8_timeout = 0; 612 } 613 614 err = device_property_read_u32(host->mmc->parent, 615 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 616 &autocal->pull_down_1v8_timeout); 617 if (err) { 618 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 619 (tegra_host->pinctrl_state_1v8_drv == NULL)) 620 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 621 mmc_hostname(host->mmc)); 622 autocal->pull_down_1v8_timeout = 0; 623 } 624 625 err = device_property_read_u32(host->mmc->parent, 626 "nvidia,pad-autocal-pull-up-offset-sdr104", 627 &autocal->pull_up_sdr104); 628 if (err) 629 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 630 631 err = device_property_read_u32(host->mmc->parent, 632 "nvidia,pad-autocal-pull-down-offset-sdr104", 633 &autocal->pull_down_sdr104); 634 if (err) 635 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 636 637 err = device_property_read_u32(host->mmc->parent, 638 "nvidia,pad-autocal-pull-up-offset-hs400", 639 &autocal->pull_up_hs400); 640 if (err) 641 autocal->pull_up_hs400 = autocal->pull_up_1v8; 642 643 err = device_property_read_u32(host->mmc->parent, 644 "nvidia,pad-autocal-pull-down-offset-hs400", 645 &autocal->pull_down_hs400); 646 if (err) 647 autocal->pull_down_hs400 = autocal->pull_down_1v8; 648 } 649 650 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 651 { 652 struct sdhci_host *host = mmc_priv(mmc); 653 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 654 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 655 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 656 657 /* 100 ms calibration interval is specified in the TRM */ 658 if (ktime_to_ms(since_calib) > 100) { 659 tegra_sdhci_pad_autocalib(host); 660 tegra_host->last_calib = ktime_get(); 661 } 662 663 sdhci_request(mmc, mrq); 664 } 665 666 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 667 { 668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 669 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 670 int err; 671 672 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 673 &tegra_host->default_tap); 674 if (err) 675 tegra_host->default_tap = 0; 676 677 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 678 &tegra_host->default_trim); 679 if (err) 680 tegra_host->default_trim = 0; 681 682 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 683 &tegra_host->dqs_trim); 684 if (err) 685 tegra_host->dqs_trim = 0x11; 686 } 687 688 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 689 { 690 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 691 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 692 693 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) 694 tegra_host->enable_hwcq = true; 695 else 696 tegra_host->enable_hwcq = false; 697 698 tegra_sdhci_parse_pad_autocal_dt(host); 699 tegra_sdhci_parse_tap_and_trim(host); 700 } 701 702 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 703 { 704 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 705 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 706 unsigned long host_clk; 707 708 if (!clock) 709 return sdhci_set_clock(host, clock); 710 711 /* 712 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 713 * divider to be configured to divided the host clock by two. The SDHCI 714 * clock divider is calculated as part of sdhci_set_clock() by 715 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 716 * the requested clock rate. 717 * 718 * By setting the host->max_clk to clock * 2 the divider calculation 719 * will always result in the correct value for DDR50/52 modes, 720 * regardless of clock rate rounding, which may happen if the value 721 * from clk_get_rate() is used. 722 */ 723 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 724 clk_set_rate(pltfm_host->clk, host_clk); 725 if (tegra_host->ddr_signaling) 726 host->max_clk = host_clk; 727 else 728 host->max_clk = clk_get_rate(pltfm_host->clk); 729 730 sdhci_set_clock(host, clock); 731 732 if (tegra_host->pad_calib_required) { 733 tegra_sdhci_pad_autocalib(host); 734 tegra_host->pad_calib_required = false; 735 } 736 } 737 738 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 739 { 740 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 741 742 return clk_round_rate(pltfm_host->clk, UINT_MAX); 743 } 744 745 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 746 { 747 u32 val; 748 749 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 750 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 751 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 752 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 753 } 754 755 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 756 { 757 u32 reg; 758 int err; 759 760 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 761 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 762 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 763 764 /* 1 ms sleep, 5 ms timeout */ 765 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 766 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 767 1000, 5000); 768 if (err) 769 dev_err(mmc_dev(host->mmc), 770 "HS400 delay line calibration timed out\n"); 771 } 772 773 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 774 unsigned timing) 775 { 776 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 777 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 778 bool set_default_tap = false; 779 bool set_dqs_trim = false; 780 bool do_hs400_dll_cal = false; 781 782 switch (timing) { 783 case MMC_TIMING_UHS_SDR50: 784 case MMC_TIMING_UHS_SDR104: 785 case MMC_TIMING_MMC_HS200: 786 /* Don't set default tap on tunable modes. */ 787 break; 788 case MMC_TIMING_MMC_HS400: 789 set_dqs_trim = true; 790 do_hs400_dll_cal = true; 791 break; 792 case MMC_TIMING_MMC_DDR52: 793 case MMC_TIMING_UHS_DDR50: 794 tegra_host->ddr_signaling = true; 795 set_default_tap = true; 796 break; 797 default: 798 set_default_tap = true; 799 break; 800 } 801 802 sdhci_set_uhs_signaling(host, timing); 803 804 tegra_sdhci_pad_autocalib(host); 805 806 if (set_default_tap) 807 tegra_sdhci_set_tap(host, tegra_host->default_tap); 808 809 if (set_dqs_trim) 810 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 811 812 if (do_hs400_dll_cal) 813 tegra_sdhci_hs400_dll_cal(host); 814 } 815 816 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 817 { 818 unsigned int min, max; 819 820 /* 821 * Start search for minimum tap value at 10, as smaller values are 822 * may wrongly be reported as working but fail at higher speeds, 823 * according to the TRM. 824 */ 825 min = 10; 826 while (min < 255) { 827 tegra_sdhci_set_tap(host, min); 828 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 829 break; 830 min++; 831 } 832 833 /* Find the maximum tap value that still passes. */ 834 max = min + 1; 835 while (max < 255) { 836 tegra_sdhci_set_tap(host, max); 837 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 838 max--; 839 break; 840 } 841 max++; 842 } 843 844 /* The TRM states the ideal tap value is at 75% in the passing range. */ 845 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 846 847 return mmc_send_tuning(host->mmc, opcode, NULL); 848 } 849 850 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 851 struct mmc_ios *ios) 852 { 853 struct sdhci_host *host = mmc_priv(mmc); 854 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 855 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 856 int ret = 0; 857 858 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 859 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 860 if (ret < 0) 861 return ret; 862 ret = sdhci_start_signal_voltage_switch(mmc, ios); 863 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 864 ret = sdhci_start_signal_voltage_switch(mmc, ios); 865 if (ret < 0) 866 return ret; 867 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 868 } 869 870 if (tegra_host->pad_calib_required) 871 tegra_sdhci_pad_autocalib(host); 872 873 return ret; 874 } 875 876 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 877 struct sdhci_tegra *tegra_host) 878 { 879 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 880 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 881 dev_dbg(dev, "No pinctrl info, err: %ld\n", 882 PTR_ERR(tegra_host->pinctrl_sdmmc)); 883 return -1; 884 } 885 886 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 887 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 888 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 889 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 890 tegra_host->pinctrl_state_1v8_drv = NULL; 891 } 892 893 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 894 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 895 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 896 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 897 tegra_host->pinctrl_state_3v3_drv = NULL; 898 } 899 900 tegra_host->pinctrl_state_3v3 = 901 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 902 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 903 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 904 PTR_ERR(tegra_host->pinctrl_state_3v3)); 905 return -1; 906 } 907 908 tegra_host->pinctrl_state_1v8 = 909 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 910 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 911 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 912 PTR_ERR(tegra_host->pinctrl_state_1v8)); 913 return -1; 914 } 915 916 tegra_host->pad_control_available = true; 917 918 return 0; 919 } 920 921 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 922 { 923 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 924 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 925 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 926 927 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 928 tegra_host->pad_calib_required = true; 929 } 930 931 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 932 { 933 struct cqhci_host *cq_host = mmc->cqe_private; 934 u32 cqcfg = 0; 935 936 /* 937 * Tegra SDMMC Controller design prevents write access to BLOCK_COUNT 938 * registers when CQE is enabled. 939 */ 940 cqcfg = cqhci_readl(cq_host, CQHCI_CFG); 941 if (cqcfg & CQHCI_ENABLE) 942 cqhci_writel(cq_host, (cqcfg & ~CQHCI_ENABLE), CQHCI_CFG); 943 944 sdhci_cqe_enable(mmc); 945 946 if (cqcfg & CQHCI_ENABLE) 947 cqhci_writel(cq_host, cqcfg, CQHCI_CFG); 948 } 949 950 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 951 { 952 sdhci_dumpregs(mmc_priv(mmc)); 953 } 954 955 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 956 { 957 int cmd_error = 0; 958 int data_error = 0; 959 960 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 961 return intmask; 962 963 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 964 965 return 0; 966 } 967 968 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 969 .enable = sdhci_tegra_cqe_enable, 970 .disable = sdhci_cqe_disable, 971 .dumpregs = sdhci_tegra_dumpregs, 972 }; 973 974 static const struct sdhci_ops tegra_sdhci_ops = { 975 .read_w = tegra_sdhci_readw, 976 .write_l = tegra_sdhci_writel, 977 .set_clock = tegra_sdhci_set_clock, 978 .set_bus_width = sdhci_set_bus_width, 979 .reset = tegra_sdhci_reset, 980 .platform_execute_tuning = tegra_sdhci_execute_tuning, 981 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 982 .voltage_switch = tegra_sdhci_voltage_switch, 983 .get_max_clock = tegra_sdhci_get_max_clock, 984 }; 985 986 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 987 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 988 SDHCI_QUIRK_SINGLE_POWER_WRITE | 989 SDHCI_QUIRK_NO_HISPD_BIT | 990 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 991 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 992 .ops = &tegra_sdhci_ops, 993 }; 994 995 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 996 .pdata = &sdhci_tegra20_pdata, 997 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 998 NVQUIRK_ENABLE_BLOCK_GAP_DET, 999 }; 1000 1001 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1002 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1003 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1004 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1005 SDHCI_QUIRK_NO_HISPD_BIT | 1006 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1007 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1008 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1009 SDHCI_QUIRK2_BROKEN_HS200 | 1010 /* 1011 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1012 * though no command operation was in progress." 1013 * 1014 * The exact reason is unknown, as the same hardware seems 1015 * to support Auto CMD23 on a downstream 3.1 kernel. 1016 */ 1017 SDHCI_QUIRK2_ACMD23_BROKEN, 1018 .ops = &tegra_sdhci_ops, 1019 }; 1020 1021 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1022 .pdata = &sdhci_tegra30_pdata, 1023 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1024 NVQUIRK_ENABLE_SDR50 | 1025 NVQUIRK_ENABLE_SDR104 | 1026 NVQUIRK_HAS_PADCALIB, 1027 }; 1028 1029 static const struct sdhci_ops tegra114_sdhci_ops = { 1030 .read_w = tegra_sdhci_readw, 1031 .write_w = tegra_sdhci_writew, 1032 .write_l = tegra_sdhci_writel, 1033 .set_clock = tegra_sdhci_set_clock, 1034 .set_bus_width = sdhci_set_bus_width, 1035 .reset = tegra_sdhci_reset, 1036 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1037 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1038 .voltage_switch = tegra_sdhci_voltage_switch, 1039 .get_max_clock = tegra_sdhci_get_max_clock, 1040 }; 1041 1042 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1043 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1044 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1045 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1046 SDHCI_QUIRK_NO_HISPD_BIT | 1047 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1048 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1049 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1050 .ops = &tegra114_sdhci_ops, 1051 }; 1052 1053 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1054 .pdata = &sdhci_tegra114_pdata, 1055 }; 1056 1057 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1058 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1059 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1060 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1061 SDHCI_QUIRK_NO_HISPD_BIT | 1062 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1063 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1064 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1065 /* 1066 * The TRM states that the SD/MMC controller found on 1067 * Tegra124 can address 34 bits (the maximum supported by 1068 * the Tegra memory controller), but tests show that DMA 1069 * to or from above 4 GiB doesn't work. This is possibly 1070 * caused by missing programming, though it's not obvious 1071 * what sequence is required. Mark 64-bit DMA broken for 1072 * now to fix this for existing users (e.g. Nyan boards). 1073 */ 1074 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1075 .ops = &tegra114_sdhci_ops, 1076 }; 1077 1078 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1079 .pdata = &sdhci_tegra124_pdata, 1080 }; 1081 1082 static const struct sdhci_ops tegra210_sdhci_ops = { 1083 .read_w = tegra_sdhci_readw, 1084 .write_w = tegra210_sdhci_writew, 1085 .write_l = tegra_sdhci_writel, 1086 .set_clock = tegra_sdhci_set_clock, 1087 .set_bus_width = sdhci_set_bus_width, 1088 .reset = tegra_sdhci_reset, 1089 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1090 .voltage_switch = tegra_sdhci_voltage_switch, 1091 .get_max_clock = tegra_sdhci_get_max_clock, 1092 }; 1093 1094 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1095 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1096 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1097 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1098 SDHCI_QUIRK_NO_HISPD_BIT | 1099 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1100 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1101 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1102 .ops = &tegra210_sdhci_ops, 1103 }; 1104 1105 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1106 .pdata = &sdhci_tegra210_pdata, 1107 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1108 NVQUIRK_HAS_PADCALIB | 1109 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1110 NVQUIRK_ENABLE_SDR50 | 1111 NVQUIRK_ENABLE_SDR104, 1112 }; 1113 1114 static const struct sdhci_ops tegra186_sdhci_ops = { 1115 .read_w = tegra_sdhci_readw, 1116 .write_l = tegra_sdhci_writel, 1117 .set_clock = tegra_sdhci_set_clock, 1118 .set_bus_width = sdhci_set_bus_width, 1119 .reset = tegra_sdhci_reset, 1120 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1121 .voltage_switch = tegra_sdhci_voltage_switch, 1122 .get_max_clock = tegra_sdhci_get_max_clock, 1123 .irq = sdhci_tegra_cqhci_irq, 1124 }; 1125 1126 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1127 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1128 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1129 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1130 SDHCI_QUIRK_NO_HISPD_BIT | 1131 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1132 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1133 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1134 /* SDHCI controllers on Tegra186 support 40-bit addressing. 1135 * IOVA addresses are 48-bit wide on Tegra186. 1136 * With 64-bit dma mask used for SDHCI, accesses can 1137 * be broken. Disable 64-bit dma, which would fall back 1138 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 1139 * But it is not supported as of now. 1140 */ 1141 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1142 .ops = &tegra186_sdhci_ops, 1143 }; 1144 1145 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1146 .pdata = &sdhci_tegra186_pdata, 1147 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1148 NVQUIRK_HAS_PADCALIB | 1149 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1150 NVQUIRK_ENABLE_SDR50 | 1151 NVQUIRK_ENABLE_SDR104, 1152 }; 1153 1154 static const struct of_device_id sdhci_tegra_dt_match[] = { 1155 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1156 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1157 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1158 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1159 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1160 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1161 {} 1162 }; 1163 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1164 1165 static int sdhci_tegra_add_host(struct sdhci_host *host) 1166 { 1167 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1168 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1169 struct cqhci_host *cq_host; 1170 bool dma64; 1171 int ret; 1172 1173 if (!tegra_host->enable_hwcq) 1174 return sdhci_add_host(host); 1175 1176 sdhci_enable_v4_mode(host); 1177 1178 ret = sdhci_setup_host(host); 1179 if (ret) 1180 return ret; 1181 1182 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1183 1184 cq_host = devm_kzalloc(host->mmc->parent, 1185 sizeof(*cq_host), GFP_KERNEL); 1186 if (!cq_host) { 1187 ret = -ENOMEM; 1188 goto cleanup; 1189 } 1190 1191 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1192 cq_host->ops = &sdhci_tegra_cqhci_ops; 1193 1194 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1195 if (dma64) 1196 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1197 1198 ret = cqhci_init(cq_host, host->mmc, dma64); 1199 if (ret) 1200 goto cleanup; 1201 1202 ret = __sdhci_add_host(host); 1203 if (ret) 1204 goto cleanup; 1205 1206 return 0; 1207 1208 cleanup: 1209 sdhci_cleanup_host(host); 1210 return ret; 1211 } 1212 1213 static int sdhci_tegra_probe(struct platform_device *pdev) 1214 { 1215 const struct of_device_id *match; 1216 const struct sdhci_tegra_soc_data *soc_data; 1217 struct sdhci_host *host; 1218 struct sdhci_pltfm_host *pltfm_host; 1219 struct sdhci_tegra *tegra_host; 1220 struct clk *clk; 1221 int rc; 1222 1223 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1224 if (!match) 1225 return -EINVAL; 1226 soc_data = match->data; 1227 1228 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1229 if (IS_ERR(host)) 1230 return PTR_ERR(host); 1231 pltfm_host = sdhci_priv(host); 1232 1233 tegra_host = sdhci_pltfm_priv(pltfm_host); 1234 tegra_host->ddr_signaling = false; 1235 tegra_host->pad_calib_required = false; 1236 tegra_host->pad_control_available = false; 1237 tegra_host->soc_data = soc_data; 1238 1239 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1240 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1241 if (rc == 0) 1242 host->mmc_host_ops.start_signal_voltage_switch = 1243 sdhci_tegra_start_signal_voltage_switch; 1244 } 1245 1246 /* Hook to periodically rerun pad calibration */ 1247 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1248 host->mmc_host_ops.request = tegra_sdhci_request; 1249 1250 host->mmc_host_ops.hs400_enhanced_strobe = 1251 tegra_sdhci_hs400_enhanced_strobe; 1252 1253 rc = mmc_of_parse(host->mmc); 1254 if (rc) 1255 goto err_parse_dt; 1256 1257 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1258 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1259 1260 tegra_sdhci_parse_dt(host); 1261 1262 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1263 GPIOD_OUT_HIGH); 1264 if (IS_ERR(tegra_host->power_gpio)) { 1265 rc = PTR_ERR(tegra_host->power_gpio); 1266 goto err_power_req; 1267 } 1268 1269 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1270 if (IS_ERR(clk)) { 1271 dev_err(mmc_dev(host->mmc), "clk err\n"); 1272 rc = PTR_ERR(clk); 1273 goto err_clk_get; 1274 } 1275 clk_prepare_enable(clk); 1276 pltfm_host->clk = clk; 1277 1278 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1279 "sdhci"); 1280 if (IS_ERR(tegra_host->rst)) { 1281 rc = PTR_ERR(tegra_host->rst); 1282 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1283 goto err_rst_get; 1284 } 1285 1286 rc = reset_control_assert(tegra_host->rst); 1287 if (rc) 1288 goto err_rst_get; 1289 1290 usleep_range(2000, 4000); 1291 1292 rc = reset_control_deassert(tegra_host->rst); 1293 if (rc) 1294 goto err_rst_get; 1295 1296 usleep_range(2000, 4000); 1297 1298 rc = sdhci_tegra_add_host(host); 1299 if (rc) 1300 goto err_add_host; 1301 1302 return 0; 1303 1304 err_add_host: 1305 reset_control_assert(tegra_host->rst); 1306 err_rst_get: 1307 clk_disable_unprepare(pltfm_host->clk); 1308 err_clk_get: 1309 err_power_req: 1310 err_parse_dt: 1311 sdhci_pltfm_free(pdev); 1312 return rc; 1313 } 1314 1315 static int sdhci_tegra_remove(struct platform_device *pdev) 1316 { 1317 struct sdhci_host *host = platform_get_drvdata(pdev); 1318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1319 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1320 1321 sdhci_remove_host(host, 0); 1322 1323 reset_control_assert(tegra_host->rst); 1324 usleep_range(2000, 4000); 1325 clk_disable_unprepare(pltfm_host->clk); 1326 1327 sdhci_pltfm_free(pdev); 1328 1329 return 0; 1330 } 1331 1332 static struct platform_driver sdhci_tegra_driver = { 1333 .driver = { 1334 .name = "sdhci-tegra", 1335 .of_match_table = sdhci_tegra_dt_match, 1336 .pm = &sdhci_pltfm_pmops, 1337 }, 1338 .probe = sdhci_tegra_probe, 1339 .remove = sdhci_tegra_remove, 1340 }; 1341 1342 module_platform_driver(sdhci_tegra_driver); 1343 1344 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1345 MODULE_AUTHOR("Google, Inc."); 1346 MODULE_LICENSE("GPL v2"); 1347