1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/module.h> 28 29 #include <asm/gpio.h> 30 31 #include <mach/gpio-tegra.h> 32 #include <mach/sdhci.h> 33 34 #include "sdhci-pltfm.h" 35 36 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 37 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 38 39 struct sdhci_tegra_soc_data { 40 struct sdhci_pltfm_data *pdata; 41 u32 nvquirks; 42 }; 43 44 struct sdhci_tegra { 45 const struct tegra_sdhci_platform_data *plat; 46 const struct sdhci_tegra_soc_data *soc_data; 47 }; 48 49 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg) 50 { 51 u32 val; 52 53 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 54 /* Use wp_gpio here instead? */ 55 val = readl(host->ioaddr + reg); 56 return val | SDHCI_WRITE_PROTECT; 57 } 58 59 return readl(host->ioaddr + reg); 60 } 61 62 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 63 { 64 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 65 struct sdhci_tegra *tegra_host = pltfm_host->priv; 66 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 67 68 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 69 (reg == SDHCI_HOST_VERSION))) { 70 /* Erratum: Version register is invalid in HW. */ 71 return SDHCI_SPEC_200; 72 } 73 74 return readw(host->ioaddr + reg); 75 } 76 77 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 78 { 79 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 80 struct sdhci_tegra *tegra_host = pltfm_host->priv; 81 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 82 83 /* Seems like we're getting spurious timeout and crc errors, so 84 * disable signalling of them. In case of real errors software 85 * timers should take care of eventually detecting them. 86 */ 87 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 88 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 89 90 writel(val, host->ioaddr + reg); 91 92 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 93 (reg == SDHCI_INT_ENABLE))) { 94 /* Erratum: Must enable block gap interrupt detection */ 95 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 96 if (val & SDHCI_INT_CARD_INT) 97 gap_ctrl |= 0x8; 98 else 99 gap_ctrl &= ~0x8; 100 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 101 } 102 } 103 104 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 105 { 106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 107 struct sdhci_tegra *tegra_host = pltfm_host->priv; 108 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 109 110 if (!gpio_is_valid(plat->wp_gpio)) 111 return -1; 112 113 return gpio_get_value(plat->wp_gpio); 114 } 115 116 static irqreturn_t carddetect_irq(int irq, void *data) 117 { 118 struct sdhci_host *sdhost = (struct sdhci_host *)data; 119 120 tasklet_schedule(&sdhost->card_tasklet); 121 return IRQ_HANDLED; 122 }; 123 124 static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width) 125 { 126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 127 struct sdhci_tegra *tegra_host = pltfm_host->priv; 128 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 129 u32 ctrl; 130 131 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 132 if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) { 133 ctrl &= ~SDHCI_CTRL_4BITBUS; 134 ctrl |= SDHCI_CTRL_8BITBUS; 135 } else { 136 ctrl &= ~SDHCI_CTRL_8BITBUS; 137 if (bus_width == MMC_BUS_WIDTH_4) 138 ctrl |= SDHCI_CTRL_4BITBUS; 139 else 140 ctrl &= ~SDHCI_CTRL_4BITBUS; 141 } 142 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 143 return 0; 144 } 145 146 static struct sdhci_ops tegra_sdhci_ops = { 147 .get_ro = tegra_sdhci_get_ro, 148 .read_l = tegra_sdhci_readl, 149 .read_w = tegra_sdhci_readw, 150 .write_l = tegra_sdhci_writel, 151 .platform_8bit_width = tegra_sdhci_8bit, 152 }; 153 154 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 155 static struct sdhci_pltfm_data sdhci_tegra20_pdata = { 156 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 157 SDHCI_QUIRK_SINGLE_POWER_WRITE | 158 SDHCI_QUIRK_NO_HISPD_BIT | 159 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 160 .ops = &tegra_sdhci_ops, 161 }; 162 163 static struct sdhci_tegra_soc_data soc_data_tegra20 = { 164 .pdata = &sdhci_tegra20_pdata, 165 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 166 NVQUIRK_ENABLE_BLOCK_GAP_DET, 167 }; 168 #endif 169 170 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 171 static struct sdhci_pltfm_data sdhci_tegra30_pdata = { 172 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 173 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 174 SDHCI_QUIRK_SINGLE_POWER_WRITE | 175 SDHCI_QUIRK_NO_HISPD_BIT | 176 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 177 .ops = &tegra_sdhci_ops, 178 }; 179 180 static struct sdhci_tegra_soc_data soc_data_tegra30 = { 181 .pdata = &sdhci_tegra30_pdata, 182 }; 183 #endif 184 185 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = { 186 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 187 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 188 #endif 189 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 190 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 191 #endif 192 {} 193 }; 194 MODULE_DEVICE_TABLE(of, sdhci_dt_ids); 195 196 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata( 197 struct platform_device *pdev) 198 { 199 struct tegra_sdhci_platform_data *plat; 200 struct device_node *np = pdev->dev.of_node; 201 202 if (!np) 203 return NULL; 204 205 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 206 if (!plat) { 207 dev_err(&pdev->dev, "Can't allocate platform data\n"); 208 return NULL; 209 } 210 211 plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 212 plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 213 plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0); 214 if (of_find_property(np, "support-8bit", NULL)) 215 plat->is_8bit = 1; 216 217 return plat; 218 } 219 220 static int __devinit sdhci_tegra_probe(struct platform_device *pdev) 221 { 222 const struct of_device_id *match; 223 const struct sdhci_tegra_soc_data *soc_data; 224 struct sdhci_host *host; 225 struct sdhci_pltfm_host *pltfm_host; 226 struct tegra_sdhci_platform_data *plat; 227 struct sdhci_tegra *tegra_host; 228 struct clk *clk; 229 int rc; 230 231 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 232 if (match) 233 soc_data = match->data; 234 else 235 soc_data = &soc_data_tegra20; 236 237 host = sdhci_pltfm_init(pdev, soc_data->pdata); 238 if (IS_ERR(host)) 239 return PTR_ERR(host); 240 241 pltfm_host = sdhci_priv(host); 242 243 plat = pdev->dev.platform_data; 244 245 if (plat == NULL) 246 plat = sdhci_tegra_dt_parse_pdata(pdev); 247 248 if (plat == NULL) { 249 dev_err(mmc_dev(host->mmc), "missing platform data\n"); 250 rc = -ENXIO; 251 goto err_no_plat; 252 } 253 254 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 255 if (!tegra_host) { 256 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 257 rc = -ENOMEM; 258 goto err_no_plat; 259 } 260 261 tegra_host->plat = plat; 262 tegra_host->soc_data = soc_data; 263 264 pltfm_host->priv = tegra_host; 265 266 if (gpio_is_valid(plat->power_gpio)) { 267 rc = gpio_request(plat->power_gpio, "sdhci_power"); 268 if (rc) { 269 dev_err(mmc_dev(host->mmc), 270 "failed to allocate power gpio\n"); 271 goto err_power_req; 272 } 273 tegra_gpio_enable(plat->power_gpio); 274 gpio_direction_output(plat->power_gpio, 1); 275 } 276 277 if (gpio_is_valid(plat->cd_gpio)) { 278 rc = gpio_request(plat->cd_gpio, "sdhci_cd"); 279 if (rc) { 280 dev_err(mmc_dev(host->mmc), 281 "failed to allocate cd gpio\n"); 282 goto err_cd_req; 283 } 284 tegra_gpio_enable(plat->cd_gpio); 285 gpio_direction_input(plat->cd_gpio); 286 287 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, 288 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 289 mmc_hostname(host->mmc), host); 290 291 if (rc) { 292 dev_err(mmc_dev(host->mmc), "request irq error\n"); 293 goto err_cd_irq_req; 294 } 295 296 } 297 298 if (gpio_is_valid(plat->wp_gpio)) { 299 rc = gpio_request(plat->wp_gpio, "sdhci_wp"); 300 if (rc) { 301 dev_err(mmc_dev(host->mmc), 302 "failed to allocate wp gpio\n"); 303 goto err_wp_req; 304 } 305 tegra_gpio_enable(plat->wp_gpio); 306 gpio_direction_input(plat->wp_gpio); 307 } 308 309 clk = clk_get(mmc_dev(host->mmc), NULL); 310 if (IS_ERR(clk)) { 311 dev_err(mmc_dev(host->mmc), "clk err\n"); 312 rc = PTR_ERR(clk); 313 goto err_clk_get; 314 } 315 clk_enable(clk); 316 pltfm_host->clk = clk; 317 318 host->mmc->pm_caps = plat->pm_flags; 319 320 if (plat->is_8bit) 321 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 322 323 rc = sdhci_add_host(host); 324 if (rc) 325 goto err_add_host; 326 327 return 0; 328 329 err_add_host: 330 clk_disable(pltfm_host->clk); 331 clk_put(pltfm_host->clk); 332 err_clk_get: 333 if (gpio_is_valid(plat->wp_gpio)) { 334 tegra_gpio_disable(plat->wp_gpio); 335 gpio_free(plat->wp_gpio); 336 } 337 err_wp_req: 338 if (gpio_is_valid(plat->cd_gpio)) 339 free_irq(gpio_to_irq(plat->cd_gpio), host); 340 err_cd_irq_req: 341 if (gpio_is_valid(plat->cd_gpio)) { 342 tegra_gpio_disable(plat->cd_gpio); 343 gpio_free(plat->cd_gpio); 344 } 345 err_cd_req: 346 if (gpio_is_valid(plat->power_gpio)) { 347 tegra_gpio_disable(plat->power_gpio); 348 gpio_free(plat->power_gpio); 349 } 350 err_power_req: 351 err_no_plat: 352 sdhci_pltfm_free(pdev); 353 return rc; 354 } 355 356 static int __devexit sdhci_tegra_remove(struct platform_device *pdev) 357 { 358 struct sdhci_host *host = platform_get_drvdata(pdev); 359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 360 struct sdhci_tegra *tegra_host = pltfm_host->priv; 361 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 362 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 363 364 sdhci_remove_host(host, dead); 365 366 if (gpio_is_valid(plat->wp_gpio)) { 367 tegra_gpio_disable(plat->wp_gpio); 368 gpio_free(plat->wp_gpio); 369 } 370 371 if (gpio_is_valid(plat->cd_gpio)) { 372 free_irq(gpio_to_irq(plat->cd_gpio), host); 373 tegra_gpio_disable(plat->cd_gpio); 374 gpio_free(plat->cd_gpio); 375 } 376 377 if (gpio_is_valid(plat->power_gpio)) { 378 tegra_gpio_disable(plat->power_gpio); 379 gpio_free(plat->power_gpio); 380 } 381 382 clk_disable(pltfm_host->clk); 383 clk_put(pltfm_host->clk); 384 385 sdhci_pltfm_free(pdev); 386 387 return 0; 388 } 389 390 static struct platform_driver sdhci_tegra_driver = { 391 .driver = { 392 .name = "sdhci-tegra", 393 .owner = THIS_MODULE, 394 .of_match_table = sdhci_tegra_dt_match, 395 .pm = SDHCI_PLTFM_PMOPS, 396 }, 397 .probe = sdhci_tegra_probe, 398 .remove = __devexit_p(sdhci_tegra_remove), 399 }; 400 401 module_platform_driver(sdhci_tegra_driver); 402 403 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 404 MODULE_AUTHOR("Google, Inc."); 405 MODULE_LICENSE("GPL v2"); 406