1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/ktime.h> 34 35 #include "sdhci-pltfm.h" 36 #include "cqhci.h" 37 38 /* Tegra SDHOST controller vendor register definitions */ 39 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 40 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 41 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 42 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 43 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 44 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 45 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 46 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 47 48 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 49 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 50 51 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 52 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 53 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 54 55 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 56 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 57 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 58 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 59 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 60 61 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 62 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 63 64 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 65 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 66 67 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 68 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 69 70 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 71 #define SDHCI_AUTO_CAL_START BIT(31) 72 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 73 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 74 75 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 76 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 77 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 78 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 79 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 80 81 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 82 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 83 84 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 85 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 86 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 87 #define NVQUIRK_ENABLE_SDR50 BIT(3) 88 #define NVQUIRK_ENABLE_SDR104 BIT(4) 89 #define NVQUIRK_ENABLE_DDR50 BIT(5) 90 #define NVQUIRK_HAS_PADCALIB BIT(6) 91 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 92 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 93 94 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 95 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 96 97 struct sdhci_tegra_soc_data { 98 const struct sdhci_pltfm_data *pdata; 99 u32 nvquirks; 100 }; 101 102 /* Magic pull up and pull down pad calibration offsets */ 103 struct sdhci_tegra_autocal_offsets { 104 u32 pull_up_3v3; 105 u32 pull_down_3v3; 106 u32 pull_up_3v3_timeout; 107 u32 pull_down_3v3_timeout; 108 u32 pull_up_1v8; 109 u32 pull_down_1v8; 110 u32 pull_up_1v8_timeout; 111 u32 pull_down_1v8_timeout; 112 u32 pull_up_sdr104; 113 u32 pull_down_sdr104; 114 u32 pull_up_hs400; 115 u32 pull_down_hs400; 116 }; 117 118 struct sdhci_tegra { 119 const struct sdhci_tegra_soc_data *soc_data; 120 struct gpio_desc *power_gpio; 121 bool ddr_signaling; 122 bool pad_calib_required; 123 bool pad_control_available; 124 125 struct reset_control *rst; 126 struct pinctrl *pinctrl_sdmmc; 127 struct pinctrl_state *pinctrl_state_3v3; 128 struct pinctrl_state *pinctrl_state_1v8; 129 struct pinctrl_state *pinctrl_state_3v3_drv; 130 struct pinctrl_state *pinctrl_state_1v8_drv; 131 132 struct sdhci_tegra_autocal_offsets autocal_offsets; 133 ktime_t last_calib; 134 135 u32 default_tap; 136 u32 default_trim; 137 u32 dqs_trim; 138 bool enable_hwcq; 139 }; 140 141 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 142 { 143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 144 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 145 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 146 147 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 148 (reg == SDHCI_HOST_VERSION))) { 149 /* Erratum: Version register is invalid in HW. */ 150 return SDHCI_SPEC_200; 151 } 152 153 return readw(host->ioaddr + reg); 154 } 155 156 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 157 { 158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159 160 switch (reg) { 161 case SDHCI_TRANSFER_MODE: 162 /* 163 * Postpone this write, we must do it together with a 164 * command write that is down below. 165 */ 166 pltfm_host->xfer_mode_shadow = val; 167 return; 168 case SDHCI_COMMAND: 169 writel((val << 16) | pltfm_host->xfer_mode_shadow, 170 host->ioaddr + SDHCI_TRANSFER_MODE); 171 return; 172 } 173 174 writew(val, host->ioaddr + reg); 175 } 176 177 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 178 { 179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 180 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 181 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 182 183 /* Seems like we're getting spurious timeout and crc errors, so 184 * disable signalling of them. In case of real errors software 185 * timers should take care of eventually detecting them. 186 */ 187 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 188 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 189 190 writel(val, host->ioaddr + reg); 191 192 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 193 (reg == SDHCI_INT_ENABLE))) { 194 /* Erratum: Must enable block gap interrupt detection */ 195 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 196 if (val & SDHCI_INT_CARD_INT) 197 gap_ctrl |= 0x8; 198 else 199 gap_ctrl &= ~0x8; 200 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 201 } 202 } 203 204 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 205 { 206 bool status; 207 u32 reg; 208 209 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 210 status = !!(reg & SDHCI_CLOCK_CARD_EN); 211 212 if (status == enable) 213 return status; 214 215 if (enable) 216 reg |= SDHCI_CLOCK_CARD_EN; 217 else 218 reg &= ~SDHCI_CLOCK_CARD_EN; 219 220 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 221 222 return status; 223 } 224 225 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 226 { 227 bool is_tuning_cmd = 0; 228 bool clk_enabled; 229 u8 cmd; 230 231 if (reg == SDHCI_COMMAND) { 232 cmd = SDHCI_GET_CMD(val); 233 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 234 cmd == MMC_SEND_TUNING_BLOCK_HS200; 235 } 236 237 if (is_tuning_cmd) 238 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 239 240 writew(val, host->ioaddr + reg); 241 242 if (is_tuning_cmd) { 243 udelay(1); 244 tegra_sdhci_configure_card_clk(host, clk_enabled); 245 } 246 } 247 248 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 249 { 250 return mmc_gpio_get_ro(host->mmc); 251 } 252 253 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 254 { 255 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 256 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 257 int has_1v8, has_3v3; 258 259 /* 260 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 261 * voltage configuration in order to perform voltage switching. This 262 * means that valid pinctrl info is required on SDHCI instances capable 263 * of performing voltage switching. Whether or not an SDHCI instance is 264 * capable of voltage switching is determined based on the regulator. 265 */ 266 267 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 268 return true; 269 270 if (IS_ERR(host->mmc->supply.vqmmc)) 271 return false; 272 273 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 274 1700000, 1950000); 275 276 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 277 2700000, 3600000); 278 279 if (has_1v8 == 1 && has_3v3 == 1) 280 return tegra_host->pad_control_available; 281 282 /* Fixed voltage, no pad control required. */ 283 return true; 284 } 285 286 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 287 { 288 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 289 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 290 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 291 bool card_clk_enabled = false; 292 u32 reg; 293 294 /* 295 * Touching the tap values is a bit tricky on some SoC generations. 296 * The quirk enables a workaround for a glitch that sometimes occurs if 297 * the tap values are changed. 298 */ 299 300 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 301 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 302 303 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 304 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 305 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 306 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 307 308 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 309 card_clk_enabled) { 310 udelay(1); 311 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 312 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 313 } 314 } 315 316 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 317 struct mmc_ios *ios) 318 { 319 struct sdhci_host *host = mmc_priv(mmc); 320 u32 val; 321 322 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 323 324 if (ios->enhanced_strobe) 325 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 326 else 327 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 328 329 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 330 331 } 332 333 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 334 { 335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 336 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 337 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 338 u32 misc_ctrl, clk_ctrl, pad_ctrl; 339 340 sdhci_reset(host, mask); 341 342 if (!(mask & SDHCI_RESET_ALL)) 343 return; 344 345 tegra_sdhci_set_tap(host, tegra_host->default_tap); 346 347 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 348 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 349 350 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 351 SDHCI_MISC_CTRL_ENABLE_SDR50 | 352 SDHCI_MISC_CTRL_ENABLE_DDR50 | 353 SDHCI_MISC_CTRL_ENABLE_SDR104); 354 355 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 356 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 357 358 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 359 /* Erratum: Enable SDHCI spec v3.00 support */ 360 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 361 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 362 /* Advertise UHS modes as supported by host */ 363 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 364 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 365 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 366 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 367 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 368 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 369 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 370 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 371 } 372 373 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 374 375 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 376 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 377 378 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 379 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 380 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 381 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 382 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 383 384 tegra_host->pad_calib_required = true; 385 } 386 387 tegra_host->ddr_signaling = false; 388 } 389 390 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 391 { 392 u32 val; 393 394 /* 395 * Enable or disable the additional I/O pad used by the drive strength 396 * calibration process. 397 */ 398 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 399 400 if (enable) 401 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 402 else 403 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 404 405 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 406 407 if (enable) 408 usleep_range(1, 2); 409 } 410 411 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 412 u16 pdpu) 413 { 414 u32 reg; 415 416 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 417 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 418 reg |= pdpu; 419 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 420 } 421 422 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 423 bool state_drvupdn) 424 { 425 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 426 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 427 struct sdhci_tegra_autocal_offsets *offsets = 428 &tegra_host->autocal_offsets; 429 struct pinctrl_state *pinctrl_drvupdn = NULL; 430 int ret = 0; 431 u8 drvup = 0, drvdn = 0; 432 u32 reg; 433 434 if (!state_drvupdn) { 435 /* PADS Drive Strength */ 436 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 437 if (tegra_host->pinctrl_state_1v8_drv) { 438 pinctrl_drvupdn = 439 tegra_host->pinctrl_state_1v8_drv; 440 } else { 441 drvup = offsets->pull_up_1v8_timeout; 442 drvdn = offsets->pull_down_1v8_timeout; 443 } 444 } else { 445 if (tegra_host->pinctrl_state_3v3_drv) { 446 pinctrl_drvupdn = 447 tegra_host->pinctrl_state_3v3_drv; 448 } else { 449 drvup = offsets->pull_up_3v3_timeout; 450 drvdn = offsets->pull_down_3v3_timeout; 451 } 452 } 453 454 if (pinctrl_drvupdn != NULL) { 455 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 456 pinctrl_drvupdn); 457 if (ret < 0) 458 dev_err(mmc_dev(host->mmc), 459 "failed pads drvupdn, ret: %d\n", ret); 460 } else if ((drvup) || (drvdn)) { 461 reg = sdhci_readl(host, 462 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 463 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 464 reg |= (drvup << 20) | (drvdn << 12); 465 sdhci_writel(host, reg, 466 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 467 } 468 469 } else { 470 /* Dual Voltage PADS Voltage selection */ 471 if (!tegra_host->pad_control_available) 472 return 0; 473 474 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 475 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 476 tegra_host->pinctrl_state_1v8); 477 if (ret < 0) 478 dev_err(mmc_dev(host->mmc), 479 "setting 1.8V failed, ret: %d\n", ret); 480 } else { 481 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 482 tegra_host->pinctrl_state_3v3); 483 if (ret < 0) 484 dev_err(mmc_dev(host->mmc), 485 "setting 3.3V failed, ret: %d\n", ret); 486 } 487 } 488 489 return ret; 490 } 491 492 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 493 { 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 496 struct sdhci_tegra_autocal_offsets offsets = 497 tegra_host->autocal_offsets; 498 struct mmc_ios *ios = &host->mmc->ios; 499 bool card_clk_enabled; 500 u16 pdpu; 501 u32 reg; 502 int ret; 503 504 switch (ios->timing) { 505 case MMC_TIMING_UHS_SDR104: 506 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 507 break; 508 case MMC_TIMING_MMC_HS400: 509 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 510 break; 511 default: 512 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 513 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 514 else 515 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 516 } 517 518 /* Set initial offset before auto-calibration */ 519 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 520 521 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 522 523 tegra_sdhci_configure_cal_pad(host, true); 524 525 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 526 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 527 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 528 529 usleep_range(1, 2); 530 /* 10 ms timeout */ 531 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 532 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 533 1000, 10000); 534 535 tegra_sdhci_configure_cal_pad(host, false); 536 537 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 538 539 if (ret) { 540 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 541 542 /* Disable automatic cal and use fixed Drive Strengths */ 543 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 544 reg &= ~SDHCI_AUTO_CAL_ENABLE; 545 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 546 547 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 548 if (ret < 0) 549 dev_err(mmc_dev(host->mmc), 550 "Setting drive strengths failed: %d\n", ret); 551 } 552 } 553 554 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 555 { 556 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 557 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 558 struct sdhci_tegra_autocal_offsets *autocal = 559 &tegra_host->autocal_offsets; 560 int err; 561 562 err = device_property_read_u32(host->mmc->parent, 563 "nvidia,pad-autocal-pull-up-offset-3v3", 564 &autocal->pull_up_3v3); 565 if (err) 566 autocal->pull_up_3v3 = 0; 567 568 err = device_property_read_u32(host->mmc->parent, 569 "nvidia,pad-autocal-pull-down-offset-3v3", 570 &autocal->pull_down_3v3); 571 if (err) 572 autocal->pull_down_3v3 = 0; 573 574 err = device_property_read_u32(host->mmc->parent, 575 "nvidia,pad-autocal-pull-up-offset-1v8", 576 &autocal->pull_up_1v8); 577 if (err) 578 autocal->pull_up_1v8 = 0; 579 580 err = device_property_read_u32(host->mmc->parent, 581 "nvidia,pad-autocal-pull-down-offset-1v8", 582 &autocal->pull_down_1v8); 583 if (err) 584 autocal->pull_down_1v8 = 0; 585 586 err = device_property_read_u32(host->mmc->parent, 587 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 588 &autocal->pull_up_3v3_timeout); 589 if (err) { 590 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 591 (tegra_host->pinctrl_state_3v3_drv == NULL)) 592 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 593 mmc_hostname(host->mmc)); 594 autocal->pull_up_3v3_timeout = 0; 595 } 596 597 err = device_property_read_u32(host->mmc->parent, 598 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 599 &autocal->pull_down_3v3_timeout); 600 if (err) { 601 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 602 (tegra_host->pinctrl_state_3v3_drv == NULL)) 603 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 604 mmc_hostname(host->mmc)); 605 autocal->pull_down_3v3_timeout = 0; 606 } 607 608 err = device_property_read_u32(host->mmc->parent, 609 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 610 &autocal->pull_up_1v8_timeout); 611 if (err) { 612 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 613 (tegra_host->pinctrl_state_1v8_drv == NULL)) 614 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 615 mmc_hostname(host->mmc)); 616 autocal->pull_up_1v8_timeout = 0; 617 } 618 619 err = device_property_read_u32(host->mmc->parent, 620 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 621 &autocal->pull_down_1v8_timeout); 622 if (err) { 623 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 624 (tegra_host->pinctrl_state_1v8_drv == NULL)) 625 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 626 mmc_hostname(host->mmc)); 627 autocal->pull_down_1v8_timeout = 0; 628 } 629 630 err = device_property_read_u32(host->mmc->parent, 631 "nvidia,pad-autocal-pull-up-offset-sdr104", 632 &autocal->pull_up_sdr104); 633 if (err) 634 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 635 636 err = device_property_read_u32(host->mmc->parent, 637 "nvidia,pad-autocal-pull-down-offset-sdr104", 638 &autocal->pull_down_sdr104); 639 if (err) 640 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 641 642 err = device_property_read_u32(host->mmc->parent, 643 "nvidia,pad-autocal-pull-up-offset-hs400", 644 &autocal->pull_up_hs400); 645 if (err) 646 autocal->pull_up_hs400 = autocal->pull_up_1v8; 647 648 err = device_property_read_u32(host->mmc->parent, 649 "nvidia,pad-autocal-pull-down-offset-hs400", 650 &autocal->pull_down_hs400); 651 if (err) 652 autocal->pull_down_hs400 = autocal->pull_down_1v8; 653 } 654 655 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 656 { 657 struct sdhci_host *host = mmc_priv(mmc); 658 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 659 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 660 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 661 662 /* 100 ms calibration interval is specified in the TRM */ 663 if (ktime_to_ms(since_calib) > 100) { 664 tegra_sdhci_pad_autocalib(host); 665 tegra_host->last_calib = ktime_get(); 666 } 667 668 sdhci_request(mmc, mrq); 669 } 670 671 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 672 { 673 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 674 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 675 int err; 676 677 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 678 &tegra_host->default_tap); 679 if (err) 680 tegra_host->default_tap = 0; 681 682 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 683 &tegra_host->default_trim); 684 if (err) 685 tegra_host->default_trim = 0; 686 687 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 688 &tegra_host->dqs_trim); 689 if (err) 690 tegra_host->dqs_trim = 0x11; 691 } 692 693 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 694 { 695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 696 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 697 698 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) 699 tegra_host->enable_hwcq = true; 700 else 701 tegra_host->enable_hwcq = false; 702 703 tegra_sdhci_parse_pad_autocal_dt(host); 704 tegra_sdhci_parse_tap_and_trim(host); 705 } 706 707 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 708 { 709 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 710 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 711 unsigned long host_clk; 712 713 if (!clock) 714 return sdhci_set_clock(host, clock); 715 716 /* 717 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 718 * divider to be configured to divided the host clock by two. The SDHCI 719 * clock divider is calculated as part of sdhci_set_clock() by 720 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 721 * the requested clock rate. 722 * 723 * By setting the host->max_clk to clock * 2 the divider calculation 724 * will always result in the correct value for DDR50/52 modes, 725 * regardless of clock rate rounding, which may happen if the value 726 * from clk_get_rate() is used. 727 */ 728 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 729 clk_set_rate(pltfm_host->clk, host_clk); 730 if (tegra_host->ddr_signaling) 731 host->max_clk = host_clk; 732 else 733 host->max_clk = clk_get_rate(pltfm_host->clk); 734 735 sdhci_set_clock(host, clock); 736 737 if (tegra_host->pad_calib_required) { 738 tegra_sdhci_pad_autocalib(host); 739 tegra_host->pad_calib_required = false; 740 } 741 } 742 743 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 744 { 745 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 746 747 return clk_round_rate(pltfm_host->clk, UINT_MAX); 748 } 749 750 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 751 { 752 u32 val; 753 754 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 755 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 756 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 757 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 758 } 759 760 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 761 { 762 u32 reg; 763 int err; 764 765 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 766 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 767 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 768 769 /* 1 ms sleep, 5 ms timeout */ 770 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 771 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 772 1000, 5000); 773 if (err) 774 dev_err(mmc_dev(host->mmc), 775 "HS400 delay line calibration timed out\n"); 776 } 777 778 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 779 unsigned timing) 780 { 781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 782 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 783 bool set_default_tap = false; 784 bool set_dqs_trim = false; 785 bool do_hs400_dll_cal = false; 786 787 switch (timing) { 788 case MMC_TIMING_UHS_SDR50: 789 case MMC_TIMING_UHS_SDR104: 790 case MMC_TIMING_MMC_HS200: 791 /* Don't set default tap on tunable modes. */ 792 break; 793 case MMC_TIMING_MMC_HS400: 794 set_dqs_trim = true; 795 do_hs400_dll_cal = true; 796 break; 797 case MMC_TIMING_MMC_DDR52: 798 case MMC_TIMING_UHS_DDR50: 799 tegra_host->ddr_signaling = true; 800 set_default_tap = true; 801 break; 802 default: 803 set_default_tap = true; 804 break; 805 } 806 807 sdhci_set_uhs_signaling(host, timing); 808 809 tegra_sdhci_pad_autocalib(host); 810 811 if (set_default_tap) 812 tegra_sdhci_set_tap(host, tegra_host->default_tap); 813 814 if (set_dqs_trim) 815 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 816 817 if (do_hs400_dll_cal) 818 tegra_sdhci_hs400_dll_cal(host); 819 } 820 821 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 822 { 823 unsigned int min, max; 824 825 /* 826 * Start search for minimum tap value at 10, as smaller values are 827 * may wrongly be reported as working but fail at higher speeds, 828 * according to the TRM. 829 */ 830 min = 10; 831 while (min < 255) { 832 tegra_sdhci_set_tap(host, min); 833 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 834 break; 835 min++; 836 } 837 838 /* Find the maximum tap value that still passes. */ 839 max = min + 1; 840 while (max < 255) { 841 tegra_sdhci_set_tap(host, max); 842 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 843 max--; 844 break; 845 } 846 max++; 847 } 848 849 /* The TRM states the ideal tap value is at 75% in the passing range. */ 850 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 851 852 return mmc_send_tuning(host->mmc, opcode, NULL); 853 } 854 855 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 856 struct mmc_ios *ios) 857 { 858 struct sdhci_host *host = mmc_priv(mmc); 859 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 860 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 861 int ret = 0; 862 863 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 864 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 865 if (ret < 0) 866 return ret; 867 ret = sdhci_start_signal_voltage_switch(mmc, ios); 868 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 869 ret = sdhci_start_signal_voltage_switch(mmc, ios); 870 if (ret < 0) 871 return ret; 872 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 873 } 874 875 if (tegra_host->pad_calib_required) 876 tegra_sdhci_pad_autocalib(host); 877 878 return ret; 879 } 880 881 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 882 struct sdhci_tegra *tegra_host) 883 { 884 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 885 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 886 dev_dbg(dev, "No pinctrl info, err: %ld\n", 887 PTR_ERR(tegra_host->pinctrl_sdmmc)); 888 return -1; 889 } 890 891 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 892 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 893 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 894 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 895 tegra_host->pinctrl_state_1v8_drv = NULL; 896 } 897 898 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 899 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 900 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 901 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 902 tegra_host->pinctrl_state_3v3_drv = NULL; 903 } 904 905 tegra_host->pinctrl_state_3v3 = 906 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 907 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 908 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 909 PTR_ERR(tegra_host->pinctrl_state_3v3)); 910 return -1; 911 } 912 913 tegra_host->pinctrl_state_1v8 = 914 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 915 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 916 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 917 PTR_ERR(tegra_host->pinctrl_state_1v8)); 918 return -1; 919 } 920 921 tegra_host->pad_control_available = true; 922 923 return 0; 924 } 925 926 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 927 { 928 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 929 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 930 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 931 932 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 933 tegra_host->pad_calib_required = true; 934 } 935 936 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 937 { 938 struct cqhci_host *cq_host = mmc->cqe_private; 939 u32 cqcfg = 0; 940 941 /* 942 * Tegra SDMMC Controller design prevents write access to BLOCK_COUNT 943 * registers when CQE is enabled. 944 */ 945 cqcfg = cqhci_readl(cq_host, CQHCI_CFG); 946 if (cqcfg & CQHCI_ENABLE) 947 cqhci_writel(cq_host, (cqcfg & ~CQHCI_ENABLE), CQHCI_CFG); 948 949 sdhci_cqe_enable(mmc); 950 951 if (cqcfg & CQHCI_ENABLE) 952 cqhci_writel(cq_host, cqcfg, CQHCI_CFG); 953 } 954 955 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 956 { 957 sdhci_dumpregs(mmc_priv(mmc)); 958 } 959 960 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 961 { 962 int cmd_error = 0; 963 int data_error = 0; 964 965 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 966 return intmask; 967 968 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 969 970 return 0; 971 } 972 973 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 974 .enable = sdhci_tegra_cqe_enable, 975 .disable = sdhci_cqe_disable, 976 .dumpregs = sdhci_tegra_dumpregs, 977 }; 978 979 static const struct sdhci_ops tegra_sdhci_ops = { 980 .get_ro = tegra_sdhci_get_ro, 981 .read_w = tegra_sdhci_readw, 982 .write_l = tegra_sdhci_writel, 983 .set_clock = tegra_sdhci_set_clock, 984 .set_bus_width = sdhci_set_bus_width, 985 .reset = tegra_sdhci_reset, 986 .platform_execute_tuning = tegra_sdhci_execute_tuning, 987 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 988 .voltage_switch = tegra_sdhci_voltage_switch, 989 .get_max_clock = tegra_sdhci_get_max_clock, 990 }; 991 992 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 993 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 994 SDHCI_QUIRK_SINGLE_POWER_WRITE | 995 SDHCI_QUIRK_NO_HISPD_BIT | 996 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 997 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 998 .ops = &tegra_sdhci_ops, 999 }; 1000 1001 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1002 .pdata = &sdhci_tegra20_pdata, 1003 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1004 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1005 }; 1006 1007 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1008 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1009 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1010 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1011 SDHCI_QUIRK_NO_HISPD_BIT | 1012 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1013 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1014 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1015 SDHCI_QUIRK2_BROKEN_HS200 | 1016 /* 1017 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1018 * though no command operation was in progress." 1019 * 1020 * The exact reason is unknown, as the same hardware seems 1021 * to support Auto CMD23 on a downstream 3.1 kernel. 1022 */ 1023 SDHCI_QUIRK2_ACMD23_BROKEN, 1024 .ops = &tegra_sdhci_ops, 1025 }; 1026 1027 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1028 .pdata = &sdhci_tegra30_pdata, 1029 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1030 NVQUIRK_ENABLE_SDR50 | 1031 NVQUIRK_ENABLE_SDR104 | 1032 NVQUIRK_HAS_PADCALIB, 1033 }; 1034 1035 static const struct sdhci_ops tegra114_sdhci_ops = { 1036 .get_ro = tegra_sdhci_get_ro, 1037 .read_w = tegra_sdhci_readw, 1038 .write_w = tegra_sdhci_writew, 1039 .write_l = tegra_sdhci_writel, 1040 .set_clock = tegra_sdhci_set_clock, 1041 .set_bus_width = sdhci_set_bus_width, 1042 .reset = tegra_sdhci_reset, 1043 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1044 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1045 .voltage_switch = tegra_sdhci_voltage_switch, 1046 .get_max_clock = tegra_sdhci_get_max_clock, 1047 }; 1048 1049 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1050 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1051 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1052 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1053 SDHCI_QUIRK_NO_HISPD_BIT | 1054 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1055 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1056 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1057 .ops = &tegra114_sdhci_ops, 1058 }; 1059 1060 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1061 .pdata = &sdhci_tegra114_pdata, 1062 }; 1063 1064 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1065 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1066 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1067 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1068 SDHCI_QUIRK_NO_HISPD_BIT | 1069 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1070 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1071 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1072 /* 1073 * The TRM states that the SD/MMC controller found on 1074 * Tegra124 can address 34 bits (the maximum supported by 1075 * the Tegra memory controller), but tests show that DMA 1076 * to or from above 4 GiB doesn't work. This is possibly 1077 * caused by missing programming, though it's not obvious 1078 * what sequence is required. Mark 64-bit DMA broken for 1079 * now to fix this for existing users (e.g. Nyan boards). 1080 */ 1081 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1082 .ops = &tegra114_sdhci_ops, 1083 }; 1084 1085 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1086 .pdata = &sdhci_tegra124_pdata, 1087 }; 1088 1089 static const struct sdhci_ops tegra210_sdhci_ops = { 1090 .get_ro = tegra_sdhci_get_ro, 1091 .read_w = tegra_sdhci_readw, 1092 .write_w = tegra210_sdhci_writew, 1093 .write_l = tegra_sdhci_writel, 1094 .set_clock = tegra_sdhci_set_clock, 1095 .set_bus_width = sdhci_set_bus_width, 1096 .reset = tegra_sdhci_reset, 1097 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1098 .voltage_switch = tegra_sdhci_voltage_switch, 1099 .get_max_clock = tegra_sdhci_get_max_clock, 1100 }; 1101 1102 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1103 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1104 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1105 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1106 SDHCI_QUIRK_NO_HISPD_BIT | 1107 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1108 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1109 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1110 .ops = &tegra210_sdhci_ops, 1111 }; 1112 1113 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1114 .pdata = &sdhci_tegra210_pdata, 1115 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1116 NVQUIRK_HAS_PADCALIB | 1117 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1118 NVQUIRK_ENABLE_SDR50 | 1119 NVQUIRK_ENABLE_SDR104, 1120 }; 1121 1122 static const struct sdhci_ops tegra186_sdhci_ops = { 1123 .get_ro = tegra_sdhci_get_ro, 1124 .read_w = tegra_sdhci_readw, 1125 .write_l = tegra_sdhci_writel, 1126 .set_clock = tegra_sdhci_set_clock, 1127 .set_bus_width = sdhci_set_bus_width, 1128 .reset = tegra_sdhci_reset, 1129 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1130 .voltage_switch = tegra_sdhci_voltage_switch, 1131 .get_max_clock = tegra_sdhci_get_max_clock, 1132 .irq = sdhci_tegra_cqhci_irq, 1133 }; 1134 1135 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1136 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1137 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1138 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1139 SDHCI_QUIRK_NO_HISPD_BIT | 1140 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1141 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1142 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1143 /* SDHCI controllers on Tegra186 support 40-bit addressing. 1144 * IOVA addresses are 48-bit wide on Tegra186. 1145 * With 64-bit dma mask used for SDHCI, accesses can 1146 * be broken. Disable 64-bit dma, which would fall back 1147 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 1148 * But it is not supported as of now. 1149 */ 1150 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1151 .ops = &tegra186_sdhci_ops, 1152 }; 1153 1154 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1155 .pdata = &sdhci_tegra186_pdata, 1156 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1157 NVQUIRK_HAS_PADCALIB | 1158 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1159 NVQUIRK_ENABLE_SDR50 | 1160 NVQUIRK_ENABLE_SDR104, 1161 }; 1162 1163 static const struct of_device_id sdhci_tegra_dt_match[] = { 1164 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1165 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1166 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1167 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1168 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1169 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1170 {} 1171 }; 1172 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1173 1174 static int sdhci_tegra_add_host(struct sdhci_host *host) 1175 { 1176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1177 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1178 struct cqhci_host *cq_host; 1179 bool dma64; 1180 int ret; 1181 1182 if (!tegra_host->enable_hwcq) 1183 return sdhci_add_host(host); 1184 1185 sdhci_enable_v4_mode(host); 1186 1187 ret = sdhci_setup_host(host); 1188 if (ret) 1189 return ret; 1190 1191 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1192 1193 cq_host = devm_kzalloc(host->mmc->parent, 1194 sizeof(*cq_host), GFP_KERNEL); 1195 if (!cq_host) { 1196 ret = -ENOMEM; 1197 goto cleanup; 1198 } 1199 1200 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1201 cq_host->ops = &sdhci_tegra_cqhci_ops; 1202 1203 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1204 if (dma64) 1205 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1206 1207 ret = cqhci_init(cq_host, host->mmc, dma64); 1208 if (ret) 1209 goto cleanup; 1210 1211 ret = __sdhci_add_host(host); 1212 if (ret) 1213 goto cleanup; 1214 1215 return 0; 1216 1217 cleanup: 1218 sdhci_cleanup_host(host); 1219 return ret; 1220 } 1221 1222 static int sdhci_tegra_probe(struct platform_device *pdev) 1223 { 1224 const struct of_device_id *match; 1225 const struct sdhci_tegra_soc_data *soc_data; 1226 struct sdhci_host *host; 1227 struct sdhci_pltfm_host *pltfm_host; 1228 struct sdhci_tegra *tegra_host; 1229 struct clk *clk; 1230 int rc; 1231 1232 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1233 if (!match) 1234 return -EINVAL; 1235 soc_data = match->data; 1236 1237 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1238 if (IS_ERR(host)) 1239 return PTR_ERR(host); 1240 pltfm_host = sdhci_priv(host); 1241 1242 tegra_host = sdhci_pltfm_priv(pltfm_host); 1243 tegra_host->ddr_signaling = false; 1244 tegra_host->pad_calib_required = false; 1245 tegra_host->pad_control_available = false; 1246 tegra_host->soc_data = soc_data; 1247 1248 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1249 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1250 if (rc == 0) 1251 host->mmc_host_ops.start_signal_voltage_switch = 1252 sdhci_tegra_start_signal_voltage_switch; 1253 } 1254 1255 /* Hook to periodically rerun pad calibration */ 1256 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1257 host->mmc_host_ops.request = tegra_sdhci_request; 1258 1259 host->mmc_host_ops.hs400_enhanced_strobe = 1260 tegra_sdhci_hs400_enhanced_strobe; 1261 1262 rc = mmc_of_parse(host->mmc); 1263 if (rc) 1264 goto err_parse_dt; 1265 1266 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1267 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1268 1269 tegra_sdhci_parse_dt(host); 1270 1271 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1272 GPIOD_OUT_HIGH); 1273 if (IS_ERR(tegra_host->power_gpio)) { 1274 rc = PTR_ERR(tegra_host->power_gpio); 1275 goto err_power_req; 1276 } 1277 1278 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1279 if (IS_ERR(clk)) { 1280 dev_err(mmc_dev(host->mmc), "clk err\n"); 1281 rc = PTR_ERR(clk); 1282 goto err_clk_get; 1283 } 1284 clk_prepare_enable(clk); 1285 pltfm_host->clk = clk; 1286 1287 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1288 "sdhci"); 1289 if (IS_ERR(tegra_host->rst)) { 1290 rc = PTR_ERR(tegra_host->rst); 1291 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1292 goto err_rst_get; 1293 } 1294 1295 rc = reset_control_assert(tegra_host->rst); 1296 if (rc) 1297 goto err_rst_get; 1298 1299 usleep_range(2000, 4000); 1300 1301 rc = reset_control_deassert(tegra_host->rst); 1302 if (rc) 1303 goto err_rst_get; 1304 1305 usleep_range(2000, 4000); 1306 1307 rc = sdhci_tegra_add_host(host); 1308 if (rc) 1309 goto err_add_host; 1310 1311 return 0; 1312 1313 err_add_host: 1314 reset_control_assert(tegra_host->rst); 1315 err_rst_get: 1316 clk_disable_unprepare(pltfm_host->clk); 1317 err_clk_get: 1318 err_power_req: 1319 err_parse_dt: 1320 sdhci_pltfm_free(pdev); 1321 return rc; 1322 } 1323 1324 static int sdhci_tegra_remove(struct platform_device *pdev) 1325 { 1326 struct sdhci_host *host = platform_get_drvdata(pdev); 1327 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1328 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1329 1330 sdhci_remove_host(host, 0); 1331 1332 reset_control_assert(tegra_host->rst); 1333 usleep_range(2000, 4000); 1334 clk_disable_unprepare(pltfm_host->clk); 1335 1336 sdhci_pltfm_free(pdev); 1337 1338 return 0; 1339 } 1340 1341 static struct platform_driver sdhci_tegra_driver = { 1342 .driver = { 1343 .name = "sdhci-tegra", 1344 .of_match_table = sdhci_tegra_dt_match, 1345 .pm = &sdhci_pltfm_pmops, 1346 }, 1347 .probe = sdhci_tegra_probe, 1348 .remove = sdhci_tegra_remove, 1349 }; 1350 1351 module_platform_driver(sdhci_tegra_driver); 1352 1353 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1354 MODULE_AUTHOR("Google, Inc."); 1355 MODULE_LICENSE("GPL v2"); 1356