1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 41 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 42 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 43 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 44 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 45 46 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 47 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 48 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 49 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 50 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 51 52 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 53 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 54 55 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 56 #define SDHCI_AUTO_CAL_START BIT(31) 57 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 58 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 59 60 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 61 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 62 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 63 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 64 65 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 66 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 67 68 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 69 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 70 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 71 #define NVQUIRK_ENABLE_SDR50 BIT(3) 72 #define NVQUIRK_ENABLE_SDR104 BIT(4) 73 #define NVQUIRK_ENABLE_DDR50 BIT(5) 74 #define NVQUIRK_HAS_PADCALIB BIT(6) 75 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 76 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 77 78 struct sdhci_tegra_soc_data { 79 const struct sdhci_pltfm_data *pdata; 80 u32 nvquirks; 81 }; 82 83 /* Magic pull up and pull down pad calibration offsets */ 84 struct sdhci_tegra_autocal_offsets { 85 u32 pull_up_3v3; 86 u32 pull_down_3v3; 87 u32 pull_up_3v3_timeout; 88 u32 pull_down_3v3_timeout; 89 u32 pull_up_1v8; 90 u32 pull_down_1v8; 91 u32 pull_up_1v8_timeout; 92 u32 pull_down_1v8_timeout; 93 u32 pull_up_sdr104; 94 u32 pull_down_sdr104; 95 u32 pull_up_hs400; 96 u32 pull_down_hs400; 97 }; 98 99 struct sdhci_tegra { 100 const struct sdhci_tegra_soc_data *soc_data; 101 struct gpio_desc *power_gpio; 102 bool ddr_signaling; 103 bool pad_calib_required; 104 bool pad_control_available; 105 106 struct reset_control *rst; 107 struct pinctrl *pinctrl_sdmmc; 108 struct pinctrl_state *pinctrl_state_3v3; 109 struct pinctrl_state *pinctrl_state_1v8; 110 111 struct sdhci_tegra_autocal_offsets autocal_offsets; 112 113 u32 default_tap; 114 u32 default_trim; 115 }; 116 117 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 118 { 119 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 120 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 121 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 122 123 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 124 (reg == SDHCI_HOST_VERSION))) { 125 /* Erratum: Version register is invalid in HW. */ 126 return SDHCI_SPEC_200; 127 } 128 129 return readw(host->ioaddr + reg); 130 } 131 132 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 133 { 134 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 135 136 switch (reg) { 137 case SDHCI_TRANSFER_MODE: 138 /* 139 * Postpone this write, we must do it together with a 140 * command write that is down below. 141 */ 142 pltfm_host->xfer_mode_shadow = val; 143 return; 144 case SDHCI_COMMAND: 145 writel((val << 16) | pltfm_host->xfer_mode_shadow, 146 host->ioaddr + SDHCI_TRANSFER_MODE); 147 return; 148 } 149 150 writew(val, host->ioaddr + reg); 151 } 152 153 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 154 { 155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 156 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 157 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 158 159 /* Seems like we're getting spurious timeout and crc errors, so 160 * disable signalling of them. In case of real errors software 161 * timers should take care of eventually detecting them. 162 */ 163 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 164 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 165 166 writel(val, host->ioaddr + reg); 167 168 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 169 (reg == SDHCI_INT_ENABLE))) { 170 /* Erratum: Must enable block gap interrupt detection */ 171 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 172 if (val & SDHCI_INT_CARD_INT) 173 gap_ctrl |= 0x8; 174 else 175 gap_ctrl &= ~0x8; 176 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 177 } 178 } 179 180 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 181 { 182 bool status; 183 u32 reg; 184 185 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 186 status = !!(reg & SDHCI_CLOCK_CARD_EN); 187 188 if (status == enable) 189 return status; 190 191 if (enable) 192 reg |= SDHCI_CLOCK_CARD_EN; 193 else 194 reg &= ~SDHCI_CLOCK_CARD_EN; 195 196 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 197 198 return status; 199 } 200 201 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 202 { 203 bool is_tuning_cmd = 0; 204 bool clk_enabled; 205 u8 cmd; 206 207 if (reg == SDHCI_COMMAND) { 208 cmd = SDHCI_GET_CMD(val); 209 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 210 cmd == MMC_SEND_TUNING_BLOCK_HS200; 211 } 212 213 if (is_tuning_cmd) 214 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 215 216 writew(val, host->ioaddr + reg); 217 218 if (is_tuning_cmd) { 219 udelay(1); 220 tegra_sdhci_configure_card_clk(host, clk_enabled); 221 } 222 } 223 224 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 225 { 226 return mmc_gpio_get_ro(host->mmc); 227 } 228 229 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 230 { 231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 232 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 233 int has_1v8, has_3v3; 234 235 /* 236 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 237 * voltage configuration in order to perform voltage switching. This 238 * means that valid pinctrl info is required on SDHCI instances capable 239 * of performing voltage switching. Whether or not an SDHCI instance is 240 * capable of voltage switching is determined based on the regulator. 241 */ 242 243 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 244 return true; 245 246 if (IS_ERR(host->mmc->supply.vqmmc)) 247 return false; 248 249 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 250 1700000, 1950000); 251 252 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 253 2700000, 3600000); 254 255 if (has_1v8 == 1 && has_3v3 == 1) 256 return tegra_host->pad_control_available; 257 258 /* Fixed voltage, no pad control required. */ 259 return true; 260 } 261 262 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 263 { 264 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 265 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 266 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 267 bool card_clk_enabled = false; 268 u32 reg; 269 270 /* 271 * Touching the tap values is a bit tricky on some SoC generations. 272 * The quirk enables a workaround for a glitch that sometimes occurs if 273 * the tap values are changed. 274 */ 275 276 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 277 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 278 279 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 280 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 281 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 282 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 283 284 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 285 card_clk_enabled) { 286 udelay(1); 287 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 288 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 289 } 290 } 291 292 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 293 { 294 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 295 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 296 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 297 u32 misc_ctrl, clk_ctrl, pad_ctrl; 298 299 sdhci_reset(host, mask); 300 301 if (!(mask & SDHCI_RESET_ALL)) 302 return; 303 304 tegra_sdhci_set_tap(host, tegra_host->default_tap); 305 306 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 307 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 308 309 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 310 SDHCI_MISC_CTRL_ENABLE_SDR50 | 311 SDHCI_MISC_CTRL_ENABLE_DDR50 | 312 SDHCI_MISC_CTRL_ENABLE_SDR104); 313 314 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 315 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 316 317 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 318 /* Erratum: Enable SDHCI spec v3.00 support */ 319 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 320 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 321 /* Advertise UHS modes as supported by host */ 322 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 323 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 324 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 325 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 326 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 327 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 328 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 329 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 330 } 331 332 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 333 334 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 335 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 336 337 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 338 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 339 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 340 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 341 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 342 343 tegra_host->pad_calib_required = true; 344 } 345 346 tegra_host->ddr_signaling = false; 347 } 348 349 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 350 { 351 u32 val; 352 353 /* 354 * Enable or disable the additional I/O pad used by the drive strength 355 * calibration process. 356 */ 357 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 358 359 if (enable) 360 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 361 else 362 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 363 364 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 365 366 if (enable) 367 usleep_range(1, 2); 368 } 369 370 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 371 u16 pdpu) 372 { 373 u32 reg; 374 375 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 376 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 377 reg |= pdpu; 378 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 379 } 380 381 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 382 { 383 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 384 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 385 struct sdhci_tegra_autocal_offsets offsets = 386 tegra_host->autocal_offsets; 387 struct mmc_ios *ios = &host->mmc->ios; 388 bool card_clk_enabled; 389 u16 pdpu; 390 u32 reg; 391 int ret; 392 393 switch (ios->timing) { 394 case MMC_TIMING_UHS_SDR104: 395 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 396 break; 397 case MMC_TIMING_MMC_HS400: 398 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 399 break; 400 default: 401 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 402 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 403 else 404 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 405 } 406 407 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 408 409 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 410 411 tegra_sdhci_configure_cal_pad(host, true); 412 413 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 414 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 415 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 416 417 usleep_range(1, 2); 418 /* 10 ms timeout */ 419 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 420 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 421 1000, 10000); 422 423 tegra_sdhci_configure_cal_pad(host, false); 424 425 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 426 427 if (ret) { 428 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 429 430 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 431 pdpu = offsets.pull_down_1v8_timeout << 8 | 432 offsets.pull_up_1v8_timeout; 433 else 434 pdpu = offsets.pull_down_3v3_timeout << 8 | 435 offsets.pull_up_3v3_timeout; 436 437 /* Disable automatic calibration and use fixed offsets */ 438 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 439 reg &= ~SDHCI_AUTO_CAL_ENABLE; 440 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 441 442 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 443 } 444 } 445 446 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 447 { 448 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 449 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 450 struct sdhci_tegra_autocal_offsets *autocal = 451 &tegra_host->autocal_offsets; 452 int err; 453 454 err = device_property_read_u32(host->mmc->parent, 455 "nvidia,pad-autocal-pull-up-offset-3v3", 456 &autocal->pull_up_3v3); 457 if (err) 458 autocal->pull_up_3v3 = 0; 459 460 err = device_property_read_u32(host->mmc->parent, 461 "nvidia,pad-autocal-pull-down-offset-3v3", 462 &autocal->pull_down_3v3); 463 if (err) 464 autocal->pull_down_3v3 = 0; 465 466 err = device_property_read_u32(host->mmc->parent, 467 "nvidia,pad-autocal-pull-up-offset-1v8", 468 &autocal->pull_up_1v8); 469 if (err) 470 autocal->pull_up_1v8 = 0; 471 472 err = device_property_read_u32(host->mmc->parent, 473 "nvidia,pad-autocal-pull-down-offset-1v8", 474 &autocal->pull_down_1v8); 475 if (err) 476 autocal->pull_down_1v8 = 0; 477 478 err = device_property_read_u32(host->mmc->parent, 479 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 480 &autocal->pull_up_3v3); 481 if (err) 482 autocal->pull_up_3v3_timeout = 0; 483 484 err = device_property_read_u32(host->mmc->parent, 485 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 486 &autocal->pull_down_3v3); 487 if (err) 488 autocal->pull_down_3v3_timeout = 0; 489 490 err = device_property_read_u32(host->mmc->parent, 491 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 492 &autocal->pull_up_1v8); 493 if (err) 494 autocal->pull_up_1v8_timeout = 0; 495 496 err = device_property_read_u32(host->mmc->parent, 497 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 498 &autocal->pull_down_1v8); 499 if (err) 500 autocal->pull_down_1v8_timeout = 0; 501 502 err = device_property_read_u32(host->mmc->parent, 503 "nvidia,pad-autocal-pull-up-offset-sdr104", 504 &autocal->pull_up_sdr104); 505 if (err) 506 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 507 508 err = device_property_read_u32(host->mmc->parent, 509 "nvidia,pad-autocal-pull-down-offset-sdr104", 510 &autocal->pull_down_sdr104); 511 if (err) 512 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 513 514 err = device_property_read_u32(host->mmc->parent, 515 "nvidia,pad-autocal-pull-up-offset-hs400", 516 &autocal->pull_up_hs400); 517 if (err) 518 autocal->pull_up_hs400 = autocal->pull_up_1v8; 519 520 err = device_property_read_u32(host->mmc->parent, 521 "nvidia,pad-autocal-pull-down-offset-hs400", 522 &autocal->pull_down_hs400); 523 if (err) 524 autocal->pull_down_hs400 = autocal->pull_down_1v8; 525 } 526 527 static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host) 528 { 529 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 530 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 531 int err; 532 533 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 534 &tegra_host->default_tap); 535 if (err) 536 tegra_host->default_tap = 0; 537 538 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 539 &tegra_host->default_trim); 540 if (err) 541 tegra_host->default_trim = 0; 542 } 543 544 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 545 { 546 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 547 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 548 unsigned long host_clk; 549 550 if (!clock) 551 return sdhci_set_clock(host, clock); 552 553 /* 554 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 555 * divider to be configured to divided the host clock by two. The SDHCI 556 * clock divider is calculated as part of sdhci_set_clock() by 557 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 558 * the requested clock rate. 559 * 560 * By setting the host->max_clk to clock * 2 the divider calculation 561 * will always result in the correct value for DDR50/52 modes, 562 * regardless of clock rate rounding, which may happen if the value 563 * from clk_get_rate() is used. 564 */ 565 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 566 clk_set_rate(pltfm_host->clk, host_clk); 567 if (tegra_host->ddr_signaling) 568 host->max_clk = host_clk; 569 else 570 host->max_clk = clk_get_rate(pltfm_host->clk); 571 572 sdhci_set_clock(host, clock); 573 574 if (tegra_host->pad_calib_required) { 575 tegra_sdhci_pad_autocalib(host); 576 tegra_host->pad_calib_required = false; 577 } 578 } 579 580 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 581 { 582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 583 584 return clk_round_rate(pltfm_host->clk, UINT_MAX); 585 } 586 587 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 588 unsigned timing) 589 { 590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 591 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 592 bool set_default_tap = false; 593 594 switch (timing) { 595 case MMC_TIMING_UHS_SDR50: 596 case MMC_TIMING_UHS_SDR104: 597 case MMC_TIMING_MMC_HS200: 598 case MMC_TIMING_MMC_HS400: 599 /* Don't set default tap on tunable modes. */ 600 break; 601 case MMC_TIMING_MMC_DDR52: 602 case MMC_TIMING_UHS_DDR50: 603 tegra_host->ddr_signaling = true; 604 set_default_tap = true; 605 break; 606 default: 607 set_default_tap = true; 608 break; 609 } 610 611 sdhci_set_uhs_signaling(host, timing); 612 613 tegra_sdhci_pad_autocalib(host); 614 615 if (set_default_tap) 616 tegra_sdhci_set_tap(host, tegra_host->default_tap); 617 } 618 619 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 620 { 621 unsigned int min, max; 622 623 /* 624 * Start search for minimum tap value at 10, as smaller values are 625 * may wrongly be reported as working but fail at higher speeds, 626 * according to the TRM. 627 */ 628 min = 10; 629 while (min < 255) { 630 tegra_sdhci_set_tap(host, min); 631 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 632 break; 633 min++; 634 } 635 636 /* Find the maximum tap value that still passes. */ 637 max = min + 1; 638 while (max < 255) { 639 tegra_sdhci_set_tap(host, max); 640 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 641 max--; 642 break; 643 } 644 max++; 645 } 646 647 /* The TRM states the ideal tap value is at 75% in the passing range. */ 648 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 649 650 return mmc_send_tuning(host->mmc, opcode, NULL); 651 } 652 653 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 654 { 655 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 656 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 657 int ret; 658 659 if (!tegra_host->pad_control_available) 660 return 0; 661 662 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 663 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 664 tegra_host->pinctrl_state_1v8); 665 if (ret < 0) 666 dev_err(mmc_dev(host->mmc), 667 "setting 1.8V failed, ret: %d\n", ret); 668 } else { 669 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 670 tegra_host->pinctrl_state_3v3); 671 if (ret < 0) 672 dev_err(mmc_dev(host->mmc), 673 "setting 3.3V failed, ret: %d\n", ret); 674 } 675 676 return ret; 677 } 678 679 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 680 struct mmc_ios *ios) 681 { 682 struct sdhci_host *host = mmc_priv(mmc); 683 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 684 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 685 int ret = 0; 686 687 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 688 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 689 if (ret < 0) 690 return ret; 691 ret = sdhci_start_signal_voltage_switch(mmc, ios); 692 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 693 ret = sdhci_start_signal_voltage_switch(mmc, ios); 694 if (ret < 0) 695 return ret; 696 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 697 } 698 699 if (tegra_host->pad_calib_required) 700 tegra_sdhci_pad_autocalib(host); 701 702 return ret; 703 } 704 705 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 706 struct sdhci_tegra *tegra_host) 707 { 708 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 709 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 710 dev_dbg(dev, "No pinctrl info, err: %ld\n", 711 PTR_ERR(tegra_host->pinctrl_sdmmc)); 712 return -1; 713 } 714 715 tegra_host->pinctrl_state_3v3 = 716 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 717 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 718 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 719 PTR_ERR(tegra_host->pinctrl_state_3v3)); 720 return -1; 721 } 722 723 tegra_host->pinctrl_state_1v8 = 724 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 725 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 726 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 727 PTR_ERR(tegra_host->pinctrl_state_3v3)); 728 return -1; 729 } 730 731 tegra_host->pad_control_available = true; 732 733 return 0; 734 } 735 736 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 737 { 738 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 739 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 740 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 741 742 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 743 tegra_host->pad_calib_required = true; 744 } 745 746 static const struct sdhci_ops tegra_sdhci_ops = { 747 .get_ro = tegra_sdhci_get_ro, 748 .read_w = tegra_sdhci_readw, 749 .write_l = tegra_sdhci_writel, 750 .set_clock = tegra_sdhci_set_clock, 751 .set_bus_width = sdhci_set_bus_width, 752 .reset = tegra_sdhci_reset, 753 .platform_execute_tuning = tegra_sdhci_execute_tuning, 754 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 755 .voltage_switch = tegra_sdhci_voltage_switch, 756 .get_max_clock = tegra_sdhci_get_max_clock, 757 }; 758 759 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 760 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 761 SDHCI_QUIRK_SINGLE_POWER_WRITE | 762 SDHCI_QUIRK_NO_HISPD_BIT | 763 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 764 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 765 .ops = &tegra_sdhci_ops, 766 }; 767 768 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 769 .pdata = &sdhci_tegra20_pdata, 770 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 771 NVQUIRK_ENABLE_BLOCK_GAP_DET, 772 }; 773 774 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 775 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 776 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 777 SDHCI_QUIRK_SINGLE_POWER_WRITE | 778 SDHCI_QUIRK_NO_HISPD_BIT | 779 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 780 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 781 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 782 SDHCI_QUIRK2_BROKEN_HS200 | 783 /* 784 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 785 * though no command operation was in progress." 786 * 787 * The exact reason is unknown, as the same hardware seems 788 * to support Auto CMD23 on a downstream 3.1 kernel. 789 */ 790 SDHCI_QUIRK2_ACMD23_BROKEN, 791 .ops = &tegra_sdhci_ops, 792 }; 793 794 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 795 .pdata = &sdhci_tegra30_pdata, 796 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 797 NVQUIRK_ENABLE_SDR50 | 798 NVQUIRK_ENABLE_SDR104 | 799 NVQUIRK_HAS_PADCALIB, 800 }; 801 802 static const struct sdhci_ops tegra114_sdhci_ops = { 803 .get_ro = tegra_sdhci_get_ro, 804 .read_w = tegra_sdhci_readw, 805 .write_w = tegra_sdhci_writew, 806 .write_l = tegra_sdhci_writel, 807 .set_clock = tegra_sdhci_set_clock, 808 .set_bus_width = sdhci_set_bus_width, 809 .reset = tegra_sdhci_reset, 810 .platform_execute_tuning = tegra_sdhci_execute_tuning, 811 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 812 .voltage_switch = tegra_sdhci_voltage_switch, 813 .get_max_clock = tegra_sdhci_get_max_clock, 814 }; 815 816 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 817 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 818 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 819 SDHCI_QUIRK_SINGLE_POWER_WRITE | 820 SDHCI_QUIRK_NO_HISPD_BIT | 821 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 822 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 823 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 824 .ops = &tegra114_sdhci_ops, 825 }; 826 827 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 828 .pdata = &sdhci_tegra114_pdata, 829 }; 830 831 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 832 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 833 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 834 SDHCI_QUIRK_SINGLE_POWER_WRITE | 835 SDHCI_QUIRK_NO_HISPD_BIT | 836 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 837 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 838 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 839 /* 840 * The TRM states that the SD/MMC controller found on 841 * Tegra124 can address 34 bits (the maximum supported by 842 * the Tegra memory controller), but tests show that DMA 843 * to or from above 4 GiB doesn't work. This is possibly 844 * caused by missing programming, though it's not obvious 845 * what sequence is required. Mark 64-bit DMA broken for 846 * now to fix this for existing users (e.g. Nyan boards). 847 */ 848 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 849 .ops = &tegra114_sdhci_ops, 850 }; 851 852 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 853 .pdata = &sdhci_tegra124_pdata, 854 }; 855 856 static const struct sdhci_ops tegra210_sdhci_ops = { 857 .get_ro = tegra_sdhci_get_ro, 858 .read_w = tegra_sdhci_readw, 859 .write_w = tegra210_sdhci_writew, 860 .write_l = tegra_sdhci_writel, 861 .set_clock = tegra_sdhci_set_clock, 862 .set_bus_width = sdhci_set_bus_width, 863 .reset = tegra_sdhci_reset, 864 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 865 .voltage_switch = tegra_sdhci_voltage_switch, 866 .get_max_clock = tegra_sdhci_get_max_clock, 867 }; 868 869 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 870 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 871 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 872 SDHCI_QUIRK_SINGLE_POWER_WRITE | 873 SDHCI_QUIRK_NO_HISPD_BIT | 874 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 875 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 876 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 877 .ops = &tegra210_sdhci_ops, 878 }; 879 880 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 881 .pdata = &sdhci_tegra210_pdata, 882 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 883 NVQUIRK_HAS_PADCALIB | 884 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 885 }; 886 887 static const struct sdhci_ops tegra186_sdhci_ops = { 888 .get_ro = tegra_sdhci_get_ro, 889 .read_w = tegra_sdhci_readw, 890 .write_l = tegra_sdhci_writel, 891 .set_clock = tegra_sdhci_set_clock, 892 .set_bus_width = sdhci_set_bus_width, 893 .reset = tegra_sdhci_reset, 894 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 895 .voltage_switch = tegra_sdhci_voltage_switch, 896 .get_max_clock = tegra_sdhci_get_max_clock, 897 }; 898 899 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 900 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 901 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 902 SDHCI_QUIRK_SINGLE_POWER_WRITE | 903 SDHCI_QUIRK_NO_HISPD_BIT | 904 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 905 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 906 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 907 /* SDHCI controllers on Tegra186 support 40-bit addressing. 908 * IOVA addresses are 48-bit wide on Tegra186. 909 * With 64-bit dma mask used for SDHCI, accesses can 910 * be broken. Disable 64-bit dma, which would fall back 911 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 912 * But it is not supported as of now. 913 */ 914 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 915 .ops = &tegra186_sdhci_ops, 916 }; 917 918 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 919 .pdata = &sdhci_tegra186_pdata, 920 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 921 NVQUIRK_HAS_PADCALIB | 922 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 923 }; 924 925 static const struct of_device_id sdhci_tegra_dt_match[] = { 926 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 927 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 928 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 929 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 930 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 931 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 932 {} 933 }; 934 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 935 936 static int sdhci_tegra_probe(struct platform_device *pdev) 937 { 938 const struct of_device_id *match; 939 const struct sdhci_tegra_soc_data *soc_data; 940 struct sdhci_host *host; 941 struct sdhci_pltfm_host *pltfm_host; 942 struct sdhci_tegra *tegra_host; 943 struct clk *clk; 944 int rc; 945 946 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 947 if (!match) 948 return -EINVAL; 949 soc_data = match->data; 950 951 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 952 if (IS_ERR(host)) 953 return PTR_ERR(host); 954 pltfm_host = sdhci_priv(host); 955 956 tegra_host = sdhci_pltfm_priv(pltfm_host); 957 tegra_host->ddr_signaling = false; 958 tegra_host->pad_calib_required = false; 959 tegra_host->pad_control_available = false; 960 tegra_host->soc_data = soc_data; 961 962 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 963 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 964 if (rc == 0) 965 host->mmc_host_ops.start_signal_voltage_switch = 966 sdhci_tegra_start_signal_voltage_switch; 967 } 968 969 rc = mmc_of_parse(host->mmc); 970 if (rc) 971 goto err_parse_dt; 972 973 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 974 host->mmc->caps |= MMC_CAP_1_8V_DDR; 975 976 tegra_sdhci_parse_pad_autocal_dt(host); 977 978 tegra_sdhci_parse_default_tap_and_trim(host); 979 980 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 981 GPIOD_OUT_HIGH); 982 if (IS_ERR(tegra_host->power_gpio)) { 983 rc = PTR_ERR(tegra_host->power_gpio); 984 goto err_power_req; 985 } 986 987 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 988 if (IS_ERR(clk)) { 989 dev_err(mmc_dev(host->mmc), "clk err\n"); 990 rc = PTR_ERR(clk); 991 goto err_clk_get; 992 } 993 clk_prepare_enable(clk); 994 pltfm_host->clk = clk; 995 996 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 997 "sdhci"); 998 if (IS_ERR(tegra_host->rst)) { 999 rc = PTR_ERR(tegra_host->rst); 1000 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1001 goto err_rst_get; 1002 } 1003 1004 rc = reset_control_assert(tegra_host->rst); 1005 if (rc) 1006 goto err_rst_get; 1007 1008 usleep_range(2000, 4000); 1009 1010 rc = reset_control_deassert(tegra_host->rst); 1011 if (rc) 1012 goto err_rst_get; 1013 1014 usleep_range(2000, 4000); 1015 1016 rc = sdhci_add_host(host); 1017 if (rc) 1018 goto err_add_host; 1019 1020 return 0; 1021 1022 err_add_host: 1023 reset_control_assert(tegra_host->rst); 1024 err_rst_get: 1025 clk_disable_unprepare(pltfm_host->clk); 1026 err_clk_get: 1027 err_power_req: 1028 err_parse_dt: 1029 sdhci_pltfm_free(pdev); 1030 return rc; 1031 } 1032 1033 static int sdhci_tegra_remove(struct platform_device *pdev) 1034 { 1035 struct sdhci_host *host = platform_get_drvdata(pdev); 1036 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1037 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1038 1039 sdhci_remove_host(host, 0); 1040 1041 reset_control_assert(tegra_host->rst); 1042 usleep_range(2000, 4000); 1043 clk_disable_unprepare(pltfm_host->clk); 1044 1045 sdhci_pltfm_free(pdev); 1046 1047 return 0; 1048 } 1049 1050 static struct platform_driver sdhci_tegra_driver = { 1051 .driver = { 1052 .name = "sdhci-tegra", 1053 .of_match_table = sdhci_tegra_dt_match, 1054 .pm = &sdhci_pltfm_pmops, 1055 }, 1056 .probe = sdhci_tegra_probe, 1057 .remove = sdhci_tegra_remove, 1058 }; 1059 1060 module_platform_driver(sdhci_tegra_driver); 1061 1062 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1063 MODULE_AUTHOR("Google, Inc."); 1064 MODULE_LICENSE("GPL v2"); 1065