1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/reset.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/gpio/consumer.h> 30 31 #include "sdhci-pltfm.h" 32 33 /* Tegra SDHOST controller vendor register definitions */ 34 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 35 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 36 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 37 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 38 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 39 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 40 41 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 42 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 43 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 44 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 45 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 46 47 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 48 #define SDHCI_AUTO_CAL_START BIT(31) 49 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 50 51 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 52 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 53 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 54 #define NVQUIRK_ENABLE_SDR50 BIT(3) 55 #define NVQUIRK_ENABLE_SDR104 BIT(4) 56 #define NVQUIRK_ENABLE_DDR50 BIT(5) 57 #define NVQUIRK_HAS_PADCALIB BIT(6) 58 59 struct sdhci_tegra_soc_data { 60 const struct sdhci_pltfm_data *pdata; 61 u32 nvquirks; 62 }; 63 64 struct sdhci_tegra { 65 const struct sdhci_tegra_soc_data *soc_data; 66 struct gpio_desc *power_gpio; 67 bool ddr_signaling; 68 bool pad_calib_required; 69 70 struct reset_control *rst; 71 }; 72 73 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 74 { 75 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 76 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 77 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 78 79 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 80 (reg == SDHCI_HOST_VERSION))) { 81 /* Erratum: Version register is invalid in HW. */ 82 return SDHCI_SPEC_200; 83 } 84 85 return readw(host->ioaddr + reg); 86 } 87 88 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 89 { 90 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 91 92 switch (reg) { 93 case SDHCI_TRANSFER_MODE: 94 /* 95 * Postpone this write, we must do it together with a 96 * command write that is down below. 97 */ 98 pltfm_host->xfer_mode_shadow = val; 99 return; 100 case SDHCI_COMMAND: 101 writel((val << 16) | pltfm_host->xfer_mode_shadow, 102 host->ioaddr + SDHCI_TRANSFER_MODE); 103 return; 104 } 105 106 writew(val, host->ioaddr + reg); 107 } 108 109 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 110 { 111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 112 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 113 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 114 115 /* Seems like we're getting spurious timeout and crc errors, so 116 * disable signalling of them. In case of real errors software 117 * timers should take care of eventually detecting them. 118 */ 119 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 120 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 121 122 writel(val, host->ioaddr + reg); 123 124 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 125 (reg == SDHCI_INT_ENABLE))) { 126 /* Erratum: Must enable block gap interrupt detection */ 127 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 128 if (val & SDHCI_INT_CARD_INT) 129 gap_ctrl |= 0x8; 130 else 131 gap_ctrl &= ~0x8; 132 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 133 } 134 } 135 136 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 137 { 138 return mmc_gpio_get_ro(host->mmc); 139 } 140 141 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 142 { 143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 144 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 145 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 146 u32 misc_ctrl, clk_ctrl; 147 148 sdhci_reset(host, mask); 149 150 if (!(mask & SDHCI_RESET_ALL)) 151 return; 152 153 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 154 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 155 156 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 157 SDHCI_MISC_CTRL_ENABLE_SDR50 | 158 SDHCI_MISC_CTRL_ENABLE_DDR50 | 159 SDHCI_MISC_CTRL_ENABLE_SDR104); 160 161 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 162 163 /* 164 * If the board does not define a regulator for the SDHCI 165 * IO voltage, then don't advertise support for UHS modes 166 * even if the device supports it because the IO voltage 167 * cannot be configured. 168 */ 169 if (!IS_ERR(host->mmc->supply.vqmmc)) { 170 /* Erratum: Enable SDHCI spec v3.00 support */ 171 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 172 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 173 /* Advertise UHS modes as supported by host */ 174 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 175 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 176 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 177 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 178 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 179 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 180 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 181 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 182 } 183 184 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 185 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 186 187 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 188 tegra_host->pad_calib_required = true; 189 190 tegra_host->ddr_signaling = false; 191 } 192 193 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 194 { 195 u32 val; 196 197 mdelay(1); 198 199 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 200 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 201 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); 202 } 203 204 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 205 { 206 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 207 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 208 unsigned long host_clk; 209 210 if (!clock) 211 return sdhci_set_clock(host, clock); 212 213 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 214 clk_set_rate(pltfm_host->clk, host_clk); 215 host->max_clk = clk_get_rate(pltfm_host->clk); 216 217 sdhci_set_clock(host, clock); 218 219 if (tegra_host->pad_calib_required) { 220 tegra_sdhci_pad_autocalib(host); 221 tegra_host->pad_calib_required = false; 222 } 223 } 224 225 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 226 unsigned timing) 227 { 228 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 229 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 230 231 if (timing == MMC_TIMING_UHS_DDR50) 232 tegra_host->ddr_signaling = true; 233 234 sdhci_set_uhs_signaling(host, timing); 235 } 236 237 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 238 { 239 u32 reg; 240 241 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 242 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 243 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 244 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 245 } 246 247 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 248 { 249 unsigned int min, max; 250 251 /* 252 * Start search for minimum tap value at 10, as smaller values are 253 * may wrongly be reported as working but fail at higher speeds, 254 * according to the TRM. 255 */ 256 min = 10; 257 while (min < 255) { 258 tegra_sdhci_set_tap(host, min); 259 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 260 break; 261 min++; 262 } 263 264 /* Find the maximum tap value that still passes. */ 265 max = min + 1; 266 while (max < 255) { 267 tegra_sdhci_set_tap(host, max); 268 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 269 max--; 270 break; 271 } 272 max++; 273 } 274 275 /* The TRM states the ideal tap value is at 75% in the passing range. */ 276 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 277 278 return mmc_send_tuning(host->mmc, opcode, NULL); 279 } 280 281 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 282 { 283 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 284 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 285 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 286 287 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 288 tegra_host->pad_calib_required = true; 289 } 290 291 static const struct sdhci_ops tegra_sdhci_ops = { 292 .get_ro = tegra_sdhci_get_ro, 293 .read_w = tegra_sdhci_readw, 294 .write_l = tegra_sdhci_writel, 295 .set_clock = tegra_sdhci_set_clock, 296 .set_bus_width = sdhci_set_bus_width, 297 .reset = tegra_sdhci_reset, 298 .platform_execute_tuning = tegra_sdhci_execute_tuning, 299 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 300 .voltage_switch = tegra_sdhci_voltage_switch, 301 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 302 }; 303 304 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 305 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 306 SDHCI_QUIRK_SINGLE_POWER_WRITE | 307 SDHCI_QUIRK_NO_HISPD_BIT | 308 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 309 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 310 .ops = &tegra_sdhci_ops, 311 }; 312 313 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 314 .pdata = &sdhci_tegra20_pdata, 315 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 316 NVQUIRK_ENABLE_BLOCK_GAP_DET, 317 }; 318 319 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 320 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 321 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 322 SDHCI_QUIRK_SINGLE_POWER_WRITE | 323 SDHCI_QUIRK_NO_HISPD_BIT | 324 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 325 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 326 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 327 SDHCI_QUIRK2_BROKEN_HS200, 328 .ops = &tegra_sdhci_ops, 329 }; 330 331 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 332 .pdata = &sdhci_tegra30_pdata, 333 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 334 NVQUIRK_ENABLE_SDR50 | 335 NVQUIRK_ENABLE_SDR104 | 336 NVQUIRK_HAS_PADCALIB, 337 }; 338 339 static const struct sdhci_ops tegra114_sdhci_ops = { 340 .get_ro = tegra_sdhci_get_ro, 341 .read_w = tegra_sdhci_readw, 342 .write_w = tegra_sdhci_writew, 343 .write_l = tegra_sdhci_writel, 344 .set_clock = tegra_sdhci_set_clock, 345 .set_bus_width = sdhci_set_bus_width, 346 .reset = tegra_sdhci_reset, 347 .platform_execute_tuning = tegra_sdhci_execute_tuning, 348 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 349 .voltage_switch = tegra_sdhci_voltage_switch, 350 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 351 }; 352 353 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 354 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 355 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 356 SDHCI_QUIRK_SINGLE_POWER_WRITE | 357 SDHCI_QUIRK_NO_HISPD_BIT | 358 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 359 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 360 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 361 .ops = &tegra114_sdhci_ops, 362 }; 363 364 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 365 .pdata = &sdhci_tegra114_pdata, 366 }; 367 368 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 369 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 370 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 371 SDHCI_QUIRK_SINGLE_POWER_WRITE | 372 SDHCI_QUIRK_NO_HISPD_BIT | 373 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 374 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 375 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 376 /* 377 * The TRM states that the SD/MMC controller found on 378 * Tegra124 can address 34 bits (the maximum supported by 379 * the Tegra memory controller), but tests show that DMA 380 * to or from above 4 GiB doesn't work. This is possibly 381 * caused by missing programming, though it's not obvious 382 * what sequence is required. Mark 64-bit DMA broken for 383 * now to fix this for existing users (e.g. Nyan boards). 384 */ 385 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 386 .ops = &tegra114_sdhci_ops, 387 }; 388 389 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 390 .pdata = &sdhci_tegra124_pdata, 391 }; 392 393 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 394 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 395 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 396 SDHCI_QUIRK_SINGLE_POWER_WRITE | 397 SDHCI_QUIRK_NO_HISPD_BIT | 398 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 399 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 400 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 401 .ops = &tegra114_sdhci_ops, 402 }; 403 404 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 405 .pdata = &sdhci_tegra210_pdata, 406 }; 407 408 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 409 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 410 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 411 SDHCI_QUIRK_SINGLE_POWER_WRITE | 412 SDHCI_QUIRK_NO_HISPD_BIT | 413 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 414 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 415 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 416 /* SDHCI controllers on Tegra186 support 40-bit addressing. 417 * IOVA addresses are 48-bit wide on Tegra186. 418 * With 64-bit dma mask used for SDHCI, accesses can 419 * be broken. Disable 64-bit dma, which would fall back 420 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 421 * But it is not supported as of now. 422 */ 423 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 424 .ops = &tegra114_sdhci_ops, 425 }; 426 427 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 428 .pdata = &sdhci_tegra186_pdata, 429 }; 430 431 static const struct of_device_id sdhci_tegra_dt_match[] = { 432 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 433 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 434 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 435 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 436 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 437 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 438 {} 439 }; 440 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 441 442 static int sdhci_tegra_probe(struct platform_device *pdev) 443 { 444 const struct of_device_id *match; 445 const struct sdhci_tegra_soc_data *soc_data; 446 struct sdhci_host *host; 447 struct sdhci_pltfm_host *pltfm_host; 448 struct sdhci_tegra *tegra_host; 449 struct clk *clk; 450 int rc; 451 452 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 453 if (!match) 454 return -EINVAL; 455 soc_data = match->data; 456 457 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 458 if (IS_ERR(host)) 459 return PTR_ERR(host); 460 pltfm_host = sdhci_priv(host); 461 462 tegra_host = sdhci_pltfm_priv(pltfm_host); 463 tegra_host->ddr_signaling = false; 464 tegra_host->pad_calib_required = false; 465 tegra_host->soc_data = soc_data; 466 467 rc = mmc_of_parse(host->mmc); 468 if (rc) 469 goto err_parse_dt; 470 471 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 472 host->mmc->caps |= MMC_CAP_1_8V_DDR; 473 474 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 475 GPIOD_OUT_HIGH); 476 if (IS_ERR(tegra_host->power_gpio)) { 477 rc = PTR_ERR(tegra_host->power_gpio); 478 goto err_power_req; 479 } 480 481 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 482 if (IS_ERR(clk)) { 483 dev_err(mmc_dev(host->mmc), "clk err\n"); 484 rc = PTR_ERR(clk); 485 goto err_clk_get; 486 } 487 clk_prepare_enable(clk); 488 pltfm_host->clk = clk; 489 490 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 491 "sdhci"); 492 if (IS_ERR(tegra_host->rst)) { 493 rc = PTR_ERR(tegra_host->rst); 494 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 495 goto err_rst_get; 496 } 497 498 rc = reset_control_assert(tegra_host->rst); 499 if (rc) 500 goto err_rst_get; 501 502 usleep_range(2000, 4000); 503 504 rc = reset_control_deassert(tegra_host->rst); 505 if (rc) 506 goto err_rst_get; 507 508 usleep_range(2000, 4000); 509 510 rc = sdhci_add_host(host); 511 if (rc) 512 goto err_add_host; 513 514 return 0; 515 516 err_add_host: 517 reset_control_assert(tegra_host->rst); 518 err_rst_get: 519 clk_disable_unprepare(pltfm_host->clk); 520 err_clk_get: 521 err_power_req: 522 err_parse_dt: 523 sdhci_pltfm_free(pdev); 524 return rc; 525 } 526 527 static int sdhci_tegra_remove(struct platform_device *pdev) 528 { 529 struct sdhci_host *host = platform_get_drvdata(pdev); 530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 531 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 532 533 sdhci_remove_host(host, 0); 534 535 reset_control_assert(tegra_host->rst); 536 usleep_range(2000, 4000); 537 clk_disable_unprepare(pltfm_host->clk); 538 539 sdhci_pltfm_free(pdev); 540 541 return 0; 542 } 543 544 static struct platform_driver sdhci_tegra_driver = { 545 .driver = { 546 .name = "sdhci-tegra", 547 .of_match_table = sdhci_tegra_dt_match, 548 .pm = &sdhci_pltfm_pmops, 549 }, 550 .probe = sdhci_tegra_probe, 551 .remove = sdhci_tegra_remove, 552 }; 553 554 module_platform_driver(sdhci_tegra_driver); 555 556 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 557 MODULE_AUTHOR("Google, Inc."); 558 MODULE_LICENSE("GPL v2"); 559