1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/ktime.h> 15 #include <linux/mmc/card.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mmc/mmc.h> 18 #include <linux/mmc/slot-gpio.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/of.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_opp.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 29 #include <soc/tegra/common.h> 30 31 #include "sdhci-cqhci.h" 32 #include "sdhci-pltfm.h" 33 #include "cqhci.h" 34 35 /* Tegra SDHOST controller vendor register definitions */ 36 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 37 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 38 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 39 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 40 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 41 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 42 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 43 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 44 45 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 46 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 47 48 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 49 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 50 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 51 52 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 53 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 54 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 55 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 56 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 57 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 58 59 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 60 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 61 62 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 63 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 64 65 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 66 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 67 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 68 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 69 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 70 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 71 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 72 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 73 #define TRIES_128 2 74 #define TRIES_256 4 75 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 76 77 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 78 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 79 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 80 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 81 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 82 #define TUNING_WORD_BIT_SIZE 32 83 84 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 85 #define SDHCI_AUTO_CAL_START BIT(31) 86 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 87 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 88 89 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 90 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 91 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 92 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 93 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 94 95 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 96 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 97 98 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 99 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 100 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 101 #define NVQUIRK_ENABLE_SDR50 BIT(3) 102 #define NVQUIRK_ENABLE_SDR104 BIT(4) 103 #define NVQUIRK_ENABLE_DDR50 BIT(5) 104 /* 105 * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads 106 * drive strength. 107 */ 108 #define NVQUIRK_HAS_PADCALIB BIT(6) 109 /* 110 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. 111 * 3V3/1V8 pad selection happens through pinctrl state selection depending 112 * on the signaling mode. 113 */ 114 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 115 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 116 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 117 118 /* 119 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra 120 * SDMMC hardware data timeout. 121 */ 122 #define NVQUIRK_HAS_TMCLK BIT(10) 123 124 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 125 126 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 127 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 128 129 #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 130 SDHCI_TRNS_BLK_CNT_EN | \ 131 SDHCI_TRNS_DMA) 132 133 struct sdhci_tegra_soc_data { 134 const struct sdhci_pltfm_data *pdata; 135 u64 dma_mask; 136 u32 nvquirks; 137 u8 min_tap_delay; 138 u8 max_tap_delay; 139 }; 140 141 /* Magic pull up and pull down pad calibration offsets */ 142 struct sdhci_tegra_autocal_offsets { 143 u32 pull_up_3v3; 144 u32 pull_down_3v3; 145 u32 pull_up_3v3_timeout; 146 u32 pull_down_3v3_timeout; 147 u32 pull_up_1v8; 148 u32 pull_down_1v8; 149 u32 pull_up_1v8_timeout; 150 u32 pull_down_1v8_timeout; 151 u32 pull_up_sdr104; 152 u32 pull_down_sdr104; 153 u32 pull_up_hs400; 154 u32 pull_down_hs400; 155 }; 156 157 struct sdhci_tegra { 158 const struct sdhci_tegra_soc_data *soc_data; 159 struct gpio_desc *power_gpio; 160 struct clk *tmclk; 161 bool ddr_signaling; 162 bool pad_calib_required; 163 bool pad_control_available; 164 165 struct reset_control *rst; 166 struct pinctrl *pinctrl_sdmmc; 167 struct pinctrl_state *pinctrl_state_3v3; 168 struct pinctrl_state *pinctrl_state_1v8; 169 struct pinctrl_state *pinctrl_state_3v3_drv; 170 struct pinctrl_state *pinctrl_state_1v8_drv; 171 172 struct sdhci_tegra_autocal_offsets autocal_offsets; 173 ktime_t last_calib; 174 175 u32 default_tap; 176 u32 default_trim; 177 u32 dqs_trim; 178 bool enable_hwcq; 179 unsigned long curr_clk_rate; 180 u8 tuned_tap_delay; 181 }; 182 183 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 187 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 188 189 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 190 (reg == SDHCI_HOST_VERSION))) { 191 /* Erratum: Version register is invalid in HW. */ 192 return SDHCI_SPEC_200; 193 } 194 195 return readw(host->ioaddr + reg); 196 } 197 198 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 199 { 200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 201 202 switch (reg) { 203 case SDHCI_TRANSFER_MODE: 204 /* 205 * Postpone this write, we must do it together with a 206 * command write that is down below. 207 */ 208 pltfm_host->xfer_mode_shadow = val; 209 return; 210 case SDHCI_COMMAND: 211 writel((val << 16) | pltfm_host->xfer_mode_shadow, 212 host->ioaddr + SDHCI_TRANSFER_MODE); 213 return; 214 } 215 216 writew(val, host->ioaddr + reg); 217 } 218 219 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 220 { 221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 223 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 224 225 /* Seems like we're getting spurious timeout and crc errors, so 226 * disable signalling of them. In case of real errors software 227 * timers should take care of eventually detecting them. 228 */ 229 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 230 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 231 232 writel(val, host->ioaddr + reg); 233 234 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 235 (reg == SDHCI_INT_ENABLE))) { 236 /* Erratum: Must enable block gap interrupt detection */ 237 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 238 if (val & SDHCI_INT_CARD_INT) 239 gap_ctrl |= 0x8; 240 else 241 gap_ctrl &= ~0x8; 242 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 243 } 244 } 245 246 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 247 { 248 bool status; 249 u32 reg; 250 251 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 252 status = !!(reg & SDHCI_CLOCK_CARD_EN); 253 254 if (status == enable) 255 return status; 256 257 if (enable) 258 reg |= SDHCI_CLOCK_CARD_EN; 259 else 260 reg &= ~SDHCI_CLOCK_CARD_EN; 261 262 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 263 264 return status; 265 } 266 267 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 268 { 269 bool is_tuning_cmd = 0; 270 bool clk_enabled; 271 272 if (reg == SDHCI_COMMAND) 273 is_tuning_cmd = mmc_op_tuning(SDHCI_GET_CMD(val)); 274 275 if (is_tuning_cmd) 276 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 277 278 writew(val, host->ioaddr + reg); 279 280 if (is_tuning_cmd) { 281 udelay(1); 282 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 283 tegra_sdhci_configure_card_clk(host, clk_enabled); 284 } 285 } 286 287 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 288 { 289 /* 290 * Write-enable shall be assumed if GPIO is missing in a board's 291 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 292 * Tegra. 293 */ 294 return mmc_gpio_get_ro(host->mmc); 295 } 296 297 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 298 { 299 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 300 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 301 int has_1v8, has_3v3; 302 303 /* 304 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 305 * voltage configuration in order to perform voltage switching. This 306 * means that valid pinctrl info is required on SDHCI instances capable 307 * of performing voltage switching. Whether or not an SDHCI instance is 308 * capable of voltage switching is determined based on the regulator. 309 */ 310 311 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 312 return true; 313 314 if (IS_ERR(host->mmc->supply.vqmmc)) 315 return false; 316 317 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 318 1700000, 1950000); 319 320 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 321 2700000, 3600000); 322 323 if (has_1v8 == 1 && has_3v3 == 1) 324 return tegra_host->pad_control_available; 325 326 /* Fixed voltage, no pad control required. */ 327 return true; 328 } 329 330 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 331 { 332 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 333 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 334 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 335 bool card_clk_enabled = false; 336 u32 reg; 337 338 /* 339 * Touching the tap values is a bit tricky on some SoC generations. 340 * The quirk enables a workaround for a glitch that sometimes occurs if 341 * the tap values are changed. 342 */ 343 344 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 345 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 346 347 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 348 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 349 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 350 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 351 352 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 353 card_clk_enabled) { 354 udelay(1); 355 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 356 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 357 } 358 } 359 360 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 361 { 362 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 363 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 364 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 365 u32 misc_ctrl, clk_ctrl, pad_ctrl; 366 367 sdhci_and_cqhci_reset(host, mask); 368 369 if (!(mask & SDHCI_RESET_ALL)) 370 return; 371 372 tegra_sdhci_set_tap(host, tegra_host->default_tap); 373 374 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 375 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 376 377 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 378 SDHCI_MISC_CTRL_ENABLE_SDR50 | 379 SDHCI_MISC_CTRL_ENABLE_DDR50 | 380 SDHCI_MISC_CTRL_ENABLE_SDR104); 381 382 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 383 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 384 385 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 386 /* Erratum: Enable SDHCI spec v3.00 support */ 387 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 388 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 389 /* Advertise UHS modes as supported by host */ 390 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 391 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 392 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 393 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 394 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 395 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 396 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 397 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 398 } 399 400 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 401 402 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 403 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 404 405 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 406 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 407 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 408 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 409 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 410 411 tegra_host->pad_calib_required = true; 412 } 413 414 tegra_host->ddr_signaling = false; 415 } 416 417 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 418 { 419 u32 val; 420 421 /* 422 * Enable or disable the additional I/O pad used by the drive strength 423 * calibration process. 424 */ 425 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 426 427 if (enable) 428 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 429 else 430 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 431 432 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 433 434 if (enable) 435 usleep_range(1, 2); 436 } 437 438 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 439 u16 pdpu) 440 { 441 u32 reg; 442 443 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 444 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 445 reg |= pdpu; 446 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 447 } 448 449 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 450 bool state_drvupdn) 451 { 452 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 453 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 454 struct sdhci_tegra_autocal_offsets *offsets = 455 &tegra_host->autocal_offsets; 456 struct pinctrl_state *pinctrl_drvupdn = NULL; 457 int ret = 0; 458 u8 drvup = 0, drvdn = 0; 459 u32 reg; 460 461 if (!state_drvupdn) { 462 /* PADS Drive Strength */ 463 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 464 if (tegra_host->pinctrl_state_1v8_drv) { 465 pinctrl_drvupdn = 466 tegra_host->pinctrl_state_1v8_drv; 467 } else { 468 drvup = offsets->pull_up_1v8_timeout; 469 drvdn = offsets->pull_down_1v8_timeout; 470 } 471 } else { 472 if (tegra_host->pinctrl_state_3v3_drv) { 473 pinctrl_drvupdn = 474 tegra_host->pinctrl_state_3v3_drv; 475 } else { 476 drvup = offsets->pull_up_3v3_timeout; 477 drvdn = offsets->pull_down_3v3_timeout; 478 } 479 } 480 481 if (pinctrl_drvupdn != NULL) { 482 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 483 pinctrl_drvupdn); 484 if (ret < 0) 485 dev_err(mmc_dev(host->mmc), 486 "failed pads drvupdn, ret: %d\n", ret); 487 } else if ((drvup) || (drvdn)) { 488 reg = sdhci_readl(host, 489 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 490 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 491 reg |= (drvup << 20) | (drvdn << 12); 492 sdhci_writel(host, reg, 493 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 494 } 495 496 } else { 497 /* Dual Voltage PADS Voltage selection */ 498 if (!tegra_host->pad_control_available) 499 return 0; 500 501 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 502 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 503 tegra_host->pinctrl_state_1v8); 504 if (ret < 0) 505 dev_err(mmc_dev(host->mmc), 506 "setting 1.8V failed, ret: %d\n", ret); 507 } else { 508 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 509 tegra_host->pinctrl_state_3v3); 510 if (ret < 0) 511 dev_err(mmc_dev(host->mmc), 512 "setting 3.3V failed, ret: %d\n", ret); 513 } 514 } 515 516 return ret; 517 } 518 519 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 520 { 521 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 522 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 523 struct sdhci_tegra_autocal_offsets offsets = 524 tegra_host->autocal_offsets; 525 struct mmc_ios *ios = &host->mmc->ios; 526 bool card_clk_enabled; 527 u16 pdpu; 528 u32 reg; 529 int ret; 530 531 switch (ios->timing) { 532 case MMC_TIMING_UHS_SDR104: 533 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 534 break; 535 case MMC_TIMING_MMC_HS400: 536 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 537 break; 538 default: 539 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 540 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 541 else 542 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 543 } 544 545 /* Set initial offset before auto-calibration */ 546 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 547 548 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 549 550 tegra_sdhci_configure_cal_pad(host, true); 551 552 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 553 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 554 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 555 556 usleep_range(1, 2); 557 /* 10 ms timeout */ 558 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 559 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 560 1000, 10000); 561 562 tegra_sdhci_configure_cal_pad(host, false); 563 564 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 565 566 if (ret) { 567 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 568 569 /* Disable automatic cal and use fixed Drive Strengths */ 570 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 571 reg &= ~SDHCI_AUTO_CAL_ENABLE; 572 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 573 574 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 575 if (ret < 0) 576 dev_err(mmc_dev(host->mmc), 577 "Setting drive strengths failed: %d\n", ret); 578 } 579 } 580 581 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 582 { 583 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 584 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 585 struct sdhci_tegra_autocal_offsets *autocal = 586 &tegra_host->autocal_offsets; 587 int err; 588 589 err = device_property_read_u32(mmc_dev(host->mmc), 590 "nvidia,pad-autocal-pull-up-offset-3v3", 591 &autocal->pull_up_3v3); 592 if (err) 593 autocal->pull_up_3v3 = 0; 594 595 err = device_property_read_u32(mmc_dev(host->mmc), 596 "nvidia,pad-autocal-pull-down-offset-3v3", 597 &autocal->pull_down_3v3); 598 if (err) 599 autocal->pull_down_3v3 = 0; 600 601 err = device_property_read_u32(mmc_dev(host->mmc), 602 "nvidia,pad-autocal-pull-up-offset-1v8", 603 &autocal->pull_up_1v8); 604 if (err) 605 autocal->pull_up_1v8 = 0; 606 607 err = device_property_read_u32(mmc_dev(host->mmc), 608 "nvidia,pad-autocal-pull-down-offset-1v8", 609 &autocal->pull_down_1v8); 610 if (err) 611 autocal->pull_down_1v8 = 0; 612 613 err = device_property_read_u32(mmc_dev(host->mmc), 614 "nvidia,pad-autocal-pull-up-offset-sdr104", 615 &autocal->pull_up_sdr104); 616 if (err) 617 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 618 619 err = device_property_read_u32(mmc_dev(host->mmc), 620 "nvidia,pad-autocal-pull-down-offset-sdr104", 621 &autocal->pull_down_sdr104); 622 if (err) 623 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 624 625 err = device_property_read_u32(mmc_dev(host->mmc), 626 "nvidia,pad-autocal-pull-up-offset-hs400", 627 &autocal->pull_up_hs400); 628 if (err) 629 autocal->pull_up_hs400 = autocal->pull_up_1v8; 630 631 err = device_property_read_u32(mmc_dev(host->mmc), 632 "nvidia,pad-autocal-pull-down-offset-hs400", 633 &autocal->pull_down_hs400); 634 if (err) 635 autocal->pull_down_hs400 = autocal->pull_down_1v8; 636 637 /* 638 * Different fail-safe drive strength values based on the signaling 639 * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. 640 * So, avoid reading below device tree properties for SoCs that don't 641 * have NVQUIRK_NEEDS_PAD_CONTROL. 642 */ 643 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 644 return; 645 646 err = device_property_read_u32(mmc_dev(host->mmc), 647 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 648 &autocal->pull_up_3v3_timeout); 649 if (err) { 650 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 651 (tegra_host->pinctrl_state_3v3_drv == NULL)) 652 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 653 mmc_hostname(host->mmc)); 654 autocal->pull_up_3v3_timeout = 0; 655 } 656 657 err = device_property_read_u32(mmc_dev(host->mmc), 658 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 659 &autocal->pull_down_3v3_timeout); 660 if (err) { 661 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 662 (tegra_host->pinctrl_state_3v3_drv == NULL)) 663 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 664 mmc_hostname(host->mmc)); 665 autocal->pull_down_3v3_timeout = 0; 666 } 667 668 err = device_property_read_u32(mmc_dev(host->mmc), 669 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 670 &autocal->pull_up_1v8_timeout); 671 if (err) { 672 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 673 (tegra_host->pinctrl_state_1v8_drv == NULL)) 674 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 675 mmc_hostname(host->mmc)); 676 autocal->pull_up_1v8_timeout = 0; 677 } 678 679 err = device_property_read_u32(mmc_dev(host->mmc), 680 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 681 &autocal->pull_down_1v8_timeout); 682 if (err) { 683 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 684 (tegra_host->pinctrl_state_1v8_drv == NULL)) 685 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 686 mmc_hostname(host->mmc)); 687 autocal->pull_down_1v8_timeout = 0; 688 } 689 } 690 691 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 692 { 693 struct sdhci_host *host = mmc_priv(mmc); 694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 695 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 696 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 697 698 /* 100 ms calibration interval is specified in the TRM */ 699 if (ktime_to_ms(since_calib) > 100) { 700 tegra_sdhci_pad_autocalib(host); 701 tegra_host->last_calib = ktime_get(); 702 } 703 704 sdhci_request(mmc, mrq); 705 } 706 707 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 708 { 709 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 710 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 711 int err; 712 713 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", 714 &tegra_host->default_tap); 715 if (err) 716 tegra_host->default_tap = 0; 717 718 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", 719 &tegra_host->default_trim); 720 if (err) 721 tegra_host->default_trim = 0; 722 723 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", 724 &tegra_host->dqs_trim); 725 if (err) 726 tegra_host->dqs_trim = 0x11; 727 } 728 729 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 730 { 731 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 732 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 733 734 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) 735 tegra_host->enable_hwcq = true; 736 else 737 tegra_host->enable_hwcq = false; 738 739 tegra_sdhci_parse_pad_autocal_dt(host); 740 tegra_sdhci_parse_tap_and_trim(host); 741 } 742 743 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 744 { 745 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 746 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 747 struct device *dev = mmc_dev(host->mmc); 748 unsigned long host_clk; 749 int err; 750 751 if (!clock) 752 return sdhci_set_clock(host, clock); 753 754 /* 755 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 756 * divider to be configured to divided the host clock by two. The SDHCI 757 * clock divider is calculated as part of sdhci_set_clock() by 758 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 759 * the requested clock rate. 760 * 761 * By setting the host->max_clk to clock * 2 the divider calculation 762 * will always result in the correct value for DDR50/52 modes, 763 * regardless of clock rate rounding, which may happen if the value 764 * from clk_get_rate() is used. 765 */ 766 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 767 768 err = dev_pm_opp_set_rate(dev, host_clk); 769 if (err) 770 dev_err(dev, "failed to set clk rate to %luHz: %d\n", 771 host_clk, err); 772 773 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); 774 if (tegra_host->ddr_signaling) 775 host->max_clk = host_clk; 776 else 777 host->max_clk = clk_get_rate(pltfm_host->clk); 778 779 sdhci_set_clock(host, clock); 780 781 if (tegra_host->pad_calib_required) { 782 tegra_sdhci_pad_autocalib(host); 783 tegra_host->pad_calib_required = false; 784 } 785 } 786 787 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 788 struct mmc_ios *ios) 789 { 790 struct sdhci_host *host = mmc_priv(mmc); 791 u32 val; 792 793 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 794 795 if (ios->enhanced_strobe) { 796 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 797 /* 798 * When CMD13 is sent from mmc_select_hs400es() after 799 * switching to HS400ES mode, the bus is operating at 800 * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. 801 * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI 802 * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host 803 * controller CAR clock and the interface clock are rate matched. 804 */ 805 tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); 806 } else { 807 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 808 } 809 810 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 811 } 812 813 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 814 { 815 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 816 817 return clk_round_rate(pltfm_host->clk, UINT_MAX); 818 } 819 820 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 821 { 822 u32 val; 823 824 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 825 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 826 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 827 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 828 } 829 830 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 831 { 832 u32 reg; 833 int err; 834 835 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 836 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 837 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 838 839 /* 1 ms sleep, 5 ms timeout */ 840 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 841 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 842 1000, 5000); 843 if (err) 844 dev_err(mmc_dev(host->mmc), 845 "HS400 delay line calibration timed out\n"); 846 } 847 848 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 849 u8 thd_low, u8 fixed_tap) 850 { 851 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 852 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 853 u32 val, tun_status; 854 u8 word, bit, edge1, tap, window; 855 bool tap_result; 856 bool start_fail = false; 857 bool start_pass = false; 858 bool end_pass = false; 859 bool first_fail = false; 860 bool first_pass = false; 861 u8 start_pass_tap = 0; 862 u8 end_pass_tap = 0; 863 u8 first_fail_tap = 0; 864 u8 first_pass_tap = 0; 865 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 866 867 /* 868 * Read auto-tuned results and extract good valid passing window by 869 * filtering out un-wanted bubble/partial/merged windows. 870 */ 871 for (word = 0; word < total_tuning_words; word++) { 872 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 873 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 874 val |= word; 875 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 876 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 877 bit = 0; 878 while (bit < TUNING_WORD_BIT_SIZE) { 879 tap = word * TUNING_WORD_BIT_SIZE + bit; 880 tap_result = tun_status & (1 << bit); 881 if (!tap_result && !start_fail) { 882 start_fail = true; 883 if (!first_fail) { 884 first_fail_tap = tap; 885 first_fail = true; 886 } 887 888 } else if (tap_result && start_fail && !start_pass) { 889 start_pass_tap = tap; 890 start_pass = true; 891 if (!first_pass) { 892 first_pass_tap = tap; 893 first_pass = true; 894 } 895 896 } else if (!tap_result && start_fail && start_pass && 897 !end_pass) { 898 end_pass_tap = tap - 1; 899 end_pass = true; 900 } else if (tap_result && start_pass && start_fail && 901 end_pass) { 902 window = end_pass_tap - start_pass_tap; 903 /* discard merged window and bubble window */ 904 if (window >= thd_up || window < thd_low) { 905 start_pass_tap = tap; 906 end_pass = false; 907 } else { 908 /* set tap at middle of valid window */ 909 tap = start_pass_tap + window / 2; 910 tegra_host->tuned_tap_delay = tap; 911 return; 912 } 913 } 914 915 bit++; 916 } 917 } 918 919 if (!first_fail) { 920 WARN(1, "no edge detected, continue with hw tuned delay.\n"); 921 } else if (first_pass) { 922 /* set tap location at fixed tap relative to the first edge */ 923 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 924 if (edge1 - 1 > fixed_tap) 925 tegra_host->tuned_tap_delay = edge1 - fixed_tap; 926 else 927 tegra_host->tuned_tap_delay = edge1 + fixed_tap; 928 } 929 } 930 931 static void tegra_sdhci_post_tuning(struct sdhci_host *host) 932 { 933 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 934 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 935 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 936 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 937 u8 fixed_tap, start_tap, end_tap, window_width; 938 u8 thdupper, thdlower; 939 u8 num_iter; 940 u32 clk_rate_mhz, period_ps, bestcase, worstcase; 941 942 /* retain HW tuned tap to use incase if no correction is needed */ 943 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 944 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 945 SDHCI_CLOCK_CTRL_TAP_SHIFT; 946 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 947 min_tap_dly = soc_data->min_tap_delay; 948 max_tap_dly = soc_data->max_tap_delay; 949 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 950 period_ps = USEC_PER_SEC / clk_rate_mhz; 951 bestcase = period_ps / min_tap_dly; 952 worstcase = period_ps / max_tap_dly; 953 /* 954 * Upper and Lower bound thresholds used to detect merged and 955 * bubble windows 956 */ 957 thdupper = (2 * worstcase + bestcase) / 2; 958 thdlower = worstcase / 4; 959 /* 960 * fixed tap is used when HW tuning result contains single edge 961 * and tap is set at fixed tap delay relative to the first edge 962 */ 963 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 964 fixed_tap = avg_tap_dly / 2; 965 966 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 967 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 968 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 969 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 970 window_width = end_tap - start_tap; 971 num_iter = host->tuning_loop_count; 972 /* 973 * partial window includes edges of the tuning range. 974 * merged window includes more taps so window width is higher 975 * than upper threshold. 976 */ 977 if (start_tap == 0 || (end_tap == (num_iter - 1)) || 978 (end_tap == num_iter - 2) || window_width >= thdupper) { 979 pr_debug("%s: Apply tuning correction\n", 980 mmc_hostname(host->mmc)); 981 tegra_sdhci_tap_correction(host, thdupper, thdlower, 982 fixed_tap); 983 } 984 } 985 986 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 987 } 988 989 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 990 { 991 struct sdhci_host *host = mmc_priv(mmc); 992 int err; 993 994 err = sdhci_execute_tuning(mmc, opcode); 995 if (!err && !host->tuning_err) 996 tegra_sdhci_post_tuning(host); 997 998 return err; 999 } 1000 1001 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 1002 unsigned timing) 1003 { 1004 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1005 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1006 bool set_default_tap = false; 1007 bool set_dqs_trim = false; 1008 bool do_hs400_dll_cal = false; 1009 u8 iter = TRIES_256; 1010 u32 val; 1011 1012 tegra_host->ddr_signaling = false; 1013 switch (timing) { 1014 case MMC_TIMING_UHS_SDR50: 1015 break; 1016 case MMC_TIMING_UHS_SDR104: 1017 case MMC_TIMING_MMC_HS200: 1018 /* Don't set default tap on tunable modes. */ 1019 iter = TRIES_128; 1020 break; 1021 case MMC_TIMING_MMC_HS400: 1022 set_dqs_trim = true; 1023 do_hs400_dll_cal = true; 1024 iter = TRIES_128; 1025 break; 1026 case MMC_TIMING_MMC_DDR52: 1027 case MMC_TIMING_UHS_DDR50: 1028 tegra_host->ddr_signaling = true; 1029 set_default_tap = true; 1030 break; 1031 default: 1032 set_default_tap = true; 1033 break; 1034 } 1035 1036 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 1037 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 1038 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 1039 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 1040 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 1041 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 1042 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 1043 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 1044 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 1045 1046 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 1047 1048 sdhci_set_uhs_signaling(host, timing); 1049 1050 tegra_sdhci_pad_autocalib(host); 1051 1052 if (tegra_host->tuned_tap_delay && !set_default_tap) 1053 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1054 else 1055 tegra_sdhci_set_tap(host, tegra_host->default_tap); 1056 1057 if (set_dqs_trim) 1058 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1059 1060 if (do_hs400_dll_cal) 1061 tegra_sdhci_hs400_dll_cal(host); 1062 } 1063 1064 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1065 { 1066 unsigned int min, max; 1067 1068 /* 1069 * Start search for minimum tap value at 10, as smaller values are 1070 * may wrongly be reported as working but fail at higher speeds, 1071 * according to the TRM. 1072 */ 1073 min = 10; 1074 while (min < 255) { 1075 tegra_sdhci_set_tap(host, min); 1076 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1077 break; 1078 min++; 1079 } 1080 1081 /* Find the maximum tap value that still passes. */ 1082 max = min + 1; 1083 while (max < 255) { 1084 tegra_sdhci_set_tap(host, max); 1085 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1086 max--; 1087 break; 1088 } 1089 max++; 1090 } 1091 1092 /* The TRM states the ideal tap value is at 75% in the passing range. */ 1093 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1094 1095 return mmc_send_tuning(host->mmc, opcode, NULL); 1096 } 1097 1098 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 1099 struct mmc_ios *ios) 1100 { 1101 struct sdhci_host *host = mmc_priv(mmc); 1102 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1103 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1104 int ret = 0; 1105 1106 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1107 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1108 if (ret < 0) 1109 return ret; 1110 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1111 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 1112 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1113 if (ret < 0) 1114 return ret; 1115 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1116 } 1117 1118 if (tegra_host->pad_calib_required) 1119 tegra_sdhci_pad_autocalib(host); 1120 1121 return ret; 1122 } 1123 1124 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 1125 struct sdhci_tegra *tegra_host) 1126 { 1127 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 1128 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 1129 dev_dbg(dev, "No pinctrl info, err: %ld\n", 1130 PTR_ERR(tegra_host->pinctrl_sdmmc)); 1131 return -1; 1132 } 1133 1134 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1135 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1136 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1137 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1138 tegra_host->pinctrl_state_1v8_drv = NULL; 1139 } 1140 1141 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1142 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1143 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1144 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1145 tegra_host->pinctrl_state_3v3_drv = NULL; 1146 } 1147 1148 tegra_host->pinctrl_state_3v3 = 1149 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 1150 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 1151 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 1152 PTR_ERR(tegra_host->pinctrl_state_3v3)); 1153 return -1; 1154 } 1155 1156 tegra_host->pinctrl_state_1v8 = 1157 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 1158 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 1159 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1160 PTR_ERR(tegra_host->pinctrl_state_1v8)); 1161 return -1; 1162 } 1163 1164 tegra_host->pad_control_available = true; 1165 1166 return 0; 1167 } 1168 1169 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1170 { 1171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1172 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1173 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1174 1175 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1176 tegra_host->pad_calib_required = true; 1177 } 1178 1179 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1180 { 1181 struct mmc_host *mmc = cq_host->mmc; 1182 struct sdhci_host *host = mmc_priv(mmc); 1183 u8 ctrl; 1184 ktime_t timeout; 1185 bool timed_out; 1186 1187 /* 1188 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1189 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1190 * to be re-configured. 1191 * Tegra CQHCI/SDHCI prevents write access to block size register when 1192 * CQE is unhalted. So handling CQE resume sequence here to configure 1193 * SDHCI block registers prior to exiting CQE halt state. 1194 */ 1195 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1196 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 1197 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1198 sdhci_cqe_enable(mmc); 1199 writel(val, cq_host->mmio + reg); 1200 timeout = ktime_add_us(ktime_get(), 50); 1201 while (1) { 1202 timed_out = ktime_compare(ktime_get(), timeout) > 0; 1203 ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1204 if (!(ctrl & CQHCI_HALT) || timed_out) 1205 break; 1206 } 1207 /* 1208 * CQE usually resumes very quick, but incase if Tegra CQE 1209 * doesn't resume retry unhalt. 1210 */ 1211 if (timed_out) 1212 writel(val, cq_host->mmio + reg); 1213 } else { 1214 writel(val, cq_host->mmio + reg); 1215 } 1216 } 1217 1218 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1219 struct mmc_request *mrq, u64 *data) 1220 { 1221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1222 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1223 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1224 1225 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1226 mrq->cmd->flags & MMC_RSP_R1B) 1227 *data |= CQHCI_CMD_TIMING(1); 1228 } 1229 1230 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 1231 { 1232 struct cqhci_host *cq_host = mmc->cqe_private; 1233 struct sdhci_host *host = mmc_priv(mmc); 1234 u32 val; 1235 1236 /* 1237 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1238 * register when CQE is enabled and unhalted. 1239 * CQHCI driver enables CQE prior to activation, so disable CQE before 1240 * programming block size in sdhci controller and enable it back. 1241 */ 1242 if (!cq_host->activated) { 1243 val = cqhci_readl(cq_host, CQHCI_CFG); 1244 if (val & CQHCI_ENABLE) 1245 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1246 CQHCI_CFG); 1247 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1248 sdhci_cqe_enable(mmc); 1249 if (val & CQHCI_ENABLE) 1250 cqhci_writel(cq_host, val, CQHCI_CFG); 1251 } 1252 1253 /* 1254 * CMD CRC errors are seen sometimes with some eMMC devices when status 1255 * command is sent during transfer of last data block which is the 1256 * default case as send status command block counter (CBC) is 1. 1257 * Recommended fix to set CBC to 0 allowing send status command only 1258 * when data lines are idle. 1259 */ 1260 val = cqhci_readl(cq_host, CQHCI_SSC1); 1261 val &= ~CQHCI_SSC1_CBC_MASK; 1262 cqhci_writel(cq_host, val, CQHCI_SSC1); 1263 } 1264 1265 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 1266 { 1267 sdhci_dumpregs(mmc_priv(mmc)); 1268 } 1269 1270 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 1271 { 1272 int cmd_error = 0; 1273 int data_error = 0; 1274 1275 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1276 return intmask; 1277 1278 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1279 1280 return 0; 1281 } 1282 1283 static void tegra_sdhci_set_timeout(struct sdhci_host *host, 1284 struct mmc_command *cmd) 1285 { 1286 u32 val; 1287 1288 /* 1289 * HW busy detection timeout is based on programmed data timeout 1290 * counter and maximum supported timeout is 11s which may not be 1291 * enough for long operations like cache flush, sleep awake, erase. 1292 * 1293 * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 1294 * host controller to wait for busy state until the card is busy 1295 * without HW timeout. 1296 * 1297 * So, use infinite busy wait mode for operations that may take 1298 * more than maximum HW busy timeout of 11s otherwise use finite 1299 * busy wait mode. 1300 */ 1301 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1302 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) 1303 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1304 else 1305 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1306 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1307 1308 __sdhci_set_timeout(host, cmd); 1309 } 1310 1311 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc) 1312 { 1313 struct cqhci_host *cq_host = mmc->cqe_private; 1314 u32 reg; 1315 1316 reg = cqhci_readl(cq_host, CQHCI_CFG); 1317 reg |= CQHCI_ENABLE; 1318 cqhci_writel(cq_host, reg, CQHCI_CFG); 1319 } 1320 1321 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc) 1322 { 1323 struct cqhci_host *cq_host = mmc->cqe_private; 1324 struct sdhci_host *host = mmc_priv(mmc); 1325 u32 reg; 1326 1327 reg = cqhci_readl(cq_host, CQHCI_CFG); 1328 reg &= ~CQHCI_ENABLE; 1329 cqhci_writel(cq_host, reg, CQHCI_CFG); 1330 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1331 } 1332 1333 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1334 .write_l = tegra_cqhci_writel, 1335 .enable = sdhci_tegra_cqe_enable, 1336 .disable = sdhci_cqe_disable, 1337 .dumpregs = sdhci_tegra_dumpregs, 1338 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 1339 .pre_enable = sdhci_tegra_cqe_pre_enable, 1340 .post_disable = sdhci_tegra_cqe_post_disable, 1341 }; 1342 1343 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1344 { 1345 struct sdhci_pltfm_host *platform = sdhci_priv(host); 1346 struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1347 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1348 struct device *dev = mmc_dev(host->mmc); 1349 1350 if (soc->dma_mask) 1351 return dma_set_mask_and_coherent(dev, soc->dma_mask); 1352 1353 return 0; 1354 } 1355 1356 static const struct sdhci_ops tegra_sdhci_ops = { 1357 .get_ro = tegra_sdhci_get_ro, 1358 .read_w = tegra_sdhci_readw, 1359 .write_l = tegra_sdhci_writel, 1360 .set_clock = tegra_sdhci_set_clock, 1361 .set_dma_mask = tegra_sdhci_set_dma_mask, 1362 .set_bus_width = sdhci_set_bus_width, 1363 .reset = tegra_sdhci_reset, 1364 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1365 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1366 .voltage_switch = tegra_sdhci_voltage_switch, 1367 .get_max_clock = tegra_sdhci_get_max_clock, 1368 }; 1369 1370 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 1371 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1372 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1373 SDHCI_QUIRK_NO_HISPD_BIT | 1374 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1375 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1376 .ops = &tegra_sdhci_ops, 1377 }; 1378 1379 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1380 .pdata = &sdhci_tegra20_pdata, 1381 .dma_mask = DMA_BIT_MASK(32), 1382 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1383 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1384 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1385 }; 1386 1387 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1388 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1389 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1390 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1391 SDHCI_QUIRK_NO_HISPD_BIT | 1392 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1393 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1394 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1395 SDHCI_QUIRK2_BROKEN_HS200 | 1396 /* 1397 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1398 * though no command operation was in progress." 1399 * 1400 * The exact reason is unknown, as the same hardware seems 1401 * to support Auto CMD23 on a downstream 3.1 kernel. 1402 */ 1403 SDHCI_QUIRK2_ACMD23_BROKEN, 1404 .ops = &tegra_sdhci_ops, 1405 }; 1406 1407 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1408 .pdata = &sdhci_tegra30_pdata, 1409 .dma_mask = DMA_BIT_MASK(32), 1410 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1411 NVQUIRK_ENABLE_SDR50 | 1412 NVQUIRK_ENABLE_SDR104 | 1413 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1414 NVQUIRK_HAS_PADCALIB, 1415 }; 1416 1417 static const struct sdhci_ops tegra114_sdhci_ops = { 1418 .get_ro = tegra_sdhci_get_ro, 1419 .read_w = tegra_sdhci_readw, 1420 .write_w = tegra_sdhci_writew, 1421 .write_l = tegra_sdhci_writel, 1422 .set_clock = tegra_sdhci_set_clock, 1423 .set_dma_mask = tegra_sdhci_set_dma_mask, 1424 .set_bus_width = sdhci_set_bus_width, 1425 .reset = tegra_sdhci_reset, 1426 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1427 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1428 .voltage_switch = tegra_sdhci_voltage_switch, 1429 .get_max_clock = tegra_sdhci_get_max_clock, 1430 }; 1431 1432 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1433 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1434 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1435 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1436 SDHCI_QUIRK_NO_HISPD_BIT | 1437 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1438 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1439 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1440 .ops = &tegra114_sdhci_ops, 1441 }; 1442 1443 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1444 .pdata = &sdhci_tegra114_pdata, 1445 .dma_mask = DMA_BIT_MASK(32), 1446 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1447 }; 1448 1449 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1450 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1451 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1452 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1453 SDHCI_QUIRK_NO_HISPD_BIT | 1454 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1455 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1456 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1457 .ops = &tegra114_sdhci_ops, 1458 }; 1459 1460 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1461 .pdata = &sdhci_tegra124_pdata, 1462 .dma_mask = DMA_BIT_MASK(34), 1463 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1464 }; 1465 1466 static const struct sdhci_ops tegra210_sdhci_ops = { 1467 .get_ro = tegra_sdhci_get_ro, 1468 .read_w = tegra_sdhci_readw, 1469 .write_w = tegra210_sdhci_writew, 1470 .write_l = tegra_sdhci_writel, 1471 .set_clock = tegra_sdhci_set_clock, 1472 .set_dma_mask = tegra_sdhci_set_dma_mask, 1473 .set_bus_width = sdhci_set_bus_width, 1474 .reset = tegra_sdhci_reset, 1475 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1476 .voltage_switch = tegra_sdhci_voltage_switch, 1477 .get_max_clock = tegra_sdhci_get_max_clock, 1478 .set_timeout = tegra_sdhci_set_timeout, 1479 }; 1480 1481 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1482 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1483 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1484 SDHCI_QUIRK_NO_HISPD_BIT | 1485 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1486 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1487 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1488 .ops = &tegra210_sdhci_ops, 1489 }; 1490 1491 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1492 .pdata = &sdhci_tegra210_pdata, 1493 .dma_mask = DMA_BIT_MASK(34), 1494 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1495 NVQUIRK_HAS_PADCALIB | 1496 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1497 NVQUIRK_ENABLE_SDR50 | 1498 NVQUIRK_ENABLE_SDR104 | 1499 NVQUIRK_HAS_TMCLK, 1500 .min_tap_delay = 106, 1501 .max_tap_delay = 185, 1502 }; 1503 1504 static const struct sdhci_ops tegra186_sdhci_ops = { 1505 .get_ro = tegra_sdhci_get_ro, 1506 .read_w = tegra_sdhci_readw, 1507 .write_l = tegra_sdhci_writel, 1508 .set_clock = tegra_sdhci_set_clock, 1509 .set_dma_mask = tegra_sdhci_set_dma_mask, 1510 .set_bus_width = sdhci_set_bus_width, 1511 .reset = tegra_sdhci_reset, 1512 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1513 .voltage_switch = tegra_sdhci_voltage_switch, 1514 .get_max_clock = tegra_sdhci_get_max_clock, 1515 .irq = sdhci_tegra_cqhci_irq, 1516 .set_timeout = tegra_sdhci_set_timeout, 1517 }; 1518 1519 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1520 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1521 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1522 SDHCI_QUIRK_NO_HISPD_BIT | 1523 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1524 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1525 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1526 .ops = &tegra186_sdhci_ops, 1527 }; 1528 1529 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1530 .pdata = &sdhci_tegra186_pdata, 1531 .dma_mask = DMA_BIT_MASK(40), 1532 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1533 NVQUIRK_HAS_PADCALIB | 1534 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1535 NVQUIRK_ENABLE_SDR50 | 1536 NVQUIRK_ENABLE_SDR104 | 1537 NVQUIRK_HAS_TMCLK | 1538 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1539 .min_tap_delay = 84, 1540 .max_tap_delay = 136, 1541 }; 1542 1543 static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1544 .pdata = &sdhci_tegra186_pdata, 1545 .dma_mask = DMA_BIT_MASK(39), 1546 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1547 NVQUIRK_HAS_PADCALIB | 1548 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1549 NVQUIRK_ENABLE_SDR50 | 1550 NVQUIRK_ENABLE_SDR104 | 1551 NVQUIRK_HAS_TMCLK, 1552 .min_tap_delay = 96, 1553 .max_tap_delay = 139, 1554 }; 1555 1556 static const struct of_device_id sdhci_tegra_dt_match[] = { 1557 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1558 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1559 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1560 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1561 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1562 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1563 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1564 {} 1565 }; 1566 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1567 1568 static int sdhci_tegra_add_host(struct sdhci_host *host) 1569 { 1570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1571 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1572 struct cqhci_host *cq_host; 1573 bool dma64; 1574 int ret; 1575 1576 if (!tegra_host->enable_hwcq) 1577 return sdhci_add_host(host); 1578 1579 sdhci_enable_v4_mode(host); 1580 1581 ret = sdhci_setup_host(host); 1582 if (ret) 1583 return ret; 1584 1585 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1586 1587 cq_host = devm_kzalloc(mmc_dev(host->mmc), 1588 sizeof(*cq_host), GFP_KERNEL); 1589 if (!cq_host) { 1590 ret = -ENOMEM; 1591 goto cleanup; 1592 } 1593 1594 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1595 cq_host->ops = &sdhci_tegra_cqhci_ops; 1596 1597 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1598 if (dma64) 1599 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1600 1601 ret = cqhci_init(cq_host, host->mmc, dma64); 1602 if (ret) 1603 goto cleanup; 1604 1605 ret = __sdhci_add_host(host); 1606 if (ret) 1607 goto cleanup; 1608 1609 return 0; 1610 1611 cleanup: 1612 sdhci_cleanup_host(host); 1613 return ret; 1614 } 1615 1616 static int sdhci_tegra_probe(struct platform_device *pdev) 1617 { 1618 const struct sdhci_tegra_soc_data *soc_data; 1619 struct sdhci_host *host; 1620 struct sdhci_pltfm_host *pltfm_host; 1621 struct sdhci_tegra *tegra_host; 1622 struct clk *clk; 1623 int rc; 1624 1625 soc_data = of_device_get_match_data(&pdev->dev); 1626 if (!soc_data) 1627 return -EINVAL; 1628 1629 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1630 if (IS_ERR(host)) 1631 return PTR_ERR(host); 1632 pltfm_host = sdhci_priv(host); 1633 1634 tegra_host = sdhci_pltfm_priv(pltfm_host); 1635 tegra_host->ddr_signaling = false; 1636 tegra_host->pad_calib_required = false; 1637 tegra_host->pad_control_available = false; 1638 tegra_host->soc_data = soc_data; 1639 1640 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) 1641 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; 1642 1643 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1644 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1645 if (rc == 0) 1646 host->mmc_host_ops.start_signal_voltage_switch = 1647 sdhci_tegra_start_signal_voltage_switch; 1648 } 1649 1650 /* Hook to periodically rerun pad calibration */ 1651 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1652 host->mmc_host_ops.request = tegra_sdhci_request; 1653 1654 host->mmc_host_ops.hs400_enhanced_strobe = 1655 tegra_sdhci_hs400_enhanced_strobe; 1656 1657 if (!host->ops->platform_execute_tuning) 1658 host->mmc_host_ops.execute_tuning = 1659 tegra_sdhci_execute_hw_tuning; 1660 1661 rc = mmc_of_parse(host->mmc); 1662 if (rc) 1663 goto err_parse_dt; 1664 1665 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1666 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1667 1668 /* HW busy detection is supported, but R1B responses are required. */ 1669 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1670 1671 /* GPIO CD can be set as a wakeup source */ 1672 host->mmc->caps |= MMC_CAP_CD_WAKE; 1673 1674 tegra_sdhci_parse_dt(host); 1675 1676 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1677 GPIOD_OUT_HIGH); 1678 if (IS_ERR(tegra_host->power_gpio)) { 1679 rc = PTR_ERR(tegra_host->power_gpio); 1680 goto err_power_req; 1681 } 1682 1683 /* 1684 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host 1685 * timeout clock and SW can choose TMCLK or SDCLK for hardware 1686 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of 1687 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL. 1688 * 1689 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses 1690 * 12Mhz TMCLK which is advertised in host capability register. 1691 * With TMCLK of 12Mhz provides maximum data timeout period that can 1692 * be achieved is 11s better than using SDCLK for data timeout. 1693 * 1694 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's 1695 * supporting separate TMCLK. 1696 */ 1697 1698 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { 1699 clk = devm_clk_get(&pdev->dev, "tmclk"); 1700 if (IS_ERR(clk)) { 1701 rc = PTR_ERR(clk); 1702 if (rc == -EPROBE_DEFER) 1703 goto err_power_req; 1704 1705 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 1706 clk = NULL; 1707 } 1708 1709 clk_set_rate(clk, 12000000); 1710 rc = clk_prepare_enable(clk); 1711 if (rc) { 1712 dev_err(&pdev->dev, 1713 "failed to enable tmclk: %d\n", rc); 1714 goto err_power_req; 1715 } 1716 1717 tegra_host->tmclk = clk; 1718 } 1719 1720 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1721 if (IS_ERR(clk)) { 1722 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), 1723 "failed to get clock\n"); 1724 goto err_clk_get; 1725 } 1726 pltfm_host->clk = clk; 1727 1728 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1729 "sdhci"); 1730 if (IS_ERR(tegra_host->rst)) { 1731 rc = PTR_ERR(tegra_host->rst); 1732 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1733 goto err_rst_get; 1734 } 1735 1736 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1737 if (rc) 1738 goto err_rst_get; 1739 1740 pm_runtime_enable(&pdev->dev); 1741 rc = pm_runtime_resume_and_get(&pdev->dev); 1742 if (rc) 1743 goto err_pm_get; 1744 1745 rc = reset_control_assert(tegra_host->rst); 1746 if (rc) 1747 goto err_rst_assert; 1748 1749 usleep_range(2000, 4000); 1750 1751 rc = reset_control_deassert(tegra_host->rst); 1752 if (rc) 1753 goto err_rst_assert; 1754 1755 usleep_range(2000, 4000); 1756 1757 rc = sdhci_tegra_add_host(host); 1758 if (rc) 1759 goto err_add_host; 1760 1761 return 0; 1762 1763 err_add_host: 1764 reset_control_assert(tegra_host->rst); 1765 err_rst_assert: 1766 pm_runtime_put_sync_suspend(&pdev->dev); 1767 err_pm_get: 1768 pm_runtime_disable(&pdev->dev); 1769 err_rst_get: 1770 err_clk_get: 1771 clk_disable_unprepare(tegra_host->tmclk); 1772 err_power_req: 1773 err_parse_dt: 1774 sdhci_pltfm_free(pdev); 1775 return rc; 1776 } 1777 1778 static int sdhci_tegra_remove(struct platform_device *pdev) 1779 { 1780 struct sdhci_host *host = platform_get_drvdata(pdev); 1781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1782 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1783 1784 sdhci_remove_host(host, 0); 1785 1786 reset_control_assert(tegra_host->rst); 1787 usleep_range(2000, 4000); 1788 1789 pm_runtime_put_sync_suspend(&pdev->dev); 1790 pm_runtime_force_suspend(&pdev->dev); 1791 1792 clk_disable_unprepare(tegra_host->tmclk); 1793 sdhci_pltfm_free(pdev); 1794 1795 return 0; 1796 } 1797 1798 static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev) 1799 { 1800 struct sdhci_host *host = dev_get_drvdata(dev); 1801 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1802 1803 clk_disable_unprepare(pltfm_host->clk); 1804 1805 return 0; 1806 } 1807 1808 static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev) 1809 { 1810 struct sdhci_host *host = dev_get_drvdata(dev); 1811 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1812 1813 return clk_prepare_enable(pltfm_host->clk); 1814 } 1815 1816 #ifdef CONFIG_PM_SLEEP 1817 static int sdhci_tegra_suspend(struct device *dev) 1818 { 1819 struct sdhci_host *host = dev_get_drvdata(dev); 1820 int ret; 1821 1822 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1823 ret = cqhci_suspend(host->mmc); 1824 if (ret) 1825 return ret; 1826 } 1827 1828 ret = sdhci_suspend_host(host); 1829 if (ret) { 1830 cqhci_resume(host->mmc); 1831 return ret; 1832 } 1833 1834 ret = pm_runtime_force_suspend(dev); 1835 if (ret) { 1836 sdhci_resume_host(host); 1837 cqhci_resume(host->mmc); 1838 return ret; 1839 } 1840 1841 return mmc_gpio_set_cd_wake(host->mmc, true); 1842 } 1843 1844 static int sdhci_tegra_resume(struct device *dev) 1845 { 1846 struct sdhci_host *host = dev_get_drvdata(dev); 1847 int ret; 1848 1849 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1850 if (ret) 1851 return ret; 1852 1853 ret = pm_runtime_force_resume(dev); 1854 if (ret) 1855 return ret; 1856 1857 ret = sdhci_resume_host(host); 1858 if (ret) 1859 goto disable_clk; 1860 1861 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1862 ret = cqhci_resume(host->mmc); 1863 if (ret) 1864 goto suspend_host; 1865 } 1866 1867 return 0; 1868 1869 suspend_host: 1870 sdhci_suspend_host(host); 1871 disable_clk: 1872 pm_runtime_force_suspend(dev); 1873 return ret; 1874 } 1875 #endif 1876 1877 static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = { 1878 SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume, 1879 NULL) 1880 SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume) 1881 }; 1882 1883 static struct platform_driver sdhci_tegra_driver = { 1884 .driver = { 1885 .name = "sdhci-tegra", 1886 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1887 .of_match_table = sdhci_tegra_dt_match, 1888 .pm = &sdhci_tegra_dev_pm_ops, 1889 }, 1890 .probe = sdhci_tegra_probe, 1891 .remove = sdhci_tegra_remove, 1892 }; 1893 1894 module_platform_driver(sdhci_tegra_driver); 1895 1896 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1897 MODULE_AUTHOR("Google, Inc."); 1898 MODULE_LICENSE("GPL v2"); 1899