103d2bfc8SOlof Johansson /* 203d2bfc8SOlof Johansson * Copyright (C) 2010 Google, Inc. 303d2bfc8SOlof Johansson * 403d2bfc8SOlof Johansson * This software is licensed under the terms of the GNU General Public 503d2bfc8SOlof Johansson * License version 2, as published by the Free Software Foundation, and 603d2bfc8SOlof Johansson * may be copied, distributed, and modified under those terms. 703d2bfc8SOlof Johansson * 803d2bfc8SOlof Johansson * This program is distributed in the hope that it will be useful, 903d2bfc8SOlof Johansson * but WITHOUT ANY WARRANTY; without even the implied warranty of 1003d2bfc8SOlof Johansson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1103d2bfc8SOlof Johansson * GNU General Public License for more details. 1203d2bfc8SOlof Johansson * 1303d2bfc8SOlof Johansson */ 1403d2bfc8SOlof Johansson 15e5c63d91SLucas Stach #include <linux/delay.h> 1603d2bfc8SOlof Johansson #include <linux/err.h> 1796547f5dSPaul Gortmaker #include <linux/module.h> 1803d2bfc8SOlof Johansson #include <linux/init.h> 19e7c07148SAapo Vienamo #include <linux/iopoll.h> 2003d2bfc8SOlof Johansson #include <linux/platform_device.h> 2103d2bfc8SOlof Johansson #include <linux/clk.h> 2203d2bfc8SOlof Johansson #include <linux/io.h> 2355cd65e4SStephen Warren #include <linux/of.h> 243e44a1a7SStephen Warren #include <linux/of_device.h> 2586ac2f8bSAapo Vienamo #include <linux/pinctrl/consumer.h> 2686ac2f8bSAapo Vienamo #include <linux/regulator/consumer.h> 2720567be9SThierry Reding #include <linux/reset.h> 2803d2bfc8SOlof Johansson #include <linux/mmc/card.h> 2903d2bfc8SOlof Johansson #include <linux/mmc/host.h> 30c3c2384cSLucas Stach #include <linux/mmc/mmc.h> 310aacd23fSJoseph Lo #include <linux/mmc/slot-gpio.h> 322391b340SMylene JOSSERAND #include <linux/gpio/consumer.h> 3303d2bfc8SOlof Johansson 3403d2bfc8SOlof Johansson #include "sdhci-pltfm.h" 3503d2bfc8SOlof Johansson 36ca5879d3SPavan Kunapuli /* Tegra SDHOST controller vendor register definitions */ 3774cd42bcSLucas Stach #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 4174cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 4274cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 4374cd42bcSLucas Stach 44ca5879d3SPavan Kunapuli #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 453145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 463145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47ca5879d3SPavan Kunapuli #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 483145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49ca5879d3SPavan Kunapuli 50e5c63d91SLucas Stach #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 51e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_START BIT(31) 52e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_ENABLE BIT(29) 53e5c63d91SLucas Stach 54e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 55e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 56e7c07148SAapo Vienamo 573e44a1a7SStephen Warren #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 583e44a1a7SStephen Warren #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 59ca5879d3SPavan Kunapuli #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 607ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR50 BIT(3) 617ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR104 BIT(4) 627ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_DDR50 BIT(5) 63e5c63d91SLucas Stach #define NVQUIRK_HAS_PADCALIB BIT(6) 6486ac2f8bSAapo Vienamo #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 653e44a1a7SStephen Warren 663e44a1a7SStephen Warren struct sdhci_tegra_soc_data { 671db5eebfSLars-Peter Clausen const struct sdhci_pltfm_data *pdata; 683e44a1a7SStephen Warren u32 nvquirks; 693e44a1a7SStephen Warren }; 703e44a1a7SStephen Warren 713e44a1a7SStephen Warren struct sdhci_tegra { 723e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 732391b340SMylene JOSSERAND struct gpio_desc *power_gpio; 74a8e326a9SLucas Stach bool ddr_signaling; 75e5c63d91SLucas Stach bool pad_calib_required; 7686ac2f8bSAapo Vienamo bool pad_control_available; 7720567be9SThierry Reding 7820567be9SThierry Reding struct reset_control *rst; 7986ac2f8bSAapo Vienamo struct pinctrl *pinctrl_sdmmc; 8086ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_3v3; 8186ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_1v8; 823e44a1a7SStephen Warren }; 833e44a1a7SStephen Warren 8403d2bfc8SOlof Johansson static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 8503d2bfc8SOlof Johansson { 863e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 870734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 883e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 893e44a1a7SStephen Warren 903e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 913e44a1a7SStephen Warren (reg == SDHCI_HOST_VERSION))) { 9203d2bfc8SOlof Johansson /* Erratum: Version register is invalid in HW. */ 9303d2bfc8SOlof Johansson return SDHCI_SPEC_200; 9403d2bfc8SOlof Johansson } 9503d2bfc8SOlof Johansson 9603d2bfc8SOlof Johansson return readw(host->ioaddr + reg); 9703d2bfc8SOlof Johansson } 9803d2bfc8SOlof Johansson 99352ee868SPavan Kunapuli static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 100352ee868SPavan Kunapuli { 101352ee868SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 102352ee868SPavan Kunapuli 103352ee868SPavan Kunapuli switch (reg) { 104352ee868SPavan Kunapuli case SDHCI_TRANSFER_MODE: 105352ee868SPavan Kunapuli /* 106352ee868SPavan Kunapuli * Postpone this write, we must do it together with a 107352ee868SPavan Kunapuli * command write that is down below. 108352ee868SPavan Kunapuli */ 109352ee868SPavan Kunapuli pltfm_host->xfer_mode_shadow = val; 110352ee868SPavan Kunapuli return; 111352ee868SPavan Kunapuli case SDHCI_COMMAND: 112352ee868SPavan Kunapuli writel((val << 16) | pltfm_host->xfer_mode_shadow, 113352ee868SPavan Kunapuli host->ioaddr + SDHCI_TRANSFER_MODE); 114352ee868SPavan Kunapuli return; 115352ee868SPavan Kunapuli } 116352ee868SPavan Kunapuli 117352ee868SPavan Kunapuli writew(val, host->ioaddr + reg); 118352ee868SPavan Kunapuli } 119352ee868SPavan Kunapuli 12003d2bfc8SOlof Johansson static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 12103d2bfc8SOlof Johansson { 1223e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1230734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1243e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1253e44a1a7SStephen Warren 12603d2bfc8SOlof Johansson /* Seems like we're getting spurious timeout and crc errors, so 12703d2bfc8SOlof Johansson * disable signalling of them. In case of real errors software 12803d2bfc8SOlof Johansson * timers should take care of eventually detecting them. 12903d2bfc8SOlof Johansson */ 13003d2bfc8SOlof Johansson if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 13103d2bfc8SOlof Johansson val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 13203d2bfc8SOlof Johansson 13303d2bfc8SOlof Johansson writel(val, host->ioaddr + reg); 13403d2bfc8SOlof Johansson 1353e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 1363e44a1a7SStephen Warren (reg == SDHCI_INT_ENABLE))) { 13703d2bfc8SOlof Johansson /* Erratum: Must enable block gap interrupt detection */ 13803d2bfc8SOlof Johansson u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 13903d2bfc8SOlof Johansson if (val & SDHCI_INT_CARD_INT) 14003d2bfc8SOlof Johansson gap_ctrl |= 0x8; 14103d2bfc8SOlof Johansson else 14203d2bfc8SOlof Johansson gap_ctrl &= ~0x8; 14303d2bfc8SOlof Johansson writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 14403d2bfc8SOlof Johansson } 14503d2bfc8SOlof Johansson } 14603d2bfc8SOlof Johansson 1473e44a1a7SStephen Warren static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 14803d2bfc8SOlof Johansson { 1490aacd23fSJoseph Lo return mmc_gpio_get_ro(host->mmc); 15003d2bfc8SOlof Johansson } 15103d2bfc8SOlof Johansson 15286ac2f8bSAapo Vienamo static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 15386ac2f8bSAapo Vienamo { 15486ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 15586ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 15686ac2f8bSAapo Vienamo int has_1v8, has_3v3; 15786ac2f8bSAapo Vienamo 15886ac2f8bSAapo Vienamo /* 15986ac2f8bSAapo Vienamo * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 16086ac2f8bSAapo Vienamo * voltage configuration in order to perform voltage switching. This 16186ac2f8bSAapo Vienamo * means that valid pinctrl info is required on SDHCI instances capable 16286ac2f8bSAapo Vienamo * of performing voltage switching. Whether or not an SDHCI instance is 16386ac2f8bSAapo Vienamo * capable of voltage switching is determined based on the regulator. 16486ac2f8bSAapo Vienamo */ 16586ac2f8bSAapo Vienamo 16686ac2f8bSAapo Vienamo if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 16786ac2f8bSAapo Vienamo return true; 16886ac2f8bSAapo Vienamo 16986ac2f8bSAapo Vienamo if (IS_ERR(host->mmc->supply.vqmmc)) 17086ac2f8bSAapo Vienamo return false; 17186ac2f8bSAapo Vienamo 17286ac2f8bSAapo Vienamo has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 17386ac2f8bSAapo Vienamo 1700000, 1950000); 17486ac2f8bSAapo Vienamo 17586ac2f8bSAapo Vienamo has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 17686ac2f8bSAapo Vienamo 2700000, 3600000); 17786ac2f8bSAapo Vienamo 17886ac2f8bSAapo Vienamo if (has_1v8 == 1 && has_3v3 == 1) 17986ac2f8bSAapo Vienamo return tegra_host->pad_control_available; 18086ac2f8bSAapo Vienamo 18186ac2f8bSAapo Vienamo /* Fixed voltage, no pad control required. */ 18286ac2f8bSAapo Vienamo return true; 18386ac2f8bSAapo Vienamo } 18486ac2f8bSAapo Vienamo 18503231f9bSRussell King static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 186ca5879d3SPavan Kunapuli { 187ca5879d3SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1880734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 189ca5879d3SPavan Kunapuli const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 19074cd42bcSLucas Stach u32 misc_ctrl, clk_ctrl; 191ca5879d3SPavan Kunapuli 19203231f9bSRussell King sdhci_reset(host, mask); 19303231f9bSRussell King 194ca5879d3SPavan Kunapuli if (!(mask & SDHCI_RESET_ALL)) 195ca5879d3SPavan Kunapuli return; 196ca5879d3SPavan Kunapuli 1971b84def8SLucas Stach misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1984f6aa326SJon Hunter clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 1994f6aa326SJon Hunter 2004f6aa326SJon Hunter misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 2014f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR50 | 2024f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_DDR50 | 2034f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR104); 2044f6aa326SJon Hunter 2054f6aa326SJon Hunter clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 2064f6aa326SJon Hunter 20786ac2f8bSAapo Vienamo if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 208ca5879d3SPavan Kunapuli /* Erratum: Enable SDHCI spec v3.00 support */ 2093145351aSAndrew Bresticker if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 210ca5879d3SPavan Kunapuli misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 2117ad2ed1dSLucas Stach /* Advertise UHS modes as supported by host */ 2127ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 2137ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 2147ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 2157ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 2167ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 2177ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 2187ad2ed1dSLucas Stach if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 219c3c2384cSLucas Stach clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 2204f6aa326SJon Hunter } 2214f6aa326SJon Hunter 2224f6aa326SJon Hunter sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 22374cd42bcSLucas Stach sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 22474cd42bcSLucas Stach 225e5c63d91SLucas Stach if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 226e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 227e5c63d91SLucas Stach 228a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 229ca5879d3SPavan Kunapuli } 230ca5879d3SPavan Kunapuli 231e5c63d91SLucas Stach static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 232e5c63d91SLucas Stach { 233e7c07148SAapo Vienamo u32 reg; 234e7c07148SAapo Vienamo int ret; 235e5c63d91SLucas Stach 236e7c07148SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 237e7c07148SAapo Vienamo reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 238e7c07148SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 239e5c63d91SLucas Stach 240e7c07148SAapo Vienamo usleep_range(1, 2); 241e7c07148SAapo Vienamo /* 10 ms timeout */ 242e7c07148SAapo Vienamo ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 243e7c07148SAapo Vienamo reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 244e7c07148SAapo Vienamo 1000, 10000); 245e7c07148SAapo Vienamo 246e7c07148SAapo Vienamo if (ret) 247e7c07148SAapo Vienamo dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 248e5c63d91SLucas Stach } 249e5c63d91SLucas Stach 250a8e326a9SLucas Stach static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 251a8e326a9SLucas Stach { 252a8e326a9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2530734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 254a8e326a9SLucas Stach unsigned long host_clk; 255a8e326a9SLucas Stach 256a8e326a9SLucas Stach if (!clock) 2573491b690SLucas Stach return sdhci_set_clock(host, clock); 258a8e326a9SLucas Stach 25957d1654eSAapo Vienamo /* 26057d1654eSAapo Vienamo * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 26157d1654eSAapo Vienamo * divider to be configured to divided the host clock by two. The SDHCI 26257d1654eSAapo Vienamo * clock divider is calculated as part of sdhci_set_clock() by 26357d1654eSAapo Vienamo * sdhci_calc_clk(). The divider is calculated from host->max_clk and 26457d1654eSAapo Vienamo * the requested clock rate. 26557d1654eSAapo Vienamo * 26657d1654eSAapo Vienamo * By setting the host->max_clk to clock * 2 the divider calculation 26757d1654eSAapo Vienamo * will always result in the correct value for DDR50/52 modes, 26857d1654eSAapo Vienamo * regardless of clock rate rounding, which may happen if the value 26957d1654eSAapo Vienamo * from clk_get_rate() is used. 27057d1654eSAapo Vienamo */ 271a8e326a9SLucas Stach host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 272a8e326a9SLucas Stach clk_set_rate(pltfm_host->clk, host_clk); 27357d1654eSAapo Vienamo if (tegra_host->ddr_signaling) 27457d1654eSAapo Vienamo host->max_clk = host_clk; 27557d1654eSAapo Vienamo else 276a8e326a9SLucas Stach host->max_clk = clk_get_rate(pltfm_host->clk); 277a8e326a9SLucas Stach 278e5c63d91SLucas Stach sdhci_set_clock(host, clock); 279e5c63d91SLucas Stach 280e5c63d91SLucas Stach if (tegra_host->pad_calib_required) { 281e5c63d91SLucas Stach tegra_sdhci_pad_autocalib(host); 282e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 283e5c63d91SLucas Stach } 284a8e326a9SLucas Stach } 285a8e326a9SLucas Stach 286a8e326a9SLucas Stach static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 287a8e326a9SLucas Stach unsigned timing) 288a8e326a9SLucas Stach { 289a8e326a9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2900734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 291a8e326a9SLucas Stach 292e300149eSStefan Agner if (timing == MMC_TIMING_UHS_DDR50 || 293e300149eSStefan Agner timing == MMC_TIMING_MMC_DDR52) 294a8e326a9SLucas Stach tegra_host->ddr_signaling = true; 295a8e326a9SLucas Stach 296cf56c819SAapo Vienamo sdhci_set_uhs_signaling(host, timing); 297a8e326a9SLucas Stach } 298a8e326a9SLucas Stach 29944350993SAapo Vienamo static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 30044350993SAapo Vienamo { 30144350993SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 30244350993SAapo Vienamo 30344350993SAapo Vienamo return clk_round_rate(pltfm_host->clk, UINT_MAX); 30444350993SAapo Vienamo } 30544350993SAapo Vienamo 306c3c2384cSLucas Stach static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 307c3c2384cSLucas Stach { 308c3c2384cSLucas Stach u32 reg; 309c3c2384cSLucas Stach 310c3c2384cSLucas Stach reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 311c3c2384cSLucas Stach reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 312c3c2384cSLucas Stach reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 313c3c2384cSLucas Stach sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 314c3c2384cSLucas Stach } 315c3c2384cSLucas Stach 316c3c2384cSLucas Stach static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 317c3c2384cSLucas Stach { 318c3c2384cSLucas Stach unsigned int min, max; 319c3c2384cSLucas Stach 320c3c2384cSLucas Stach /* 321c3c2384cSLucas Stach * Start search for minimum tap value at 10, as smaller values are 322c3c2384cSLucas Stach * may wrongly be reported as working but fail at higher speeds, 323c3c2384cSLucas Stach * according to the TRM. 324c3c2384cSLucas Stach */ 325c3c2384cSLucas Stach min = 10; 326c3c2384cSLucas Stach while (min < 255) { 327c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min); 328c3c2384cSLucas Stach if (!mmc_send_tuning(host->mmc, opcode, NULL)) 329c3c2384cSLucas Stach break; 330c3c2384cSLucas Stach min++; 331c3c2384cSLucas Stach } 332c3c2384cSLucas Stach 333c3c2384cSLucas Stach /* Find the maximum tap value that still passes. */ 334c3c2384cSLucas Stach max = min + 1; 335c3c2384cSLucas Stach while (max < 255) { 336c3c2384cSLucas Stach tegra_sdhci_set_tap(host, max); 337c3c2384cSLucas Stach if (mmc_send_tuning(host->mmc, opcode, NULL)) { 338c3c2384cSLucas Stach max--; 339c3c2384cSLucas Stach break; 340c3c2384cSLucas Stach } 341c3c2384cSLucas Stach max++; 342c3c2384cSLucas Stach } 343c3c2384cSLucas Stach 344c3c2384cSLucas Stach /* The TRM states the ideal tap value is at 75% in the passing range. */ 345c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 346c3c2384cSLucas Stach 347c3c2384cSLucas Stach return mmc_send_tuning(host->mmc, opcode, NULL); 348c3c2384cSLucas Stach } 349c3c2384cSLucas Stach 35086ac2f8bSAapo Vienamo static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 35186ac2f8bSAapo Vienamo { 35286ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 35386ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 35486ac2f8bSAapo Vienamo int ret; 35586ac2f8bSAapo Vienamo 35686ac2f8bSAapo Vienamo if (!tegra_host->pad_control_available) 35786ac2f8bSAapo Vienamo return 0; 35886ac2f8bSAapo Vienamo 35986ac2f8bSAapo Vienamo if (voltage == MMC_SIGNAL_VOLTAGE_180) { 36086ac2f8bSAapo Vienamo ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 36186ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8); 36286ac2f8bSAapo Vienamo if (ret < 0) 36386ac2f8bSAapo Vienamo dev_err(mmc_dev(host->mmc), 36486ac2f8bSAapo Vienamo "setting 1.8V failed, ret: %d\n", ret); 36586ac2f8bSAapo Vienamo } else { 36686ac2f8bSAapo Vienamo ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 36786ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3); 36886ac2f8bSAapo Vienamo if (ret < 0) 36986ac2f8bSAapo Vienamo dev_err(mmc_dev(host->mmc), 37086ac2f8bSAapo Vienamo "setting 3.3V failed, ret: %d\n", ret); 37186ac2f8bSAapo Vienamo } 37286ac2f8bSAapo Vienamo 37386ac2f8bSAapo Vienamo return ret; 37486ac2f8bSAapo Vienamo } 37586ac2f8bSAapo Vienamo 37686ac2f8bSAapo Vienamo static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 37786ac2f8bSAapo Vienamo struct mmc_ios *ios) 37886ac2f8bSAapo Vienamo { 37986ac2f8bSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 38086ac2f8bSAapo Vienamo int ret = 0; 38186ac2f8bSAapo Vienamo 38286ac2f8bSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 38386ac2f8bSAapo Vienamo ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 38486ac2f8bSAapo Vienamo if (ret < 0) 38586ac2f8bSAapo Vienamo return ret; 38686ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 38786ac2f8bSAapo Vienamo } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 38886ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 38986ac2f8bSAapo Vienamo if (ret < 0) 39086ac2f8bSAapo Vienamo return ret; 39186ac2f8bSAapo Vienamo ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 39286ac2f8bSAapo Vienamo } 39386ac2f8bSAapo Vienamo 39486ac2f8bSAapo Vienamo return ret; 39586ac2f8bSAapo Vienamo } 39686ac2f8bSAapo Vienamo 39786ac2f8bSAapo Vienamo static int tegra_sdhci_init_pinctrl_info(struct device *dev, 39886ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host) 39986ac2f8bSAapo Vienamo { 40086ac2f8bSAapo Vienamo tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 40186ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 40286ac2f8bSAapo Vienamo dev_dbg(dev, "No pinctrl info, err: %ld\n", 40386ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_sdmmc)); 40486ac2f8bSAapo Vienamo return -1; 40586ac2f8bSAapo Vienamo } 40686ac2f8bSAapo Vienamo 40786ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3 = 40886ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 40986ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 41086ac2f8bSAapo Vienamo dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 41186ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 41286ac2f8bSAapo Vienamo return -1; 41386ac2f8bSAapo Vienamo } 41486ac2f8bSAapo Vienamo 41586ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8 = 41686ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 41786ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 41886ac2f8bSAapo Vienamo dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 41986ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 42086ac2f8bSAapo Vienamo return -1; 42186ac2f8bSAapo Vienamo } 42286ac2f8bSAapo Vienamo 42386ac2f8bSAapo Vienamo tegra_host->pad_control_available = true; 42486ac2f8bSAapo Vienamo 42586ac2f8bSAapo Vienamo return 0; 42686ac2f8bSAapo Vienamo } 42786ac2f8bSAapo Vienamo 428e5c63d91SLucas Stach static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 429e5c63d91SLucas Stach { 430e5c63d91SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 431e5c63d91SLucas Stach struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 432e5c63d91SLucas Stach const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 433e5c63d91SLucas Stach 434e5c63d91SLucas Stach if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 435e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 436e5c63d91SLucas Stach } 437e5c63d91SLucas Stach 438c915568dSLars-Peter Clausen static const struct sdhci_ops tegra_sdhci_ops = { 43985d6509dSShawn Guo .get_ro = tegra_sdhci_get_ro, 44085d6509dSShawn Guo .read_w = tegra_sdhci_readw, 44185d6509dSShawn Guo .write_l = tegra_sdhci_writel, 442a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 44314b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 44403231f9bSRussell King .reset = tegra_sdhci_reset, 445c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 446a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 447e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 44844350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 44985d6509dSShawn Guo }; 45003d2bfc8SOlof Johansson 4511db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 45285d6509dSShawn Guo .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 45385d6509dSShawn Guo SDHCI_QUIRK_SINGLE_POWER_WRITE | 45485d6509dSShawn Guo SDHCI_QUIRK_NO_HISPD_BIT | 455f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 456f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 45785d6509dSShawn Guo .ops = &tegra_sdhci_ops, 45885d6509dSShawn Guo }; 45985d6509dSShawn Guo 460d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 4613e44a1a7SStephen Warren .pdata = &sdhci_tegra20_pdata, 4623e44a1a7SStephen Warren .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 4633e44a1a7SStephen Warren NVQUIRK_ENABLE_BLOCK_GAP_DET, 4643e44a1a7SStephen Warren }; 4653e44a1a7SStephen Warren 4661db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 4673e44a1a7SStephen Warren .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 4683e44a1a7SStephen Warren SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 4693e44a1a7SStephen Warren SDHCI_QUIRK_SINGLE_POWER_WRITE | 4703e44a1a7SStephen Warren SDHCI_QUIRK_NO_HISPD_BIT | 471f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 472f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 473127407e3SStefan Agner .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 474726df1d5SStefan Agner SDHCI_QUIRK2_BROKEN_HS200 | 475726df1d5SStefan Agner /* 476726df1d5SStefan Agner * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 477726df1d5SStefan Agner * though no command operation was in progress." 478726df1d5SStefan Agner * 479726df1d5SStefan Agner * The exact reason is unknown, as the same hardware seems 480726df1d5SStefan Agner * to support Auto CMD23 on a downstream 3.1 kernel. 481726df1d5SStefan Agner */ 482726df1d5SStefan Agner SDHCI_QUIRK2_ACMD23_BROKEN, 4833e44a1a7SStephen Warren .ops = &tegra_sdhci_ops, 4843e44a1a7SStephen Warren }; 4853e44a1a7SStephen Warren 486d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 4873e44a1a7SStephen Warren .pdata = &sdhci_tegra30_pdata, 4883145351aSAndrew Bresticker .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 4897ad2ed1dSLucas Stach NVQUIRK_ENABLE_SDR50 | 490e5c63d91SLucas Stach NVQUIRK_ENABLE_SDR104 | 491e5c63d91SLucas Stach NVQUIRK_HAS_PADCALIB, 4923e44a1a7SStephen Warren }; 4933e44a1a7SStephen Warren 49401df7ecdSRhyland Klein static const struct sdhci_ops tegra114_sdhci_ops = { 49501df7ecdSRhyland Klein .get_ro = tegra_sdhci_get_ro, 49601df7ecdSRhyland Klein .read_w = tegra_sdhci_readw, 49701df7ecdSRhyland Klein .write_w = tegra_sdhci_writew, 49801df7ecdSRhyland Klein .write_l = tegra_sdhci_writel, 499a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 50014b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 50101df7ecdSRhyland Klein .reset = tegra_sdhci_reset, 502c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 503a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 504e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 50544350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 50601df7ecdSRhyland Klein }; 50701df7ecdSRhyland Klein 5081db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 5095ebf2552SRhyland Klein .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 5105ebf2552SRhyland Klein SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 5115ebf2552SRhyland Klein SDHCI_QUIRK_SINGLE_POWER_WRITE | 5125ebf2552SRhyland Klein SDHCI_QUIRK_NO_HISPD_BIT | 513f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 514f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 515a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 51601df7ecdSRhyland Klein .ops = &tegra114_sdhci_ops, 5175ebf2552SRhyland Klein }; 5185ebf2552SRhyland Klein 519d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 5205ebf2552SRhyland Klein .pdata = &sdhci_tegra114_pdata, 5217bf037d6SJon Hunter }; 5227bf037d6SJon Hunter 5234ae12588SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 5244ae12588SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 5254ae12588SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 5264ae12588SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 5274ae12588SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 5284ae12588SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 5294ae12588SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 5304ae12588SThierry Reding .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 5314ae12588SThierry Reding /* 5324ae12588SThierry Reding * The TRM states that the SD/MMC controller found on 5334ae12588SThierry Reding * Tegra124 can address 34 bits (the maximum supported by 5344ae12588SThierry Reding * the Tegra memory controller), but tests show that DMA 5354ae12588SThierry Reding * to or from above 4 GiB doesn't work. This is possibly 5364ae12588SThierry Reding * caused by missing programming, though it's not obvious 5374ae12588SThierry Reding * what sequence is required. Mark 64-bit DMA broken for 5384ae12588SThierry Reding * now to fix this for existing users (e.g. Nyan boards). 5394ae12588SThierry Reding */ 5404ae12588SThierry Reding SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 5414ae12588SThierry Reding .ops = &tegra114_sdhci_ops, 5424ae12588SThierry Reding }; 5434ae12588SThierry Reding 5444ae12588SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 5454ae12588SThierry Reding .pdata = &sdhci_tegra124_pdata, 5464ae12588SThierry Reding }; 5474ae12588SThierry Reding 548b5a84ecfSThierry Reding static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 549b5a84ecfSThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 550b5a84ecfSThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 551b5a84ecfSThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 552b5a84ecfSThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 553a8e326a9SLucas Stach SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 554a8e326a9SLucas Stach SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 555a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 556b5a84ecfSThierry Reding .ops = &tegra114_sdhci_ops, 557b5a84ecfSThierry Reding }; 558b5a84ecfSThierry Reding 559b5a84ecfSThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 560b5a84ecfSThierry Reding .pdata = &sdhci_tegra210_pdata, 56186ac2f8bSAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 562b5a84ecfSThierry Reding }; 563b5a84ecfSThierry Reding 5644346b7c7SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 5654346b7c7SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 5664346b7c7SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 5674346b7c7SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 5684346b7c7SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 5694346b7c7SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 5704346b7c7SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 57168481a7eSKrishna Reddy .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 57268481a7eSKrishna Reddy /* SDHCI controllers on Tegra186 support 40-bit addressing. 57368481a7eSKrishna Reddy * IOVA addresses are 48-bit wide on Tegra186. 57468481a7eSKrishna Reddy * With 64-bit dma mask used for SDHCI, accesses can 57568481a7eSKrishna Reddy * be broken. Disable 64-bit dma, which would fall back 57668481a7eSKrishna Reddy * to 32-bit dma mask. Ideally 40-bit dma mask would work, 57768481a7eSKrishna Reddy * But it is not supported as of now. 57868481a7eSKrishna Reddy */ 57968481a7eSKrishna Reddy SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 5804346b7c7SThierry Reding .ops = &tegra114_sdhci_ops, 5814346b7c7SThierry Reding }; 5824346b7c7SThierry Reding 5834346b7c7SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 5844346b7c7SThierry Reding .pdata = &sdhci_tegra186_pdata, 58586ac2f8bSAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 5864346b7c7SThierry Reding }; 5874346b7c7SThierry Reding 588498d83e7SBill Pemberton static const struct of_device_id sdhci_tegra_dt_match[] = { 5894346b7c7SThierry Reding { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 590b5a84ecfSThierry Reding { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 5914ae12588SThierry Reding { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 5925ebf2552SRhyland Klein { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 5933e44a1a7SStephen Warren { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 5943e44a1a7SStephen Warren { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 595275173b2SGrant Likely {} 596275173b2SGrant Likely }; 597e4404fabSArnd Bergmann MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 598275173b2SGrant Likely 599c3be1efdSBill Pemberton static int sdhci_tegra_probe(struct platform_device *pdev) 60003d2bfc8SOlof Johansson { 6013e44a1a7SStephen Warren const struct of_device_id *match; 6023e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 6033e44a1a7SStephen Warren struct sdhci_host *host; 60485d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 6053e44a1a7SStephen Warren struct sdhci_tegra *tegra_host; 60603d2bfc8SOlof Johansson struct clk *clk; 60703d2bfc8SOlof Johansson int rc; 60803d2bfc8SOlof Johansson 6093e44a1a7SStephen Warren match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 610b37f9d98SJoseph Lo if (!match) 611b37f9d98SJoseph Lo return -EINVAL; 6123e44a1a7SStephen Warren soc_data = match->data; 6133e44a1a7SStephen Warren 6140734e79cSJisheng Zhang host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 61585d6509dSShawn Guo if (IS_ERR(host)) 61685d6509dSShawn Guo return PTR_ERR(host); 61785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 61885d6509dSShawn Guo 6190734e79cSJisheng Zhang tegra_host = sdhci_pltfm_priv(pltfm_host); 620a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 621e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 62286ac2f8bSAapo Vienamo tegra_host->pad_control_available = false; 6233e44a1a7SStephen Warren tegra_host->soc_data = soc_data; 624275173b2SGrant Likely 62586ac2f8bSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 62686ac2f8bSAapo Vienamo rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 62786ac2f8bSAapo Vienamo if (rc == 0) 62886ac2f8bSAapo Vienamo host->mmc_host_ops.start_signal_voltage_switch = 62986ac2f8bSAapo Vienamo sdhci_tegra_start_signal_voltage_switch; 63086ac2f8bSAapo Vienamo } 63186ac2f8bSAapo Vienamo 6322391b340SMylene JOSSERAND rc = mmc_of_parse(host->mmc); 63347caa84fSSimon Baatz if (rc) 63447caa84fSSimon Baatz goto err_parse_dt; 6350e786102SStephen Warren 6367ad2ed1dSLucas Stach if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 637c3c2384cSLucas Stach host->mmc->caps |= MMC_CAP_1_8V_DDR; 638c3c2384cSLucas Stach 6392391b340SMylene JOSSERAND tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 6402391b340SMylene JOSSERAND GPIOD_OUT_HIGH); 6412391b340SMylene JOSSERAND if (IS_ERR(tegra_host->power_gpio)) { 6422391b340SMylene JOSSERAND rc = PTR_ERR(tegra_host->power_gpio); 64385d6509dSShawn Guo goto err_power_req; 64403d2bfc8SOlof Johansson } 64503d2bfc8SOlof Johansson 646e4f79d9cSKevin Hao clk = devm_clk_get(mmc_dev(host->mmc), NULL); 64703d2bfc8SOlof Johansson if (IS_ERR(clk)) { 64803d2bfc8SOlof Johansson dev_err(mmc_dev(host->mmc), "clk err\n"); 64903d2bfc8SOlof Johansson rc = PTR_ERR(clk); 65085d6509dSShawn Guo goto err_clk_get; 65103d2bfc8SOlof Johansson } 6521e674bc6SPrashant Gaikwad clk_prepare_enable(clk); 65303d2bfc8SOlof Johansson pltfm_host->clk = clk; 65403d2bfc8SOlof Johansson 6552cd6c49dSPhilipp Zabel tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 6562cd6c49dSPhilipp Zabel "sdhci"); 65720567be9SThierry Reding if (IS_ERR(tegra_host->rst)) { 65820567be9SThierry Reding rc = PTR_ERR(tegra_host->rst); 65920567be9SThierry Reding dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 66020567be9SThierry Reding goto err_rst_get; 66120567be9SThierry Reding } 66220567be9SThierry Reding 66320567be9SThierry Reding rc = reset_control_assert(tegra_host->rst); 66420567be9SThierry Reding if (rc) 66520567be9SThierry Reding goto err_rst_get; 66620567be9SThierry Reding 66720567be9SThierry Reding usleep_range(2000, 4000); 66820567be9SThierry Reding 66920567be9SThierry Reding rc = reset_control_deassert(tegra_host->rst); 67020567be9SThierry Reding if (rc) 67120567be9SThierry Reding goto err_rst_get; 67220567be9SThierry Reding 67320567be9SThierry Reding usleep_range(2000, 4000); 67420567be9SThierry Reding 67585d6509dSShawn Guo rc = sdhci_add_host(host); 67685d6509dSShawn Guo if (rc) 67785d6509dSShawn Guo goto err_add_host; 67885d6509dSShawn Guo 67903d2bfc8SOlof Johansson return 0; 68003d2bfc8SOlof Johansson 68185d6509dSShawn Guo err_add_host: 68220567be9SThierry Reding reset_control_assert(tegra_host->rst); 68320567be9SThierry Reding err_rst_get: 6841e674bc6SPrashant Gaikwad clk_disable_unprepare(pltfm_host->clk); 68585d6509dSShawn Guo err_clk_get: 68685d6509dSShawn Guo err_power_req: 68747caa84fSSimon Baatz err_parse_dt: 68885d6509dSShawn Guo sdhci_pltfm_free(pdev); 68903d2bfc8SOlof Johansson return rc; 69003d2bfc8SOlof Johansson } 69103d2bfc8SOlof Johansson 69220567be9SThierry Reding static int sdhci_tegra_remove(struct platform_device *pdev) 69320567be9SThierry Reding { 69420567be9SThierry Reding struct sdhci_host *host = platform_get_drvdata(pdev); 69520567be9SThierry Reding struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69620567be9SThierry Reding struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 69720567be9SThierry Reding 69820567be9SThierry Reding sdhci_remove_host(host, 0); 69920567be9SThierry Reding 70020567be9SThierry Reding reset_control_assert(tegra_host->rst); 70120567be9SThierry Reding usleep_range(2000, 4000); 70220567be9SThierry Reding clk_disable_unprepare(pltfm_host->clk); 70320567be9SThierry Reding 70420567be9SThierry Reding sdhci_pltfm_free(pdev); 70520567be9SThierry Reding 70620567be9SThierry Reding return 0; 70720567be9SThierry Reding } 70820567be9SThierry Reding 70985d6509dSShawn Guo static struct platform_driver sdhci_tegra_driver = { 71085d6509dSShawn Guo .driver = { 71185d6509dSShawn Guo .name = "sdhci-tegra", 712275173b2SGrant Likely .of_match_table = sdhci_tegra_dt_match, 713fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops, 71485d6509dSShawn Guo }, 71585d6509dSShawn Guo .probe = sdhci_tegra_probe, 71620567be9SThierry Reding .remove = sdhci_tegra_remove, 71703d2bfc8SOlof Johansson }; 71803d2bfc8SOlof Johansson 719d1f81a64SAxel Lin module_platform_driver(sdhci_tegra_driver); 72085d6509dSShawn Guo 72185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Tegra"); 72285d6509dSShawn Guo MODULE_AUTHOR("Google, Inc."); 72385d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 724