103d2bfc8SOlof Johansson /* 203d2bfc8SOlof Johansson * Copyright (C) 2010 Google, Inc. 303d2bfc8SOlof Johansson * 403d2bfc8SOlof Johansson * This software is licensed under the terms of the GNU General Public 503d2bfc8SOlof Johansson * License version 2, as published by the Free Software Foundation, and 603d2bfc8SOlof Johansson * may be copied, distributed, and modified under those terms. 703d2bfc8SOlof Johansson * 803d2bfc8SOlof Johansson * This program is distributed in the hope that it will be useful, 903d2bfc8SOlof Johansson * but WITHOUT ANY WARRANTY; without even the implied warranty of 1003d2bfc8SOlof Johansson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1103d2bfc8SOlof Johansson * GNU General Public License for more details. 1203d2bfc8SOlof Johansson * 1303d2bfc8SOlof Johansson */ 1403d2bfc8SOlof Johansson 15e5c63d91SLucas Stach #include <linux/delay.h> 1603d2bfc8SOlof Johansson #include <linux/err.h> 1796547f5dSPaul Gortmaker #include <linux/module.h> 1803d2bfc8SOlof Johansson #include <linux/init.h> 19e7c07148SAapo Vienamo #include <linux/iopoll.h> 2003d2bfc8SOlof Johansson #include <linux/platform_device.h> 2103d2bfc8SOlof Johansson #include <linux/clk.h> 2203d2bfc8SOlof Johansson #include <linux/io.h> 2355cd65e4SStephen Warren #include <linux/of.h> 243e44a1a7SStephen Warren #include <linux/of_device.h> 2586ac2f8bSAapo Vienamo #include <linux/pinctrl/consumer.h> 2686ac2f8bSAapo Vienamo #include <linux/regulator/consumer.h> 2720567be9SThierry Reding #include <linux/reset.h> 2803d2bfc8SOlof Johansson #include <linux/mmc/card.h> 2903d2bfc8SOlof Johansson #include <linux/mmc/host.h> 30c3c2384cSLucas Stach #include <linux/mmc/mmc.h> 310aacd23fSJoseph Lo #include <linux/mmc/slot-gpio.h> 322391b340SMylene JOSSERAND #include <linux/gpio/consumer.h> 3303d2bfc8SOlof Johansson 3403d2bfc8SOlof Johansson #include "sdhci-pltfm.h" 3503d2bfc8SOlof Johansson 36ca5879d3SPavan Kunapuli /* Tegra SDHOST controller vendor register definitions */ 3774cd42bcSLucas Stach #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 4041a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 4141a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 42c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 4374cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 4474cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 4574cd42bcSLucas Stach 46dfc9700cSAapo Vienamo #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 47dfc9700cSAapo Vienamo #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 48dfc9700cSAapo Vienamo 49f5313aaaSAapo Vienamo #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 50f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 51f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 52f5313aaaSAapo Vienamo 53ca5879d3SPavan Kunapuli #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 543145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 553145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 56ca5879d3SPavan Kunapuli #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 573145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 58ca5879d3SPavan Kunapuli 59d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 60d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 61d4501d8eSAapo Vienamo 62e5c63d91SLucas Stach #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 63e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_START BIT(31) 64e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_ENABLE BIT(29) 6551b77c8eSAapo Vienamo #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 66e5c63d91SLucas Stach 679d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 689d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 699d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 70212b0cf1SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 719d548f11SAapo Vienamo 72e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 73e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 74e7c07148SAapo Vienamo 753e44a1a7SStephen Warren #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 763e44a1a7SStephen Warren #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 77ca5879d3SPavan Kunapuli #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 787ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR50 BIT(3) 797ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR104 BIT(4) 807ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_DDR50 BIT(5) 81e5c63d91SLucas Stach #define NVQUIRK_HAS_PADCALIB BIT(6) 8286ac2f8bSAapo Vienamo #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 83d4501d8eSAapo Vienamo #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 843e44a1a7SStephen Warren 853e44a1a7SStephen Warren struct sdhci_tegra_soc_data { 861db5eebfSLars-Peter Clausen const struct sdhci_pltfm_data *pdata; 873e44a1a7SStephen Warren u32 nvquirks; 883e44a1a7SStephen Warren }; 893e44a1a7SStephen Warren 9051b77c8eSAapo Vienamo /* Magic pull up and pull down pad calibration offsets */ 9151b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets { 9251b77c8eSAapo Vienamo u32 pull_up_3v3; 9351b77c8eSAapo Vienamo u32 pull_down_3v3; 9451b77c8eSAapo Vienamo u32 pull_up_3v3_timeout; 9551b77c8eSAapo Vienamo u32 pull_down_3v3_timeout; 9651b77c8eSAapo Vienamo u32 pull_up_1v8; 9751b77c8eSAapo Vienamo u32 pull_down_1v8; 9851b77c8eSAapo Vienamo u32 pull_up_1v8_timeout; 9951b77c8eSAapo Vienamo u32 pull_down_1v8_timeout; 10051b77c8eSAapo Vienamo u32 pull_up_sdr104; 10151b77c8eSAapo Vienamo u32 pull_down_sdr104; 10251b77c8eSAapo Vienamo u32 pull_up_hs400; 10351b77c8eSAapo Vienamo u32 pull_down_hs400; 10451b77c8eSAapo Vienamo }; 10551b77c8eSAapo Vienamo 1063e44a1a7SStephen Warren struct sdhci_tegra { 1073e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 1082391b340SMylene JOSSERAND struct gpio_desc *power_gpio; 109a8e326a9SLucas Stach bool ddr_signaling; 110e5c63d91SLucas Stach bool pad_calib_required; 11186ac2f8bSAapo Vienamo bool pad_control_available; 11220567be9SThierry Reding 11320567be9SThierry Reding struct reset_control *rst; 11486ac2f8bSAapo Vienamo struct pinctrl *pinctrl_sdmmc; 11586ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_3v3; 11686ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_1v8; 11751b77c8eSAapo Vienamo 11851b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets autocal_offsets; 11985c0da17SAapo Vienamo 12085c0da17SAapo Vienamo u32 default_tap; 12185c0da17SAapo Vienamo u32 default_trim; 122f5313aaaSAapo Vienamo u32 dqs_trim; 1233e44a1a7SStephen Warren }; 1243e44a1a7SStephen Warren 12503d2bfc8SOlof Johansson static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 12603d2bfc8SOlof Johansson { 1273e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1280734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1293e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1303e44a1a7SStephen Warren 1313e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 1323e44a1a7SStephen Warren (reg == SDHCI_HOST_VERSION))) { 13303d2bfc8SOlof Johansson /* Erratum: Version register is invalid in HW. */ 13403d2bfc8SOlof Johansson return SDHCI_SPEC_200; 13503d2bfc8SOlof Johansson } 13603d2bfc8SOlof Johansson 13703d2bfc8SOlof Johansson return readw(host->ioaddr + reg); 13803d2bfc8SOlof Johansson } 13903d2bfc8SOlof Johansson 140352ee868SPavan Kunapuli static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 141352ee868SPavan Kunapuli { 142352ee868SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 143352ee868SPavan Kunapuli 144352ee868SPavan Kunapuli switch (reg) { 145352ee868SPavan Kunapuli case SDHCI_TRANSFER_MODE: 146352ee868SPavan Kunapuli /* 147352ee868SPavan Kunapuli * Postpone this write, we must do it together with a 148352ee868SPavan Kunapuli * command write that is down below. 149352ee868SPavan Kunapuli */ 150352ee868SPavan Kunapuli pltfm_host->xfer_mode_shadow = val; 151352ee868SPavan Kunapuli return; 152352ee868SPavan Kunapuli case SDHCI_COMMAND: 153352ee868SPavan Kunapuli writel((val << 16) | pltfm_host->xfer_mode_shadow, 154352ee868SPavan Kunapuli host->ioaddr + SDHCI_TRANSFER_MODE); 155352ee868SPavan Kunapuli return; 156352ee868SPavan Kunapuli } 157352ee868SPavan Kunapuli 158352ee868SPavan Kunapuli writew(val, host->ioaddr + reg); 159352ee868SPavan Kunapuli } 160352ee868SPavan Kunapuli 16103d2bfc8SOlof Johansson static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 16203d2bfc8SOlof Johansson { 1633e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1640734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1653e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1663e44a1a7SStephen Warren 16703d2bfc8SOlof Johansson /* Seems like we're getting spurious timeout and crc errors, so 16803d2bfc8SOlof Johansson * disable signalling of them. In case of real errors software 16903d2bfc8SOlof Johansson * timers should take care of eventually detecting them. 17003d2bfc8SOlof Johansson */ 17103d2bfc8SOlof Johansson if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 17203d2bfc8SOlof Johansson val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 17303d2bfc8SOlof Johansson 17403d2bfc8SOlof Johansson writel(val, host->ioaddr + reg); 17503d2bfc8SOlof Johansson 1763e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 1773e44a1a7SStephen Warren (reg == SDHCI_INT_ENABLE))) { 17803d2bfc8SOlof Johansson /* Erratum: Must enable block gap interrupt detection */ 17903d2bfc8SOlof Johansson u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 18003d2bfc8SOlof Johansson if (val & SDHCI_INT_CARD_INT) 18103d2bfc8SOlof Johansson gap_ctrl |= 0x8; 18203d2bfc8SOlof Johansson else 18303d2bfc8SOlof Johansson gap_ctrl &= ~0x8; 18403d2bfc8SOlof Johansson writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 18503d2bfc8SOlof Johansson } 18603d2bfc8SOlof Johansson } 18703d2bfc8SOlof Johansson 18838a284d9SAapo Vienamo static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 18938a284d9SAapo Vienamo { 19038a284d9SAapo Vienamo bool status; 19138a284d9SAapo Vienamo u32 reg; 19238a284d9SAapo Vienamo 19338a284d9SAapo Vienamo reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 19438a284d9SAapo Vienamo status = !!(reg & SDHCI_CLOCK_CARD_EN); 19538a284d9SAapo Vienamo 19638a284d9SAapo Vienamo if (status == enable) 19738a284d9SAapo Vienamo return status; 19838a284d9SAapo Vienamo 19938a284d9SAapo Vienamo if (enable) 20038a284d9SAapo Vienamo reg |= SDHCI_CLOCK_CARD_EN; 20138a284d9SAapo Vienamo else 20238a284d9SAapo Vienamo reg &= ~SDHCI_CLOCK_CARD_EN; 20338a284d9SAapo Vienamo 20438a284d9SAapo Vienamo sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 20538a284d9SAapo Vienamo 20638a284d9SAapo Vienamo return status; 20738a284d9SAapo Vienamo } 20838a284d9SAapo Vienamo 20938a284d9SAapo Vienamo static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 21038a284d9SAapo Vienamo { 21138a284d9SAapo Vienamo bool is_tuning_cmd = 0; 21238a284d9SAapo Vienamo bool clk_enabled; 21338a284d9SAapo Vienamo u8 cmd; 21438a284d9SAapo Vienamo 21538a284d9SAapo Vienamo if (reg == SDHCI_COMMAND) { 21638a284d9SAapo Vienamo cmd = SDHCI_GET_CMD(val); 21738a284d9SAapo Vienamo is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 21838a284d9SAapo Vienamo cmd == MMC_SEND_TUNING_BLOCK_HS200; 21938a284d9SAapo Vienamo } 22038a284d9SAapo Vienamo 22138a284d9SAapo Vienamo if (is_tuning_cmd) 22238a284d9SAapo Vienamo clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 22338a284d9SAapo Vienamo 22438a284d9SAapo Vienamo writew(val, host->ioaddr + reg); 22538a284d9SAapo Vienamo 22638a284d9SAapo Vienamo if (is_tuning_cmd) { 22738a284d9SAapo Vienamo udelay(1); 22838a284d9SAapo Vienamo tegra_sdhci_configure_card_clk(host, clk_enabled); 22938a284d9SAapo Vienamo } 23038a284d9SAapo Vienamo } 23138a284d9SAapo Vienamo 2323e44a1a7SStephen Warren static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 23303d2bfc8SOlof Johansson { 2340aacd23fSJoseph Lo return mmc_gpio_get_ro(host->mmc); 23503d2bfc8SOlof Johansson } 23603d2bfc8SOlof Johansson 23786ac2f8bSAapo Vienamo static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 23886ac2f8bSAapo Vienamo { 23986ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 24086ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 24186ac2f8bSAapo Vienamo int has_1v8, has_3v3; 24286ac2f8bSAapo Vienamo 24386ac2f8bSAapo Vienamo /* 24486ac2f8bSAapo Vienamo * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 24586ac2f8bSAapo Vienamo * voltage configuration in order to perform voltage switching. This 24686ac2f8bSAapo Vienamo * means that valid pinctrl info is required on SDHCI instances capable 24786ac2f8bSAapo Vienamo * of performing voltage switching. Whether or not an SDHCI instance is 24886ac2f8bSAapo Vienamo * capable of voltage switching is determined based on the regulator. 24986ac2f8bSAapo Vienamo */ 25086ac2f8bSAapo Vienamo 25186ac2f8bSAapo Vienamo if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 25286ac2f8bSAapo Vienamo return true; 25386ac2f8bSAapo Vienamo 25486ac2f8bSAapo Vienamo if (IS_ERR(host->mmc->supply.vqmmc)) 25586ac2f8bSAapo Vienamo return false; 25686ac2f8bSAapo Vienamo 25786ac2f8bSAapo Vienamo has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 25886ac2f8bSAapo Vienamo 1700000, 1950000); 25986ac2f8bSAapo Vienamo 26086ac2f8bSAapo Vienamo has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 26186ac2f8bSAapo Vienamo 2700000, 3600000); 26286ac2f8bSAapo Vienamo 26386ac2f8bSAapo Vienamo if (has_1v8 == 1 && has_3v3 == 1) 26486ac2f8bSAapo Vienamo return tegra_host->pad_control_available; 26586ac2f8bSAapo Vienamo 26686ac2f8bSAapo Vienamo /* Fixed voltage, no pad control required. */ 26786ac2f8bSAapo Vienamo return true; 26886ac2f8bSAapo Vienamo } 26986ac2f8bSAapo Vienamo 270c2c09678SAapo Vienamo static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 271c2c09678SAapo Vienamo { 272c2c09678SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 273c2c09678SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 274c2c09678SAapo Vienamo const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 275c2c09678SAapo Vienamo bool card_clk_enabled = false; 276c2c09678SAapo Vienamo u32 reg; 277c2c09678SAapo Vienamo 278c2c09678SAapo Vienamo /* 279c2c09678SAapo Vienamo * Touching the tap values is a bit tricky on some SoC generations. 280c2c09678SAapo Vienamo * The quirk enables a workaround for a glitch that sometimes occurs if 281c2c09678SAapo Vienamo * the tap values are changed. 282c2c09678SAapo Vienamo */ 283c2c09678SAapo Vienamo 284c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 285c2c09678SAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 286c2c09678SAapo Vienamo 287c2c09678SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 288c2c09678SAapo Vienamo reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 289c2c09678SAapo Vienamo reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 290c2c09678SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 291c2c09678SAapo Vienamo 292c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 293c2c09678SAapo Vienamo card_clk_enabled) { 294c2c09678SAapo Vienamo udelay(1); 295c2c09678SAapo Vienamo sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 296c2c09678SAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 297c2c09678SAapo Vienamo } 298c2c09678SAapo Vienamo } 299c2c09678SAapo Vienamo 300dfc9700cSAapo Vienamo static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 301dfc9700cSAapo Vienamo struct mmc_ios *ios) 302dfc9700cSAapo Vienamo { 303dfc9700cSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 304dfc9700cSAapo Vienamo u32 val; 305dfc9700cSAapo Vienamo 306dfc9700cSAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 307dfc9700cSAapo Vienamo 308dfc9700cSAapo Vienamo if (ios->enhanced_strobe) 309dfc9700cSAapo Vienamo val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 310dfc9700cSAapo Vienamo else 311dfc9700cSAapo Vienamo val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 312dfc9700cSAapo Vienamo 313dfc9700cSAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 314dfc9700cSAapo Vienamo 315dfc9700cSAapo Vienamo } 316dfc9700cSAapo Vienamo 31703231f9bSRussell King static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 318ca5879d3SPavan Kunapuli { 319ca5879d3SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3200734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 321ca5879d3SPavan Kunapuli const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 3229d548f11SAapo Vienamo u32 misc_ctrl, clk_ctrl, pad_ctrl; 323ca5879d3SPavan Kunapuli 32403231f9bSRussell King sdhci_reset(host, mask); 32503231f9bSRussell King 326ca5879d3SPavan Kunapuli if (!(mask & SDHCI_RESET_ALL)) 327ca5879d3SPavan Kunapuli return; 328ca5879d3SPavan Kunapuli 329c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 330c2c09678SAapo Vienamo 3311b84def8SLucas Stach misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 3324f6aa326SJon Hunter clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 3334f6aa326SJon Hunter 3344f6aa326SJon Hunter misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 3354f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR50 | 3364f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_DDR50 | 3374f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR104); 3384f6aa326SJon Hunter 33941a0b8d7SAapo Vienamo clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 34041a0b8d7SAapo Vienamo SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 3414f6aa326SJon Hunter 34286ac2f8bSAapo Vienamo if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 343ca5879d3SPavan Kunapuli /* Erratum: Enable SDHCI spec v3.00 support */ 3443145351aSAndrew Bresticker if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 345ca5879d3SPavan Kunapuli misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 3467ad2ed1dSLucas Stach /* Advertise UHS modes as supported by host */ 3477ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 3487ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 3497ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 3507ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 3517ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 3527ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 3537ad2ed1dSLucas Stach if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 354c3c2384cSLucas Stach clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 3554f6aa326SJon Hunter } 3564f6aa326SJon Hunter 35741a0b8d7SAapo Vienamo clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 35841a0b8d7SAapo Vienamo 3594f6aa326SJon Hunter sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 36074cd42bcSLucas Stach sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 36174cd42bcSLucas Stach 3629d548f11SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 3639d548f11SAapo Vienamo pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 3649d548f11SAapo Vienamo pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 3659d548f11SAapo Vienamo pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 3669d548f11SAapo Vienamo sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 3679d548f11SAapo Vienamo 368e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 3699d548f11SAapo Vienamo } 370e5c63d91SLucas Stach 371a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 372ca5879d3SPavan Kunapuli } 373ca5879d3SPavan Kunapuli 374212b0cf1SAapo Vienamo static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 375212b0cf1SAapo Vienamo { 376212b0cf1SAapo Vienamo u32 val; 377212b0cf1SAapo Vienamo 378212b0cf1SAapo Vienamo /* 379212b0cf1SAapo Vienamo * Enable or disable the additional I/O pad used by the drive strength 380212b0cf1SAapo Vienamo * calibration process. 381212b0cf1SAapo Vienamo */ 382212b0cf1SAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 383212b0cf1SAapo Vienamo 384212b0cf1SAapo Vienamo if (enable) 385212b0cf1SAapo Vienamo val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 386212b0cf1SAapo Vienamo else 387212b0cf1SAapo Vienamo val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 388212b0cf1SAapo Vienamo 389212b0cf1SAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 390212b0cf1SAapo Vienamo 391212b0cf1SAapo Vienamo if (enable) 392212b0cf1SAapo Vienamo usleep_range(1, 2); 393212b0cf1SAapo Vienamo } 394212b0cf1SAapo Vienamo 39551b77c8eSAapo Vienamo static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 39651b77c8eSAapo Vienamo u16 pdpu) 39751b77c8eSAapo Vienamo { 39851b77c8eSAapo Vienamo u32 reg; 39951b77c8eSAapo Vienamo 40051b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 40151b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 40251b77c8eSAapo Vienamo reg |= pdpu; 40351b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 40451b77c8eSAapo Vienamo } 40551b77c8eSAapo Vienamo 406e5c63d91SLucas Stach static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 407e5c63d91SLucas Stach { 40851b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 40951b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 41051b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets offsets = 41151b77c8eSAapo Vienamo tegra_host->autocal_offsets; 41251b77c8eSAapo Vienamo struct mmc_ios *ios = &host->mmc->ios; 413887bda8fSAapo Vienamo bool card_clk_enabled; 41451b77c8eSAapo Vienamo u16 pdpu; 415e7c07148SAapo Vienamo u32 reg; 416e7c07148SAapo Vienamo int ret; 417e5c63d91SLucas Stach 41851b77c8eSAapo Vienamo switch (ios->timing) { 41951b77c8eSAapo Vienamo case MMC_TIMING_UHS_SDR104: 42051b77c8eSAapo Vienamo pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 42151b77c8eSAapo Vienamo break; 42251b77c8eSAapo Vienamo case MMC_TIMING_MMC_HS400: 42351b77c8eSAapo Vienamo pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 42451b77c8eSAapo Vienamo break; 42551b77c8eSAapo Vienamo default: 42651b77c8eSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 42751b77c8eSAapo Vienamo pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 42851b77c8eSAapo Vienamo else 42951b77c8eSAapo Vienamo pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 43051b77c8eSAapo Vienamo } 43151b77c8eSAapo Vienamo 43251b77c8eSAapo Vienamo tegra_sdhci_set_pad_autocal_offset(host, pdpu); 43351b77c8eSAapo Vienamo 434887bda8fSAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 435887bda8fSAapo Vienamo 436212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, true); 437212b0cf1SAapo Vienamo 438e7c07148SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 439e7c07148SAapo Vienamo reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 440e7c07148SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 441e5c63d91SLucas Stach 442e7c07148SAapo Vienamo usleep_range(1, 2); 443e7c07148SAapo Vienamo /* 10 ms timeout */ 444e7c07148SAapo Vienamo ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 445e7c07148SAapo Vienamo reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 446e7c07148SAapo Vienamo 1000, 10000); 447e7c07148SAapo Vienamo 448212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, false); 449212b0cf1SAapo Vienamo 450887bda8fSAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 451887bda8fSAapo Vienamo 45251b77c8eSAapo Vienamo if (ret) { 453e7c07148SAapo Vienamo dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 45451b77c8eSAapo Vienamo 45551b77c8eSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 45651b77c8eSAapo Vienamo pdpu = offsets.pull_down_1v8_timeout << 8 | 45751b77c8eSAapo Vienamo offsets.pull_up_1v8_timeout; 45851b77c8eSAapo Vienamo else 45951b77c8eSAapo Vienamo pdpu = offsets.pull_down_3v3_timeout << 8 | 46051b77c8eSAapo Vienamo offsets.pull_up_3v3_timeout; 46151b77c8eSAapo Vienamo 46251b77c8eSAapo Vienamo /* Disable automatic calibration and use fixed offsets */ 46351b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 46451b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_ENABLE; 46551b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 46651b77c8eSAapo Vienamo 46751b77c8eSAapo Vienamo tegra_sdhci_set_pad_autocal_offset(host, pdpu); 46851b77c8eSAapo Vienamo } 46951b77c8eSAapo Vienamo } 47051b77c8eSAapo Vienamo 47151b77c8eSAapo Vienamo static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 47251b77c8eSAapo Vienamo { 47351b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 47451b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 47551b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets *autocal = 47651b77c8eSAapo Vienamo &tegra_host->autocal_offsets; 47751b77c8eSAapo Vienamo int err; 47851b77c8eSAapo Vienamo 47951b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 48051b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3", 48151b77c8eSAapo Vienamo &autocal->pull_up_3v3); 48251b77c8eSAapo Vienamo if (err) 48351b77c8eSAapo Vienamo autocal->pull_up_3v3 = 0; 48451b77c8eSAapo Vienamo 48551b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 48651b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3", 48751b77c8eSAapo Vienamo &autocal->pull_down_3v3); 48851b77c8eSAapo Vienamo if (err) 48951b77c8eSAapo Vienamo autocal->pull_down_3v3 = 0; 49051b77c8eSAapo Vienamo 49151b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 49251b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8", 49351b77c8eSAapo Vienamo &autocal->pull_up_1v8); 49451b77c8eSAapo Vienamo if (err) 49551b77c8eSAapo Vienamo autocal->pull_up_1v8 = 0; 49651b77c8eSAapo Vienamo 49751b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 49851b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8", 49951b77c8eSAapo Vienamo &autocal->pull_down_1v8); 50051b77c8eSAapo Vienamo if (err) 50151b77c8eSAapo Vienamo autocal->pull_down_1v8 = 0; 50251b77c8eSAapo Vienamo 50351b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 50451b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 50551b77c8eSAapo Vienamo &autocal->pull_up_3v3); 50651b77c8eSAapo Vienamo if (err) 50751b77c8eSAapo Vienamo autocal->pull_up_3v3_timeout = 0; 50851b77c8eSAapo Vienamo 50951b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 51051b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 51151b77c8eSAapo Vienamo &autocal->pull_down_3v3); 51251b77c8eSAapo Vienamo if (err) 51351b77c8eSAapo Vienamo autocal->pull_down_3v3_timeout = 0; 51451b77c8eSAapo Vienamo 51551b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 51651b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 51751b77c8eSAapo Vienamo &autocal->pull_up_1v8); 51851b77c8eSAapo Vienamo if (err) 51951b77c8eSAapo Vienamo autocal->pull_up_1v8_timeout = 0; 52051b77c8eSAapo Vienamo 52151b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 52251b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 52351b77c8eSAapo Vienamo &autocal->pull_down_1v8); 52451b77c8eSAapo Vienamo if (err) 52551b77c8eSAapo Vienamo autocal->pull_down_1v8_timeout = 0; 52651b77c8eSAapo Vienamo 52751b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 52851b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-sdr104", 52951b77c8eSAapo Vienamo &autocal->pull_up_sdr104); 53051b77c8eSAapo Vienamo if (err) 53151b77c8eSAapo Vienamo autocal->pull_up_sdr104 = autocal->pull_up_1v8; 53251b77c8eSAapo Vienamo 53351b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 53451b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-sdr104", 53551b77c8eSAapo Vienamo &autocal->pull_down_sdr104); 53651b77c8eSAapo Vienamo if (err) 53751b77c8eSAapo Vienamo autocal->pull_down_sdr104 = autocal->pull_down_1v8; 53851b77c8eSAapo Vienamo 53951b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 54051b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-hs400", 54151b77c8eSAapo Vienamo &autocal->pull_up_hs400); 54251b77c8eSAapo Vienamo if (err) 54351b77c8eSAapo Vienamo autocal->pull_up_hs400 = autocal->pull_up_1v8; 54451b77c8eSAapo Vienamo 54551b77c8eSAapo Vienamo err = device_property_read_u32(host->mmc->parent, 54651b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-hs400", 54751b77c8eSAapo Vienamo &autocal->pull_down_hs400); 54851b77c8eSAapo Vienamo if (err) 54951b77c8eSAapo Vienamo autocal->pull_down_hs400 = autocal->pull_down_1v8; 550e5c63d91SLucas Stach } 551e5c63d91SLucas Stach 552f5313aaaSAapo Vienamo static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 55385c0da17SAapo Vienamo { 55485c0da17SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 55585c0da17SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 55685c0da17SAapo Vienamo int err; 55785c0da17SAapo Vienamo 55885c0da17SAapo Vienamo err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 55985c0da17SAapo Vienamo &tegra_host->default_tap); 56085c0da17SAapo Vienamo if (err) 56185c0da17SAapo Vienamo tegra_host->default_tap = 0; 56285c0da17SAapo Vienamo 56385c0da17SAapo Vienamo err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 56485c0da17SAapo Vienamo &tegra_host->default_trim); 56585c0da17SAapo Vienamo if (err) 56685c0da17SAapo Vienamo tegra_host->default_trim = 0; 567f5313aaaSAapo Vienamo 568f5313aaaSAapo Vienamo err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 569f5313aaaSAapo Vienamo &tegra_host->dqs_trim); 570f5313aaaSAapo Vienamo if (err) 571f5313aaaSAapo Vienamo tegra_host->dqs_trim = 0x11; 57285c0da17SAapo Vienamo } 57385c0da17SAapo Vienamo 574a8e326a9SLucas Stach static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 575a8e326a9SLucas Stach { 576a8e326a9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 5770734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 578a8e326a9SLucas Stach unsigned long host_clk; 579a8e326a9SLucas Stach 580a8e326a9SLucas Stach if (!clock) 5813491b690SLucas Stach return sdhci_set_clock(host, clock); 582a8e326a9SLucas Stach 58357d1654eSAapo Vienamo /* 58457d1654eSAapo Vienamo * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 58557d1654eSAapo Vienamo * divider to be configured to divided the host clock by two. The SDHCI 58657d1654eSAapo Vienamo * clock divider is calculated as part of sdhci_set_clock() by 58757d1654eSAapo Vienamo * sdhci_calc_clk(). The divider is calculated from host->max_clk and 58857d1654eSAapo Vienamo * the requested clock rate. 58957d1654eSAapo Vienamo * 59057d1654eSAapo Vienamo * By setting the host->max_clk to clock * 2 the divider calculation 59157d1654eSAapo Vienamo * will always result in the correct value for DDR50/52 modes, 59257d1654eSAapo Vienamo * regardless of clock rate rounding, which may happen if the value 59357d1654eSAapo Vienamo * from clk_get_rate() is used. 59457d1654eSAapo Vienamo */ 595a8e326a9SLucas Stach host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 596a8e326a9SLucas Stach clk_set_rate(pltfm_host->clk, host_clk); 59757d1654eSAapo Vienamo if (tegra_host->ddr_signaling) 59857d1654eSAapo Vienamo host->max_clk = host_clk; 59957d1654eSAapo Vienamo else 600a8e326a9SLucas Stach host->max_clk = clk_get_rate(pltfm_host->clk); 601a8e326a9SLucas Stach 602e5c63d91SLucas Stach sdhci_set_clock(host, clock); 603e5c63d91SLucas Stach 604e5c63d91SLucas Stach if (tegra_host->pad_calib_required) { 605e5c63d91SLucas Stach tegra_sdhci_pad_autocalib(host); 606e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 607e5c63d91SLucas Stach } 608a8e326a9SLucas Stach } 609a8e326a9SLucas Stach 61044350993SAapo Vienamo static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 61144350993SAapo Vienamo { 61244350993SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 61344350993SAapo Vienamo 61444350993SAapo Vienamo return clk_round_rate(pltfm_host->clk, UINT_MAX); 61544350993SAapo Vienamo } 61644350993SAapo Vienamo 617f5313aaaSAapo Vienamo static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 618f5313aaaSAapo Vienamo { 619f5313aaaSAapo Vienamo u32 val; 620f5313aaaSAapo Vienamo 621f5313aaaSAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 622f5313aaaSAapo Vienamo val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 623f5313aaaSAapo Vienamo val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 624f5313aaaSAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 625f5313aaaSAapo Vienamo } 626f5313aaaSAapo Vienamo 627c2c09678SAapo Vienamo static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 628c2c09678SAapo Vienamo unsigned timing) 629c3c2384cSLucas Stach { 630d4501d8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 631d4501d8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 632c2c09678SAapo Vienamo bool set_default_tap = false; 633f5313aaaSAapo Vienamo bool set_dqs_trim = false; 634c3c2384cSLucas Stach 635c2c09678SAapo Vienamo switch (timing) { 636c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR50: 637c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR104: 638c2c09678SAapo Vienamo case MMC_TIMING_MMC_HS200: 639c2c09678SAapo Vienamo /* Don't set default tap on tunable modes. */ 640c2c09678SAapo Vienamo break; 641f5313aaaSAapo Vienamo case MMC_TIMING_MMC_HS400: 642f5313aaaSAapo Vienamo set_dqs_trim = true; 643f5313aaaSAapo Vienamo break; 644c2c09678SAapo Vienamo case MMC_TIMING_MMC_DDR52: 645c2c09678SAapo Vienamo case MMC_TIMING_UHS_DDR50: 646c2c09678SAapo Vienamo tegra_host->ddr_signaling = true; 647c2c09678SAapo Vienamo set_default_tap = true; 648c2c09678SAapo Vienamo break; 649c2c09678SAapo Vienamo default: 650c2c09678SAapo Vienamo set_default_tap = true; 651c2c09678SAapo Vienamo break; 652d4501d8eSAapo Vienamo } 653c2c09678SAapo Vienamo 654c2c09678SAapo Vienamo sdhci_set_uhs_signaling(host, timing); 655c2c09678SAapo Vienamo 656c2c09678SAapo Vienamo tegra_sdhci_pad_autocalib(host); 657c2c09678SAapo Vienamo 658c2c09678SAapo Vienamo if (set_default_tap) 659c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 660f5313aaaSAapo Vienamo 661f5313aaaSAapo Vienamo if (set_dqs_trim) 662f5313aaaSAapo Vienamo tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 663c3c2384cSLucas Stach } 664c3c2384cSLucas Stach 665c3c2384cSLucas Stach static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 666c3c2384cSLucas Stach { 667c3c2384cSLucas Stach unsigned int min, max; 668c3c2384cSLucas Stach 669c3c2384cSLucas Stach /* 670c3c2384cSLucas Stach * Start search for minimum tap value at 10, as smaller values are 671c3c2384cSLucas Stach * may wrongly be reported as working but fail at higher speeds, 672c3c2384cSLucas Stach * according to the TRM. 673c3c2384cSLucas Stach */ 674c3c2384cSLucas Stach min = 10; 675c3c2384cSLucas Stach while (min < 255) { 676c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min); 677c3c2384cSLucas Stach if (!mmc_send_tuning(host->mmc, opcode, NULL)) 678c3c2384cSLucas Stach break; 679c3c2384cSLucas Stach min++; 680c3c2384cSLucas Stach } 681c3c2384cSLucas Stach 682c3c2384cSLucas Stach /* Find the maximum tap value that still passes. */ 683c3c2384cSLucas Stach max = min + 1; 684c3c2384cSLucas Stach while (max < 255) { 685c3c2384cSLucas Stach tegra_sdhci_set_tap(host, max); 686c3c2384cSLucas Stach if (mmc_send_tuning(host->mmc, opcode, NULL)) { 687c3c2384cSLucas Stach max--; 688c3c2384cSLucas Stach break; 689c3c2384cSLucas Stach } 690c3c2384cSLucas Stach max++; 691c3c2384cSLucas Stach } 692c3c2384cSLucas Stach 693c3c2384cSLucas Stach /* The TRM states the ideal tap value is at 75% in the passing range. */ 694c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 695c3c2384cSLucas Stach 696c3c2384cSLucas Stach return mmc_send_tuning(host->mmc, opcode, NULL); 697c3c2384cSLucas Stach } 698c3c2384cSLucas Stach 69986ac2f8bSAapo Vienamo static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 70086ac2f8bSAapo Vienamo { 70186ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 70286ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 70386ac2f8bSAapo Vienamo int ret; 70486ac2f8bSAapo Vienamo 70586ac2f8bSAapo Vienamo if (!tegra_host->pad_control_available) 70686ac2f8bSAapo Vienamo return 0; 70786ac2f8bSAapo Vienamo 70886ac2f8bSAapo Vienamo if (voltage == MMC_SIGNAL_VOLTAGE_180) { 70986ac2f8bSAapo Vienamo ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 71086ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8); 71186ac2f8bSAapo Vienamo if (ret < 0) 71286ac2f8bSAapo Vienamo dev_err(mmc_dev(host->mmc), 71386ac2f8bSAapo Vienamo "setting 1.8V failed, ret: %d\n", ret); 71486ac2f8bSAapo Vienamo } else { 71586ac2f8bSAapo Vienamo ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 71686ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3); 71786ac2f8bSAapo Vienamo if (ret < 0) 71886ac2f8bSAapo Vienamo dev_err(mmc_dev(host->mmc), 71986ac2f8bSAapo Vienamo "setting 3.3V failed, ret: %d\n", ret); 72086ac2f8bSAapo Vienamo } 72186ac2f8bSAapo Vienamo 72286ac2f8bSAapo Vienamo return ret; 72386ac2f8bSAapo Vienamo } 72486ac2f8bSAapo Vienamo 72586ac2f8bSAapo Vienamo static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 72686ac2f8bSAapo Vienamo struct mmc_ios *ios) 72786ac2f8bSAapo Vienamo { 72886ac2f8bSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 72944babea2SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73044babea2SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 73186ac2f8bSAapo Vienamo int ret = 0; 73286ac2f8bSAapo Vienamo 73386ac2f8bSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 73486ac2f8bSAapo Vienamo ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 73586ac2f8bSAapo Vienamo if (ret < 0) 73686ac2f8bSAapo Vienamo return ret; 73786ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 73886ac2f8bSAapo Vienamo } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 73986ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 74086ac2f8bSAapo Vienamo if (ret < 0) 74186ac2f8bSAapo Vienamo return ret; 74286ac2f8bSAapo Vienamo ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 74386ac2f8bSAapo Vienamo } 74486ac2f8bSAapo Vienamo 74544babea2SAapo Vienamo if (tegra_host->pad_calib_required) 74644babea2SAapo Vienamo tegra_sdhci_pad_autocalib(host); 74744babea2SAapo Vienamo 74886ac2f8bSAapo Vienamo return ret; 74986ac2f8bSAapo Vienamo } 75086ac2f8bSAapo Vienamo 75186ac2f8bSAapo Vienamo static int tegra_sdhci_init_pinctrl_info(struct device *dev, 75286ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host) 75386ac2f8bSAapo Vienamo { 75486ac2f8bSAapo Vienamo tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 75586ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 75686ac2f8bSAapo Vienamo dev_dbg(dev, "No pinctrl info, err: %ld\n", 75786ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_sdmmc)); 75886ac2f8bSAapo Vienamo return -1; 75986ac2f8bSAapo Vienamo } 76086ac2f8bSAapo Vienamo 76186ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3 = 76286ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 76386ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 76486ac2f8bSAapo Vienamo dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 76586ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 76686ac2f8bSAapo Vienamo return -1; 76786ac2f8bSAapo Vienamo } 76886ac2f8bSAapo Vienamo 76986ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8 = 77086ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 77186ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 77286ac2f8bSAapo Vienamo dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 77386ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 77486ac2f8bSAapo Vienamo return -1; 77586ac2f8bSAapo Vienamo } 77686ac2f8bSAapo Vienamo 77786ac2f8bSAapo Vienamo tegra_host->pad_control_available = true; 77886ac2f8bSAapo Vienamo 77986ac2f8bSAapo Vienamo return 0; 78086ac2f8bSAapo Vienamo } 78186ac2f8bSAapo Vienamo 782e5c63d91SLucas Stach static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 783e5c63d91SLucas Stach { 784e5c63d91SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 785e5c63d91SLucas Stach struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 786e5c63d91SLucas Stach const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 787e5c63d91SLucas Stach 788e5c63d91SLucas Stach if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 789e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 790e5c63d91SLucas Stach } 791e5c63d91SLucas Stach 792c915568dSLars-Peter Clausen static const struct sdhci_ops tegra_sdhci_ops = { 79385d6509dSShawn Guo .get_ro = tegra_sdhci_get_ro, 79485d6509dSShawn Guo .read_w = tegra_sdhci_readw, 79585d6509dSShawn Guo .write_l = tegra_sdhci_writel, 796a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 79714b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 79803231f9bSRussell King .reset = tegra_sdhci_reset, 799c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 800a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 801e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 80244350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 80385d6509dSShawn Guo }; 80403d2bfc8SOlof Johansson 8051db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 80685d6509dSShawn Guo .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 80785d6509dSShawn Guo SDHCI_QUIRK_SINGLE_POWER_WRITE | 80885d6509dSShawn Guo SDHCI_QUIRK_NO_HISPD_BIT | 809f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 810f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 81185d6509dSShawn Guo .ops = &tegra_sdhci_ops, 81285d6509dSShawn Guo }; 81385d6509dSShawn Guo 814d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 8153e44a1a7SStephen Warren .pdata = &sdhci_tegra20_pdata, 8163e44a1a7SStephen Warren .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 8173e44a1a7SStephen Warren NVQUIRK_ENABLE_BLOCK_GAP_DET, 8183e44a1a7SStephen Warren }; 8193e44a1a7SStephen Warren 8201db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 8213e44a1a7SStephen Warren .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 8223e44a1a7SStephen Warren SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 8233e44a1a7SStephen Warren SDHCI_QUIRK_SINGLE_POWER_WRITE | 8243e44a1a7SStephen Warren SDHCI_QUIRK_NO_HISPD_BIT | 825f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 826f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 827127407e3SStefan Agner .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 828726df1d5SStefan Agner SDHCI_QUIRK2_BROKEN_HS200 | 829726df1d5SStefan Agner /* 830726df1d5SStefan Agner * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 831726df1d5SStefan Agner * though no command operation was in progress." 832726df1d5SStefan Agner * 833726df1d5SStefan Agner * The exact reason is unknown, as the same hardware seems 834726df1d5SStefan Agner * to support Auto CMD23 on a downstream 3.1 kernel. 835726df1d5SStefan Agner */ 836726df1d5SStefan Agner SDHCI_QUIRK2_ACMD23_BROKEN, 8373e44a1a7SStephen Warren .ops = &tegra_sdhci_ops, 8383e44a1a7SStephen Warren }; 8393e44a1a7SStephen Warren 840d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 8413e44a1a7SStephen Warren .pdata = &sdhci_tegra30_pdata, 8423145351aSAndrew Bresticker .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 8437ad2ed1dSLucas Stach NVQUIRK_ENABLE_SDR50 | 844e5c63d91SLucas Stach NVQUIRK_ENABLE_SDR104 | 845e5c63d91SLucas Stach NVQUIRK_HAS_PADCALIB, 8463e44a1a7SStephen Warren }; 8473e44a1a7SStephen Warren 84801df7ecdSRhyland Klein static const struct sdhci_ops tegra114_sdhci_ops = { 84901df7ecdSRhyland Klein .get_ro = tegra_sdhci_get_ro, 85001df7ecdSRhyland Klein .read_w = tegra_sdhci_readw, 85101df7ecdSRhyland Klein .write_w = tegra_sdhci_writew, 85201df7ecdSRhyland Klein .write_l = tegra_sdhci_writel, 853a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 85414b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 85501df7ecdSRhyland Klein .reset = tegra_sdhci_reset, 856c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 857a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 858e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 85944350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 86001df7ecdSRhyland Klein }; 86101df7ecdSRhyland Klein 8621db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 8635ebf2552SRhyland Klein .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 8645ebf2552SRhyland Klein SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 8655ebf2552SRhyland Klein SDHCI_QUIRK_SINGLE_POWER_WRITE | 8665ebf2552SRhyland Klein SDHCI_QUIRK_NO_HISPD_BIT | 867f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 868f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 869a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 87001df7ecdSRhyland Klein .ops = &tegra114_sdhci_ops, 8715ebf2552SRhyland Klein }; 8725ebf2552SRhyland Klein 873d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 8745ebf2552SRhyland Klein .pdata = &sdhci_tegra114_pdata, 8757bf037d6SJon Hunter }; 8767bf037d6SJon Hunter 8774ae12588SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 8784ae12588SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 8794ae12588SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 8804ae12588SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 8814ae12588SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 8824ae12588SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 8834ae12588SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 8844ae12588SThierry Reding .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 8854ae12588SThierry Reding /* 8864ae12588SThierry Reding * The TRM states that the SD/MMC controller found on 8874ae12588SThierry Reding * Tegra124 can address 34 bits (the maximum supported by 8884ae12588SThierry Reding * the Tegra memory controller), but tests show that DMA 8894ae12588SThierry Reding * to or from above 4 GiB doesn't work. This is possibly 8904ae12588SThierry Reding * caused by missing programming, though it's not obvious 8914ae12588SThierry Reding * what sequence is required. Mark 64-bit DMA broken for 8924ae12588SThierry Reding * now to fix this for existing users (e.g. Nyan boards). 8934ae12588SThierry Reding */ 8944ae12588SThierry Reding SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 8954ae12588SThierry Reding .ops = &tegra114_sdhci_ops, 8964ae12588SThierry Reding }; 8974ae12588SThierry Reding 8984ae12588SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 8994ae12588SThierry Reding .pdata = &sdhci_tegra124_pdata, 9004ae12588SThierry Reding }; 9014ae12588SThierry Reding 9021070e83aSAapo Vienamo static const struct sdhci_ops tegra210_sdhci_ops = { 9031070e83aSAapo Vienamo .get_ro = tegra_sdhci_get_ro, 9041070e83aSAapo Vienamo .read_w = tegra_sdhci_readw, 90538a284d9SAapo Vienamo .write_w = tegra210_sdhci_writew, 9061070e83aSAapo Vienamo .write_l = tegra_sdhci_writel, 9071070e83aSAapo Vienamo .set_clock = tegra_sdhci_set_clock, 9081070e83aSAapo Vienamo .set_bus_width = sdhci_set_bus_width, 9091070e83aSAapo Vienamo .reset = tegra_sdhci_reset, 9101070e83aSAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 9111070e83aSAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 9121070e83aSAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 9131070e83aSAapo Vienamo }; 9141070e83aSAapo Vienamo 915b5a84ecfSThierry Reding static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 916b5a84ecfSThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 917b5a84ecfSThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 918b5a84ecfSThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 919b5a84ecfSThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 920a8e326a9SLucas Stach SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 921a8e326a9SLucas Stach SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 922a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 9231070e83aSAapo Vienamo .ops = &tegra210_sdhci_ops, 924b5a84ecfSThierry Reding }; 925b5a84ecfSThierry Reding 926b5a84ecfSThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 927b5a84ecfSThierry Reding .pdata = &sdhci_tegra210_pdata, 928d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 929d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 9303559d4a6SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 9313559d4a6SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 9323559d4a6SAapo Vienamo NVQUIRK_ENABLE_SDR104, 933b5a84ecfSThierry Reding }; 934b5a84ecfSThierry Reding 93538a284d9SAapo Vienamo static const struct sdhci_ops tegra186_sdhci_ops = { 93638a284d9SAapo Vienamo .get_ro = tegra_sdhci_get_ro, 93738a284d9SAapo Vienamo .read_w = tegra_sdhci_readw, 93838a284d9SAapo Vienamo .write_l = tegra_sdhci_writel, 93938a284d9SAapo Vienamo .set_clock = tegra_sdhci_set_clock, 94038a284d9SAapo Vienamo .set_bus_width = sdhci_set_bus_width, 94138a284d9SAapo Vienamo .reset = tegra_sdhci_reset, 94238a284d9SAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 94338a284d9SAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 94438a284d9SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 94538a284d9SAapo Vienamo }; 94638a284d9SAapo Vienamo 9474346b7c7SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 9484346b7c7SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 9494346b7c7SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 9504346b7c7SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 9514346b7c7SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 9524346b7c7SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 9534346b7c7SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 95468481a7eSKrishna Reddy .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 95568481a7eSKrishna Reddy /* SDHCI controllers on Tegra186 support 40-bit addressing. 95668481a7eSKrishna Reddy * IOVA addresses are 48-bit wide on Tegra186. 95768481a7eSKrishna Reddy * With 64-bit dma mask used for SDHCI, accesses can 95868481a7eSKrishna Reddy * be broken. Disable 64-bit dma, which would fall back 95968481a7eSKrishna Reddy * to 32-bit dma mask. Ideally 40-bit dma mask would work, 96068481a7eSKrishna Reddy * But it is not supported as of now. 96168481a7eSKrishna Reddy */ 96268481a7eSKrishna Reddy SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 96338a284d9SAapo Vienamo .ops = &tegra186_sdhci_ops, 9644346b7c7SThierry Reding }; 9654346b7c7SThierry Reding 9664346b7c7SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 9674346b7c7SThierry Reding .pdata = &sdhci_tegra186_pdata, 968d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 969d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 9702ad50051SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 9712ad50051SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 9722ad50051SAapo Vienamo NVQUIRK_ENABLE_SDR104, 9734346b7c7SThierry Reding }; 9744346b7c7SThierry Reding 975498d83e7SBill Pemberton static const struct of_device_id sdhci_tegra_dt_match[] = { 9764346b7c7SThierry Reding { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 977b5a84ecfSThierry Reding { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 9784ae12588SThierry Reding { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 9795ebf2552SRhyland Klein { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 9803e44a1a7SStephen Warren { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 9813e44a1a7SStephen Warren { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 982275173b2SGrant Likely {} 983275173b2SGrant Likely }; 984e4404fabSArnd Bergmann MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 985275173b2SGrant Likely 986c3be1efdSBill Pemberton static int sdhci_tegra_probe(struct platform_device *pdev) 98703d2bfc8SOlof Johansson { 9883e44a1a7SStephen Warren const struct of_device_id *match; 9893e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 9903e44a1a7SStephen Warren struct sdhci_host *host; 99185d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 9923e44a1a7SStephen Warren struct sdhci_tegra *tegra_host; 99303d2bfc8SOlof Johansson struct clk *clk; 99403d2bfc8SOlof Johansson int rc; 99503d2bfc8SOlof Johansson 9963e44a1a7SStephen Warren match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 997b37f9d98SJoseph Lo if (!match) 998b37f9d98SJoseph Lo return -EINVAL; 9993e44a1a7SStephen Warren soc_data = match->data; 10003e44a1a7SStephen Warren 10010734e79cSJisheng Zhang host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 100285d6509dSShawn Guo if (IS_ERR(host)) 100385d6509dSShawn Guo return PTR_ERR(host); 100485d6509dSShawn Guo pltfm_host = sdhci_priv(host); 100585d6509dSShawn Guo 10060734e79cSJisheng Zhang tegra_host = sdhci_pltfm_priv(pltfm_host); 1007a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 1008e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 100986ac2f8bSAapo Vienamo tegra_host->pad_control_available = false; 10103e44a1a7SStephen Warren tegra_host->soc_data = soc_data; 1011275173b2SGrant Likely 101286ac2f8bSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 101386ac2f8bSAapo Vienamo rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 101486ac2f8bSAapo Vienamo if (rc == 0) 101586ac2f8bSAapo Vienamo host->mmc_host_ops.start_signal_voltage_switch = 101686ac2f8bSAapo Vienamo sdhci_tegra_start_signal_voltage_switch; 101786ac2f8bSAapo Vienamo } 101886ac2f8bSAapo Vienamo 1019dfc9700cSAapo Vienamo host->mmc_host_ops.hs400_enhanced_strobe = 1020dfc9700cSAapo Vienamo tegra_sdhci_hs400_enhanced_strobe; 1021dfc9700cSAapo Vienamo 10222391b340SMylene JOSSERAND rc = mmc_of_parse(host->mmc); 102347caa84fSSimon Baatz if (rc) 102447caa84fSSimon Baatz goto err_parse_dt; 10250e786102SStephen Warren 10267ad2ed1dSLucas Stach if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1027c3c2384cSLucas Stach host->mmc->caps |= MMC_CAP_1_8V_DDR; 1028c3c2384cSLucas Stach 102951b77c8eSAapo Vienamo tegra_sdhci_parse_pad_autocal_dt(host); 103051b77c8eSAapo Vienamo 1031f5313aaaSAapo Vienamo tegra_sdhci_parse_tap_and_trim(host); 103285c0da17SAapo Vienamo 10332391b340SMylene JOSSERAND tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 10342391b340SMylene JOSSERAND GPIOD_OUT_HIGH); 10352391b340SMylene JOSSERAND if (IS_ERR(tegra_host->power_gpio)) { 10362391b340SMylene JOSSERAND rc = PTR_ERR(tegra_host->power_gpio); 103785d6509dSShawn Guo goto err_power_req; 103803d2bfc8SOlof Johansson } 103903d2bfc8SOlof Johansson 1040e4f79d9cSKevin Hao clk = devm_clk_get(mmc_dev(host->mmc), NULL); 104103d2bfc8SOlof Johansson if (IS_ERR(clk)) { 104203d2bfc8SOlof Johansson dev_err(mmc_dev(host->mmc), "clk err\n"); 104303d2bfc8SOlof Johansson rc = PTR_ERR(clk); 104485d6509dSShawn Guo goto err_clk_get; 104503d2bfc8SOlof Johansson } 10461e674bc6SPrashant Gaikwad clk_prepare_enable(clk); 104703d2bfc8SOlof Johansson pltfm_host->clk = clk; 104803d2bfc8SOlof Johansson 10492cd6c49dSPhilipp Zabel tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 10502cd6c49dSPhilipp Zabel "sdhci"); 105120567be9SThierry Reding if (IS_ERR(tegra_host->rst)) { 105220567be9SThierry Reding rc = PTR_ERR(tegra_host->rst); 105320567be9SThierry Reding dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 105420567be9SThierry Reding goto err_rst_get; 105520567be9SThierry Reding } 105620567be9SThierry Reding 105720567be9SThierry Reding rc = reset_control_assert(tegra_host->rst); 105820567be9SThierry Reding if (rc) 105920567be9SThierry Reding goto err_rst_get; 106020567be9SThierry Reding 106120567be9SThierry Reding usleep_range(2000, 4000); 106220567be9SThierry Reding 106320567be9SThierry Reding rc = reset_control_deassert(tegra_host->rst); 106420567be9SThierry Reding if (rc) 106520567be9SThierry Reding goto err_rst_get; 106620567be9SThierry Reding 106720567be9SThierry Reding usleep_range(2000, 4000); 106820567be9SThierry Reding 106985d6509dSShawn Guo rc = sdhci_add_host(host); 107085d6509dSShawn Guo if (rc) 107185d6509dSShawn Guo goto err_add_host; 107285d6509dSShawn Guo 107303d2bfc8SOlof Johansson return 0; 107403d2bfc8SOlof Johansson 107585d6509dSShawn Guo err_add_host: 107620567be9SThierry Reding reset_control_assert(tegra_host->rst); 107720567be9SThierry Reding err_rst_get: 10781e674bc6SPrashant Gaikwad clk_disable_unprepare(pltfm_host->clk); 107985d6509dSShawn Guo err_clk_get: 108085d6509dSShawn Guo err_power_req: 108147caa84fSSimon Baatz err_parse_dt: 108285d6509dSShawn Guo sdhci_pltfm_free(pdev); 108303d2bfc8SOlof Johansson return rc; 108403d2bfc8SOlof Johansson } 108503d2bfc8SOlof Johansson 108620567be9SThierry Reding static int sdhci_tegra_remove(struct platform_device *pdev) 108720567be9SThierry Reding { 108820567be9SThierry Reding struct sdhci_host *host = platform_get_drvdata(pdev); 108920567be9SThierry Reding struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109020567be9SThierry Reding struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 109120567be9SThierry Reding 109220567be9SThierry Reding sdhci_remove_host(host, 0); 109320567be9SThierry Reding 109420567be9SThierry Reding reset_control_assert(tegra_host->rst); 109520567be9SThierry Reding usleep_range(2000, 4000); 109620567be9SThierry Reding clk_disable_unprepare(pltfm_host->clk); 109720567be9SThierry Reding 109820567be9SThierry Reding sdhci_pltfm_free(pdev); 109920567be9SThierry Reding 110020567be9SThierry Reding return 0; 110120567be9SThierry Reding } 110220567be9SThierry Reding 110385d6509dSShawn Guo static struct platform_driver sdhci_tegra_driver = { 110485d6509dSShawn Guo .driver = { 110585d6509dSShawn Guo .name = "sdhci-tegra", 1106275173b2SGrant Likely .of_match_table = sdhci_tegra_dt_match, 1107fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops, 110885d6509dSShawn Guo }, 110985d6509dSShawn Guo .probe = sdhci_tegra_probe, 111020567be9SThierry Reding .remove = sdhci_tegra_remove, 111103d2bfc8SOlof Johansson }; 111203d2bfc8SOlof Johansson 1113d1f81a64SAxel Lin module_platform_driver(sdhci_tegra_driver); 111485d6509dSShawn Guo 111585d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Tegra"); 111685d6509dSShawn Guo MODULE_AUTHOR("Google, Inc."); 111785d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1118