19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 203d2bfc8SOlof Johansson /* 303d2bfc8SOlof Johansson * Copyright (C) 2010 Google, Inc. 403d2bfc8SOlof Johansson */ 503d2bfc8SOlof Johansson 6e5c63d91SLucas Stach #include <linux/delay.h> 7b960bc44SNicolin Chen #include <linux/dma-mapping.h> 803d2bfc8SOlof Johansson #include <linux/err.h> 996547f5dSPaul Gortmaker #include <linux/module.h> 1003d2bfc8SOlof Johansson #include <linux/init.h> 11e7c07148SAapo Vienamo #include <linux/iopoll.h> 1203d2bfc8SOlof Johansson #include <linux/platform_device.h> 1303d2bfc8SOlof Johansson #include <linux/clk.h> 1403d2bfc8SOlof Johansson #include <linux/io.h> 1555cd65e4SStephen Warren #include <linux/of.h> 163e44a1a7SStephen Warren #include <linux/of_device.h> 1786ac2f8bSAapo Vienamo #include <linux/pinctrl/consumer.h> 18*d618978dSDmitry Osipenko #include <linux/pm_opp.h> 19*d618978dSDmitry Osipenko #include <linux/pm_runtime.h> 2086ac2f8bSAapo Vienamo #include <linux/regulator/consumer.h> 2120567be9SThierry Reding #include <linux/reset.h> 2203d2bfc8SOlof Johansson #include <linux/mmc/card.h> 2303d2bfc8SOlof Johansson #include <linux/mmc/host.h> 24c3c2384cSLucas Stach #include <linux/mmc/mmc.h> 250aacd23fSJoseph Lo #include <linux/mmc/slot-gpio.h> 262391b340SMylene JOSSERAND #include <linux/gpio/consumer.h> 2761dad40eSAapo Vienamo #include <linux/ktime.h> 2803d2bfc8SOlof Johansson 29*d618978dSDmitry Osipenko #include <soc/tegra/common.h> 30*d618978dSDmitry Osipenko 3103d2bfc8SOlof Johansson #include "sdhci-pltfm.h" 323c4019f9SSowjanya Komatineni #include "cqhci.h" 3303d2bfc8SOlof Johansson 34ca5879d3SPavan Kunapuli /* Tegra SDHOST controller vendor register definitions */ 3574cd42bcSLucas Stach #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 36c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 37c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 3841a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 3941a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 40c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 4174cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 4274cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 4374cd42bcSLucas Stach 44dfc9700cSAapo Vienamo #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 45dfc9700cSAapo Vienamo #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 46dfc9700cSAapo Vienamo 47f5313aaaSAapo Vienamo #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 48f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 49f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 50f5313aaaSAapo Vienamo 51ca5879d3SPavan Kunapuli #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 525e958e4aSSowjanya Komatineni #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 533145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 543145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 55ca5879d3SPavan Kunapuli #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 563145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 57ca5879d3SPavan Kunapuli 58bc5568bfSAapo Vienamo #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 59bc5568bfSAapo Vienamo #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 60bc5568bfSAapo Vienamo 61bc5568bfSAapo Vienamo #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 62bc5568bfSAapo Vienamo #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 63bc5568bfSAapo Vienamo 64d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 65d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 66ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 67ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 68ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 69ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 70ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 71ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 72ea8fc595SSowjanya Komatineni #define TRIES_128 2 73ea8fc595SSowjanya Komatineni #define TRIES_256 4 74ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 75ea8fc595SSowjanya Komatineni 76ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 77ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 78ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 79ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 80ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 81ea8fc595SSowjanya Komatineni #define TUNING_WORD_BIT_SIZE 32 82d4501d8eSAapo Vienamo 83e5c63d91SLucas Stach #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 84e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_START BIT(31) 85e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_ENABLE BIT(29) 8651b77c8eSAapo Vienamo #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 87e5c63d91SLucas Stach 889d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 899d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 909d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 91212b0cf1SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 92de25fa5aSSowjanya Komatineni #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 939d548f11SAapo Vienamo 94e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 95e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 96e7c07148SAapo Vienamo 973e44a1a7SStephen Warren #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 983e44a1a7SStephen Warren #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 99ca5879d3SPavan Kunapuli #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 1007ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR50 BIT(3) 1017ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR104 BIT(4) 1027ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_DDR50 BIT(5) 10347fad46bSSowjanya Komatineni /* 10447fad46bSSowjanya Komatineni * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads 10547fad46bSSowjanya Komatineni * drive strength. 10647fad46bSSowjanya Komatineni */ 107e5c63d91SLucas Stach #define NVQUIRK_HAS_PADCALIB BIT(6) 10847fad46bSSowjanya Komatineni /* 10947fad46bSSowjanya Komatineni * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. 11047fad46bSSowjanya Komatineni * 3V3/1V8 pad selection happens through pinctrl state selection depending 11147fad46bSSowjanya Komatineni * on the signaling mode. 11247fad46bSSowjanya Komatineni */ 11386ac2f8bSAapo Vienamo #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 114d4501d8eSAapo Vienamo #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 115c6e7ab90SSowjanya Komatineni #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 1163e44a1a7SStephen Warren 1178048822bSSowjanya Komatineni /* 1188048822bSSowjanya Komatineni * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra 1198048822bSSowjanya Komatineni * SDMMC hardware data timeout. 1208048822bSSowjanya Komatineni */ 1218048822bSSowjanya Komatineni #define NVQUIRK_HAS_TMCLK BIT(10) 1228048822bSSowjanya Komatineni 1231743fa54SDmitry Osipenko #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 1241743fa54SDmitry Osipenko 1253c4019f9SSowjanya Komatineni /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 1263c4019f9SSowjanya Komatineni #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 1273c4019f9SSowjanya Komatineni 1285ec6fa5aSAniruddha Tvs Rao #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 1295ec6fa5aSAniruddha Tvs Rao SDHCI_TRNS_BLK_CNT_EN | \ 1305ec6fa5aSAniruddha Tvs Rao SDHCI_TRNS_DMA) 1315ec6fa5aSAniruddha Tvs Rao 1323e44a1a7SStephen Warren struct sdhci_tegra_soc_data { 1331db5eebfSLars-Peter Clausen const struct sdhci_pltfm_data *pdata; 134b960bc44SNicolin Chen u64 dma_mask; 1353e44a1a7SStephen Warren u32 nvquirks; 136ea8fc595SSowjanya Komatineni u8 min_tap_delay; 137ea8fc595SSowjanya Komatineni u8 max_tap_delay; 1383e44a1a7SStephen Warren }; 1393e44a1a7SStephen Warren 14051b77c8eSAapo Vienamo /* Magic pull up and pull down pad calibration offsets */ 14151b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets { 14251b77c8eSAapo Vienamo u32 pull_up_3v3; 14351b77c8eSAapo Vienamo u32 pull_down_3v3; 14451b77c8eSAapo Vienamo u32 pull_up_3v3_timeout; 14551b77c8eSAapo Vienamo u32 pull_down_3v3_timeout; 14651b77c8eSAapo Vienamo u32 pull_up_1v8; 14751b77c8eSAapo Vienamo u32 pull_down_1v8; 14851b77c8eSAapo Vienamo u32 pull_up_1v8_timeout; 14951b77c8eSAapo Vienamo u32 pull_down_1v8_timeout; 15051b77c8eSAapo Vienamo u32 pull_up_sdr104; 15151b77c8eSAapo Vienamo u32 pull_down_sdr104; 15251b77c8eSAapo Vienamo u32 pull_up_hs400; 15351b77c8eSAapo Vienamo u32 pull_down_hs400; 15451b77c8eSAapo Vienamo }; 15551b77c8eSAapo Vienamo 1563e44a1a7SStephen Warren struct sdhci_tegra { 1573e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 1582391b340SMylene JOSSERAND struct gpio_desc *power_gpio; 1598048822bSSowjanya Komatineni struct clk *tmclk; 160a8e326a9SLucas Stach bool ddr_signaling; 161e5c63d91SLucas Stach bool pad_calib_required; 16286ac2f8bSAapo Vienamo bool pad_control_available; 16320567be9SThierry Reding 16420567be9SThierry Reding struct reset_control *rst; 16586ac2f8bSAapo Vienamo struct pinctrl *pinctrl_sdmmc; 16686ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_3v3; 16786ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_1v8; 168de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_state_3v3_drv; 169de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_state_1v8_drv; 17051b77c8eSAapo Vienamo 17151b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets autocal_offsets; 17261dad40eSAapo Vienamo ktime_t last_calib; 17385c0da17SAapo Vienamo 17485c0da17SAapo Vienamo u32 default_tap; 17585c0da17SAapo Vienamo u32 default_trim; 176f5313aaaSAapo Vienamo u32 dqs_trim; 1773c4019f9SSowjanya Komatineni bool enable_hwcq; 178ea8fc595SSowjanya Komatineni unsigned long curr_clk_rate; 179ea8fc595SSowjanya Komatineni u8 tuned_tap_delay; 1803e44a1a7SStephen Warren }; 1813e44a1a7SStephen Warren 18203d2bfc8SOlof Johansson static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 18303d2bfc8SOlof Johansson { 1843e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1850734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1863e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1873e44a1a7SStephen Warren 1883e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 1893e44a1a7SStephen Warren (reg == SDHCI_HOST_VERSION))) { 19003d2bfc8SOlof Johansson /* Erratum: Version register is invalid in HW. */ 19103d2bfc8SOlof Johansson return SDHCI_SPEC_200; 19203d2bfc8SOlof Johansson } 19303d2bfc8SOlof Johansson 19403d2bfc8SOlof Johansson return readw(host->ioaddr + reg); 19503d2bfc8SOlof Johansson } 19603d2bfc8SOlof Johansson 197352ee868SPavan Kunapuli static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 198352ee868SPavan Kunapuli { 199352ee868SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200352ee868SPavan Kunapuli 201352ee868SPavan Kunapuli switch (reg) { 202352ee868SPavan Kunapuli case SDHCI_TRANSFER_MODE: 203352ee868SPavan Kunapuli /* 204352ee868SPavan Kunapuli * Postpone this write, we must do it together with a 205352ee868SPavan Kunapuli * command write that is down below. 206352ee868SPavan Kunapuli */ 207352ee868SPavan Kunapuli pltfm_host->xfer_mode_shadow = val; 208352ee868SPavan Kunapuli return; 209352ee868SPavan Kunapuli case SDHCI_COMMAND: 210352ee868SPavan Kunapuli writel((val << 16) | pltfm_host->xfer_mode_shadow, 211352ee868SPavan Kunapuli host->ioaddr + SDHCI_TRANSFER_MODE); 212352ee868SPavan Kunapuli return; 213352ee868SPavan Kunapuli } 214352ee868SPavan Kunapuli 215352ee868SPavan Kunapuli writew(val, host->ioaddr + reg); 216352ee868SPavan Kunapuli } 217352ee868SPavan Kunapuli 21803d2bfc8SOlof Johansson static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 21903d2bfc8SOlof Johansson { 2203e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2210734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 2223e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 2233e44a1a7SStephen Warren 22403d2bfc8SOlof Johansson /* Seems like we're getting spurious timeout and crc errors, so 22503d2bfc8SOlof Johansson * disable signalling of them. In case of real errors software 22603d2bfc8SOlof Johansson * timers should take care of eventually detecting them. 22703d2bfc8SOlof Johansson */ 22803d2bfc8SOlof Johansson if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 22903d2bfc8SOlof Johansson val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 23003d2bfc8SOlof Johansson 23103d2bfc8SOlof Johansson writel(val, host->ioaddr + reg); 23203d2bfc8SOlof Johansson 2333e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 2343e44a1a7SStephen Warren (reg == SDHCI_INT_ENABLE))) { 23503d2bfc8SOlof Johansson /* Erratum: Must enable block gap interrupt detection */ 23603d2bfc8SOlof Johansson u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 23703d2bfc8SOlof Johansson if (val & SDHCI_INT_CARD_INT) 23803d2bfc8SOlof Johansson gap_ctrl |= 0x8; 23903d2bfc8SOlof Johansson else 24003d2bfc8SOlof Johansson gap_ctrl &= ~0x8; 24103d2bfc8SOlof Johansson writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 24203d2bfc8SOlof Johansson } 24303d2bfc8SOlof Johansson } 24403d2bfc8SOlof Johansson 24538a284d9SAapo Vienamo static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 24638a284d9SAapo Vienamo { 24738a284d9SAapo Vienamo bool status; 24838a284d9SAapo Vienamo u32 reg; 24938a284d9SAapo Vienamo 25038a284d9SAapo Vienamo reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 25138a284d9SAapo Vienamo status = !!(reg & SDHCI_CLOCK_CARD_EN); 25238a284d9SAapo Vienamo 25338a284d9SAapo Vienamo if (status == enable) 25438a284d9SAapo Vienamo return status; 25538a284d9SAapo Vienamo 25638a284d9SAapo Vienamo if (enable) 25738a284d9SAapo Vienamo reg |= SDHCI_CLOCK_CARD_EN; 25838a284d9SAapo Vienamo else 25938a284d9SAapo Vienamo reg &= ~SDHCI_CLOCK_CARD_EN; 26038a284d9SAapo Vienamo 26138a284d9SAapo Vienamo sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 26238a284d9SAapo Vienamo 26338a284d9SAapo Vienamo return status; 26438a284d9SAapo Vienamo } 26538a284d9SAapo Vienamo 26638a284d9SAapo Vienamo static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 26738a284d9SAapo Vienamo { 26838a284d9SAapo Vienamo bool is_tuning_cmd = 0; 26938a284d9SAapo Vienamo bool clk_enabled; 27038a284d9SAapo Vienamo u8 cmd; 27138a284d9SAapo Vienamo 27238a284d9SAapo Vienamo if (reg == SDHCI_COMMAND) { 27338a284d9SAapo Vienamo cmd = SDHCI_GET_CMD(val); 27438a284d9SAapo Vienamo is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 27538a284d9SAapo Vienamo cmd == MMC_SEND_TUNING_BLOCK_HS200; 27638a284d9SAapo Vienamo } 27738a284d9SAapo Vienamo 27838a284d9SAapo Vienamo if (is_tuning_cmd) 27938a284d9SAapo Vienamo clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 28038a284d9SAapo Vienamo 28138a284d9SAapo Vienamo writew(val, host->ioaddr + reg); 28238a284d9SAapo Vienamo 28338a284d9SAapo Vienamo if (is_tuning_cmd) { 28438a284d9SAapo Vienamo udelay(1); 285ea8fc595SSowjanya Komatineni sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 28638a284d9SAapo Vienamo tegra_sdhci_configure_card_clk(host, clk_enabled); 28738a284d9SAapo Vienamo } 28838a284d9SAapo Vienamo } 28938a284d9SAapo Vienamo 2900f686ca9SDmitry Osipenko static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 2910f686ca9SDmitry Osipenko { 2920f686ca9SDmitry Osipenko /* 2930f686ca9SDmitry Osipenko * Write-enable shall be assumed if GPIO is missing in a board's 2940f686ca9SDmitry Osipenko * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 2950f686ca9SDmitry Osipenko * Tegra. 2960f686ca9SDmitry Osipenko */ 2970f686ca9SDmitry Osipenko return mmc_gpio_get_ro(host->mmc); 2980f686ca9SDmitry Osipenko } 2990f686ca9SDmitry Osipenko 30086ac2f8bSAapo Vienamo static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 30186ac2f8bSAapo Vienamo { 30286ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 30386ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 30486ac2f8bSAapo Vienamo int has_1v8, has_3v3; 30586ac2f8bSAapo Vienamo 30686ac2f8bSAapo Vienamo /* 30786ac2f8bSAapo Vienamo * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 30886ac2f8bSAapo Vienamo * voltage configuration in order to perform voltage switching. This 30986ac2f8bSAapo Vienamo * means that valid pinctrl info is required on SDHCI instances capable 31086ac2f8bSAapo Vienamo * of performing voltage switching. Whether or not an SDHCI instance is 31186ac2f8bSAapo Vienamo * capable of voltage switching is determined based on the regulator. 31286ac2f8bSAapo Vienamo */ 31386ac2f8bSAapo Vienamo 31486ac2f8bSAapo Vienamo if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 31586ac2f8bSAapo Vienamo return true; 31686ac2f8bSAapo Vienamo 31786ac2f8bSAapo Vienamo if (IS_ERR(host->mmc->supply.vqmmc)) 31886ac2f8bSAapo Vienamo return false; 31986ac2f8bSAapo Vienamo 32086ac2f8bSAapo Vienamo has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 32186ac2f8bSAapo Vienamo 1700000, 1950000); 32286ac2f8bSAapo Vienamo 32386ac2f8bSAapo Vienamo has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 32486ac2f8bSAapo Vienamo 2700000, 3600000); 32586ac2f8bSAapo Vienamo 32686ac2f8bSAapo Vienamo if (has_1v8 == 1 && has_3v3 == 1) 32786ac2f8bSAapo Vienamo return tegra_host->pad_control_available; 32886ac2f8bSAapo Vienamo 32986ac2f8bSAapo Vienamo /* Fixed voltage, no pad control required. */ 33086ac2f8bSAapo Vienamo return true; 33186ac2f8bSAapo Vienamo } 33286ac2f8bSAapo Vienamo 333c2c09678SAapo Vienamo static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 334c2c09678SAapo Vienamo { 335c2c09678SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 336c2c09678SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 337c2c09678SAapo Vienamo const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 338c2c09678SAapo Vienamo bool card_clk_enabled = false; 339c2c09678SAapo Vienamo u32 reg; 340c2c09678SAapo Vienamo 341c2c09678SAapo Vienamo /* 342c2c09678SAapo Vienamo * Touching the tap values is a bit tricky on some SoC generations. 343c2c09678SAapo Vienamo * The quirk enables a workaround for a glitch that sometimes occurs if 344c2c09678SAapo Vienamo * the tap values are changed. 345c2c09678SAapo Vienamo */ 346c2c09678SAapo Vienamo 347c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 348c2c09678SAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 349c2c09678SAapo Vienamo 350c2c09678SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 351c2c09678SAapo Vienamo reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 352c2c09678SAapo Vienamo reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 353c2c09678SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 354c2c09678SAapo Vienamo 355c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 356c2c09678SAapo Vienamo card_clk_enabled) { 357c2c09678SAapo Vienamo udelay(1); 358c2c09678SAapo Vienamo sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 359c2c09678SAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 360c2c09678SAapo Vienamo } 361c2c09678SAapo Vienamo } 362c2c09678SAapo Vienamo 363dfc9700cSAapo Vienamo static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 364dfc9700cSAapo Vienamo struct mmc_ios *ios) 365dfc9700cSAapo Vienamo { 366dfc9700cSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 367dfc9700cSAapo Vienamo u32 val; 368dfc9700cSAapo Vienamo 369dfc9700cSAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 370dfc9700cSAapo Vienamo 371dfc9700cSAapo Vienamo if (ios->enhanced_strobe) 372dfc9700cSAapo Vienamo val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 373dfc9700cSAapo Vienamo else 374dfc9700cSAapo Vienamo val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 375dfc9700cSAapo Vienamo 376dfc9700cSAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 377dfc9700cSAapo Vienamo 378dfc9700cSAapo Vienamo } 379dfc9700cSAapo Vienamo 38003231f9bSRussell King static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 381ca5879d3SPavan Kunapuli { 382ca5879d3SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3830734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 384ca5879d3SPavan Kunapuli const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 3859d548f11SAapo Vienamo u32 misc_ctrl, clk_ctrl, pad_ctrl; 386ca5879d3SPavan Kunapuli 38703231f9bSRussell King sdhci_reset(host, mask); 38803231f9bSRussell King 389ca5879d3SPavan Kunapuli if (!(mask & SDHCI_RESET_ALL)) 390ca5879d3SPavan Kunapuli return; 391ca5879d3SPavan Kunapuli 392c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 393c2c09678SAapo Vienamo 3941b84def8SLucas Stach misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 3954f6aa326SJon Hunter clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 3964f6aa326SJon Hunter 3974f6aa326SJon Hunter misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 3984f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR50 | 3994f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_DDR50 | 4004f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR104); 4014f6aa326SJon Hunter 40241a0b8d7SAapo Vienamo clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 40341a0b8d7SAapo Vienamo SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 4044f6aa326SJon Hunter 40586ac2f8bSAapo Vienamo if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 406ca5879d3SPavan Kunapuli /* Erratum: Enable SDHCI spec v3.00 support */ 4073145351aSAndrew Bresticker if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 408ca5879d3SPavan Kunapuli misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 4097ad2ed1dSLucas Stach /* Advertise UHS modes as supported by host */ 4107ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 4117ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 4127ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 4137ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 4147ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 4157ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 416f571389cSMichał Mirosław if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 417c3c2384cSLucas Stach clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 4184f6aa326SJon Hunter } 4194f6aa326SJon Hunter 42041a0b8d7SAapo Vienamo clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 42141a0b8d7SAapo Vienamo 4224f6aa326SJon Hunter sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 42374cd42bcSLucas Stach sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 42474cd42bcSLucas Stach 4259d548f11SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 4269d548f11SAapo Vienamo pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 4279d548f11SAapo Vienamo pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 4289d548f11SAapo Vienamo pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 4299d548f11SAapo Vienamo sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 4309d548f11SAapo Vienamo 431e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 4329d548f11SAapo Vienamo } 433e5c63d91SLucas Stach 434a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 435ca5879d3SPavan Kunapuli } 436ca5879d3SPavan Kunapuli 437212b0cf1SAapo Vienamo static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 438212b0cf1SAapo Vienamo { 439212b0cf1SAapo Vienamo u32 val; 440212b0cf1SAapo Vienamo 441212b0cf1SAapo Vienamo /* 442212b0cf1SAapo Vienamo * Enable or disable the additional I/O pad used by the drive strength 443212b0cf1SAapo Vienamo * calibration process. 444212b0cf1SAapo Vienamo */ 445212b0cf1SAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 446212b0cf1SAapo Vienamo 447212b0cf1SAapo Vienamo if (enable) 448212b0cf1SAapo Vienamo val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 449212b0cf1SAapo Vienamo else 450212b0cf1SAapo Vienamo val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 451212b0cf1SAapo Vienamo 452212b0cf1SAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 453212b0cf1SAapo Vienamo 454212b0cf1SAapo Vienamo if (enable) 455212b0cf1SAapo Vienamo usleep_range(1, 2); 456212b0cf1SAapo Vienamo } 457212b0cf1SAapo Vienamo 45851b77c8eSAapo Vienamo static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 45951b77c8eSAapo Vienamo u16 pdpu) 46051b77c8eSAapo Vienamo { 46151b77c8eSAapo Vienamo u32 reg; 46251b77c8eSAapo Vienamo 46351b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 46451b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 46551b77c8eSAapo Vienamo reg |= pdpu; 46651b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 46751b77c8eSAapo Vienamo } 46851b77c8eSAapo Vienamo 469de25fa5aSSowjanya Komatineni static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 470de25fa5aSSowjanya Komatineni bool state_drvupdn) 471de25fa5aSSowjanya Komatineni { 472de25fa5aSSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 473de25fa5aSSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 474de25fa5aSSowjanya Komatineni struct sdhci_tegra_autocal_offsets *offsets = 475de25fa5aSSowjanya Komatineni &tegra_host->autocal_offsets; 476de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_drvupdn = NULL; 477de25fa5aSSowjanya Komatineni int ret = 0; 478de25fa5aSSowjanya Komatineni u8 drvup = 0, drvdn = 0; 479de25fa5aSSowjanya Komatineni u32 reg; 480de25fa5aSSowjanya Komatineni 481de25fa5aSSowjanya Komatineni if (!state_drvupdn) { 482de25fa5aSSowjanya Komatineni /* PADS Drive Strength */ 483de25fa5aSSowjanya Komatineni if (voltage == MMC_SIGNAL_VOLTAGE_180) { 484de25fa5aSSowjanya Komatineni if (tegra_host->pinctrl_state_1v8_drv) { 485de25fa5aSSowjanya Komatineni pinctrl_drvupdn = 486de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv; 487de25fa5aSSowjanya Komatineni } else { 488de25fa5aSSowjanya Komatineni drvup = offsets->pull_up_1v8_timeout; 489de25fa5aSSowjanya Komatineni drvdn = offsets->pull_down_1v8_timeout; 490de25fa5aSSowjanya Komatineni } 491de25fa5aSSowjanya Komatineni } else { 492de25fa5aSSowjanya Komatineni if (tegra_host->pinctrl_state_3v3_drv) { 493de25fa5aSSowjanya Komatineni pinctrl_drvupdn = 494de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv; 495de25fa5aSSowjanya Komatineni } else { 496de25fa5aSSowjanya Komatineni drvup = offsets->pull_up_3v3_timeout; 497de25fa5aSSowjanya Komatineni drvdn = offsets->pull_down_3v3_timeout; 498de25fa5aSSowjanya Komatineni } 499de25fa5aSSowjanya Komatineni } 500de25fa5aSSowjanya Komatineni 501de25fa5aSSowjanya Komatineni if (pinctrl_drvupdn != NULL) { 502de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 503de25fa5aSSowjanya Komatineni pinctrl_drvupdn); 504de25fa5aSSowjanya Komatineni if (ret < 0) 505de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 506de25fa5aSSowjanya Komatineni "failed pads drvupdn, ret: %d\n", ret); 507de25fa5aSSowjanya Komatineni } else if ((drvup) || (drvdn)) { 508de25fa5aSSowjanya Komatineni reg = sdhci_readl(host, 509de25fa5aSSowjanya Komatineni SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 510de25fa5aSSowjanya Komatineni reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 511de25fa5aSSowjanya Komatineni reg |= (drvup << 20) | (drvdn << 12); 512de25fa5aSSowjanya Komatineni sdhci_writel(host, reg, 513de25fa5aSSowjanya Komatineni SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 514de25fa5aSSowjanya Komatineni } 515de25fa5aSSowjanya Komatineni 516de25fa5aSSowjanya Komatineni } else { 517de25fa5aSSowjanya Komatineni /* Dual Voltage PADS Voltage selection */ 518de25fa5aSSowjanya Komatineni if (!tegra_host->pad_control_available) 519de25fa5aSSowjanya Komatineni return 0; 520de25fa5aSSowjanya Komatineni 521de25fa5aSSowjanya Komatineni if (voltage == MMC_SIGNAL_VOLTAGE_180) { 522de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 523de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8); 524de25fa5aSSowjanya Komatineni if (ret < 0) 525de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 526de25fa5aSSowjanya Komatineni "setting 1.8V failed, ret: %d\n", ret); 527de25fa5aSSowjanya Komatineni } else { 528de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 529de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3); 530de25fa5aSSowjanya Komatineni if (ret < 0) 531de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 532de25fa5aSSowjanya Komatineni "setting 3.3V failed, ret: %d\n", ret); 533de25fa5aSSowjanya Komatineni } 534de25fa5aSSowjanya Komatineni } 535de25fa5aSSowjanya Komatineni 536de25fa5aSSowjanya Komatineni return ret; 537de25fa5aSSowjanya Komatineni } 538de25fa5aSSowjanya Komatineni 539e5c63d91SLucas Stach static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 540e5c63d91SLucas Stach { 54151b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 54251b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 54351b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets offsets = 54451b77c8eSAapo Vienamo tegra_host->autocal_offsets; 54551b77c8eSAapo Vienamo struct mmc_ios *ios = &host->mmc->ios; 546887bda8fSAapo Vienamo bool card_clk_enabled; 54751b77c8eSAapo Vienamo u16 pdpu; 548e7c07148SAapo Vienamo u32 reg; 549e7c07148SAapo Vienamo int ret; 550e5c63d91SLucas Stach 55151b77c8eSAapo Vienamo switch (ios->timing) { 55251b77c8eSAapo Vienamo case MMC_TIMING_UHS_SDR104: 55351b77c8eSAapo Vienamo pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 55451b77c8eSAapo Vienamo break; 55551b77c8eSAapo Vienamo case MMC_TIMING_MMC_HS400: 55651b77c8eSAapo Vienamo pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 55751b77c8eSAapo Vienamo break; 55851b77c8eSAapo Vienamo default: 55951b77c8eSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 56051b77c8eSAapo Vienamo pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 56151b77c8eSAapo Vienamo else 56251b77c8eSAapo Vienamo pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 56351b77c8eSAapo Vienamo } 56451b77c8eSAapo Vienamo 565de25fa5aSSowjanya Komatineni /* Set initial offset before auto-calibration */ 56651b77c8eSAapo Vienamo tegra_sdhci_set_pad_autocal_offset(host, pdpu); 56751b77c8eSAapo Vienamo 568887bda8fSAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 569887bda8fSAapo Vienamo 570212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, true); 571212b0cf1SAapo Vienamo 572e7c07148SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 573e7c07148SAapo Vienamo reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 574e7c07148SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 575e5c63d91SLucas Stach 576e7c07148SAapo Vienamo usleep_range(1, 2); 577e7c07148SAapo Vienamo /* 10 ms timeout */ 578e7c07148SAapo Vienamo ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 579e7c07148SAapo Vienamo reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 580e7c07148SAapo Vienamo 1000, 10000); 581e7c07148SAapo Vienamo 582212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, false); 583212b0cf1SAapo Vienamo 584887bda8fSAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 585887bda8fSAapo Vienamo 58651b77c8eSAapo Vienamo if (ret) { 587e7c07148SAapo Vienamo dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 58851b77c8eSAapo Vienamo 589de25fa5aSSowjanya Komatineni /* Disable automatic cal and use fixed Drive Strengths */ 59051b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 59151b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_ENABLE; 59251b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 59351b77c8eSAapo Vienamo 594de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 595de25fa5aSSowjanya Komatineni if (ret < 0) 596de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 597de25fa5aSSowjanya Komatineni "Setting drive strengths failed: %d\n", ret); 59851b77c8eSAapo Vienamo } 59951b77c8eSAapo Vienamo } 60051b77c8eSAapo Vienamo 60151b77c8eSAapo Vienamo static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 60251b77c8eSAapo Vienamo { 60351b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 60451b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 60551b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets *autocal = 60651b77c8eSAapo Vienamo &tegra_host->autocal_offsets; 60751b77c8eSAapo Vienamo int err; 60851b77c8eSAapo Vienamo 609bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 61051b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3", 61151b77c8eSAapo Vienamo &autocal->pull_up_3v3); 61251b77c8eSAapo Vienamo if (err) 61351b77c8eSAapo Vienamo autocal->pull_up_3v3 = 0; 61451b77c8eSAapo Vienamo 615bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 61651b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3", 61751b77c8eSAapo Vienamo &autocal->pull_down_3v3); 61851b77c8eSAapo Vienamo if (err) 61951b77c8eSAapo Vienamo autocal->pull_down_3v3 = 0; 62051b77c8eSAapo Vienamo 621bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 62251b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8", 62351b77c8eSAapo Vienamo &autocal->pull_up_1v8); 62451b77c8eSAapo Vienamo if (err) 62551b77c8eSAapo Vienamo autocal->pull_up_1v8 = 0; 62651b77c8eSAapo Vienamo 627bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 62851b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8", 62951b77c8eSAapo Vienamo &autocal->pull_down_1v8); 63051b77c8eSAapo Vienamo if (err) 63151b77c8eSAapo Vienamo autocal->pull_down_1v8 = 0; 63251b77c8eSAapo Vienamo 633bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 634aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-up-offset-sdr104", 635aebbf577SSowjanya Komatineni &autocal->pull_up_sdr104); 636aebbf577SSowjanya Komatineni if (err) 637aebbf577SSowjanya Komatineni autocal->pull_up_sdr104 = autocal->pull_up_1v8; 638aebbf577SSowjanya Komatineni 639bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 640aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-down-offset-sdr104", 641aebbf577SSowjanya Komatineni &autocal->pull_down_sdr104); 642aebbf577SSowjanya Komatineni if (err) 643aebbf577SSowjanya Komatineni autocal->pull_down_sdr104 = autocal->pull_down_1v8; 644aebbf577SSowjanya Komatineni 645bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 646aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-up-offset-hs400", 647aebbf577SSowjanya Komatineni &autocal->pull_up_hs400); 648aebbf577SSowjanya Komatineni if (err) 649aebbf577SSowjanya Komatineni autocal->pull_up_hs400 = autocal->pull_up_1v8; 650aebbf577SSowjanya Komatineni 651bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 652aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-down-offset-hs400", 653aebbf577SSowjanya Komatineni &autocal->pull_down_hs400); 654aebbf577SSowjanya Komatineni if (err) 655aebbf577SSowjanya Komatineni autocal->pull_down_hs400 = autocal->pull_down_1v8; 656aebbf577SSowjanya Komatineni 657aebbf577SSowjanya Komatineni /* 658aebbf577SSowjanya Komatineni * Different fail-safe drive strength values based on the signaling 659aebbf577SSowjanya Komatineni * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. 660aebbf577SSowjanya Komatineni * So, avoid reading below device tree properties for SoCs that don't 661aebbf577SSowjanya Komatineni * have NVQUIRK_NEEDS_PAD_CONTROL. 662aebbf577SSowjanya Komatineni */ 663aebbf577SSowjanya Komatineni if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 664aebbf577SSowjanya Komatineni return; 665aebbf577SSowjanya Komatineni 666bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 66751b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 6685ccf7f55SSowjanya Komatineni &autocal->pull_up_3v3_timeout); 669de25fa5aSSowjanya Komatineni if (err) { 670de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 671de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_3v3_drv == NULL)) 672de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 673de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 67451b77c8eSAapo Vienamo autocal->pull_up_3v3_timeout = 0; 675de25fa5aSSowjanya Komatineni } 67651b77c8eSAapo Vienamo 677bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 67851b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 6795ccf7f55SSowjanya Komatineni &autocal->pull_down_3v3_timeout); 680de25fa5aSSowjanya Komatineni if (err) { 681de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 682de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_3v3_drv == NULL)) 683de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 684de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 68551b77c8eSAapo Vienamo autocal->pull_down_3v3_timeout = 0; 686de25fa5aSSowjanya Komatineni } 68751b77c8eSAapo Vienamo 688bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 68951b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 6905ccf7f55SSowjanya Komatineni &autocal->pull_up_1v8_timeout); 691de25fa5aSSowjanya Komatineni if (err) { 692de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 693de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_1v8_drv == NULL)) 694de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 695de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 69651b77c8eSAapo Vienamo autocal->pull_up_1v8_timeout = 0; 697de25fa5aSSowjanya Komatineni } 69851b77c8eSAapo Vienamo 699bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 70051b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 7015ccf7f55SSowjanya Komatineni &autocal->pull_down_1v8_timeout); 702de25fa5aSSowjanya Komatineni if (err) { 703de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 704de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_1v8_drv == NULL)) 705de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 706de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 70751b77c8eSAapo Vienamo autocal->pull_down_1v8_timeout = 0; 708de25fa5aSSowjanya Komatineni } 709e5c63d91SLucas Stach } 710e5c63d91SLucas Stach 71161dad40eSAapo Vienamo static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 71261dad40eSAapo Vienamo { 71361dad40eSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 71461dad40eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 71561dad40eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 71661dad40eSAapo Vienamo ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 71761dad40eSAapo Vienamo 71861dad40eSAapo Vienamo /* 100 ms calibration interval is specified in the TRM */ 71961dad40eSAapo Vienamo if (ktime_to_ms(since_calib) > 100) { 72061dad40eSAapo Vienamo tegra_sdhci_pad_autocalib(host); 72161dad40eSAapo Vienamo tegra_host->last_calib = ktime_get(); 72261dad40eSAapo Vienamo } 72361dad40eSAapo Vienamo 72461dad40eSAapo Vienamo sdhci_request(mmc, mrq); 72561dad40eSAapo Vienamo } 72661dad40eSAapo Vienamo 727f5313aaaSAapo Vienamo static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 72885c0da17SAapo Vienamo { 72985c0da17SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73085c0da17SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 73185c0da17SAapo Vienamo int err; 73285c0da17SAapo Vienamo 733bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", 73485c0da17SAapo Vienamo &tegra_host->default_tap); 73585c0da17SAapo Vienamo if (err) 73685c0da17SAapo Vienamo tegra_host->default_tap = 0; 73785c0da17SAapo Vienamo 738bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", 73985c0da17SAapo Vienamo &tegra_host->default_trim); 74085c0da17SAapo Vienamo if (err) 74185c0da17SAapo Vienamo tegra_host->default_trim = 0; 742f5313aaaSAapo Vienamo 743bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", 744f5313aaaSAapo Vienamo &tegra_host->dqs_trim); 745f5313aaaSAapo Vienamo if (err) 746f5313aaaSAapo Vienamo tegra_host->dqs_trim = 0x11; 74785c0da17SAapo Vienamo } 74885c0da17SAapo Vienamo 7493c4019f9SSowjanya Komatineni static void tegra_sdhci_parse_dt(struct sdhci_host *host) 7503c4019f9SSowjanya Komatineni { 7513c4019f9SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7523c4019f9SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 7533c4019f9SSowjanya Komatineni 754bac53336SJisheng Zhang if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) 7553c4019f9SSowjanya Komatineni tegra_host->enable_hwcq = true; 7563c4019f9SSowjanya Komatineni else 7573c4019f9SSowjanya Komatineni tegra_host->enable_hwcq = false; 7583c4019f9SSowjanya Komatineni 7593c4019f9SSowjanya Komatineni tegra_sdhci_parse_pad_autocal_dt(host); 7603c4019f9SSowjanya Komatineni tegra_sdhci_parse_tap_and_trim(host); 7613c4019f9SSowjanya Komatineni } 7623c4019f9SSowjanya Komatineni 763a8e326a9SLucas Stach static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 764a8e326a9SLucas Stach { 765a8e326a9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7660734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 767*d618978dSDmitry Osipenko struct device *dev = mmc_dev(host->mmc); 768a8e326a9SLucas Stach unsigned long host_clk; 769*d618978dSDmitry Osipenko int err; 770a8e326a9SLucas Stach 771a8e326a9SLucas Stach if (!clock) 7723491b690SLucas Stach return sdhci_set_clock(host, clock); 773a8e326a9SLucas Stach 77457d1654eSAapo Vienamo /* 77557d1654eSAapo Vienamo * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 77657d1654eSAapo Vienamo * divider to be configured to divided the host clock by two. The SDHCI 77757d1654eSAapo Vienamo * clock divider is calculated as part of sdhci_set_clock() by 77857d1654eSAapo Vienamo * sdhci_calc_clk(). The divider is calculated from host->max_clk and 77957d1654eSAapo Vienamo * the requested clock rate. 78057d1654eSAapo Vienamo * 78157d1654eSAapo Vienamo * By setting the host->max_clk to clock * 2 the divider calculation 78257d1654eSAapo Vienamo * will always result in the correct value for DDR50/52 modes, 78357d1654eSAapo Vienamo * regardless of clock rate rounding, which may happen if the value 78457d1654eSAapo Vienamo * from clk_get_rate() is used. 78557d1654eSAapo Vienamo */ 786a8e326a9SLucas Stach host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 787*d618978dSDmitry Osipenko 788*d618978dSDmitry Osipenko err = dev_pm_opp_set_rate(dev, host_clk); 789*d618978dSDmitry Osipenko if (err) 790*d618978dSDmitry Osipenko dev_err(dev, "failed to set clk rate to %luHz: %d\n", 791*d618978dSDmitry Osipenko host_clk, err); 792*d618978dSDmitry Osipenko 793ea8fc595SSowjanya Komatineni tegra_host->curr_clk_rate = host_clk; 79457d1654eSAapo Vienamo if (tegra_host->ddr_signaling) 79557d1654eSAapo Vienamo host->max_clk = host_clk; 79657d1654eSAapo Vienamo else 797a8e326a9SLucas Stach host->max_clk = clk_get_rate(pltfm_host->clk); 798a8e326a9SLucas Stach 799e5c63d91SLucas Stach sdhci_set_clock(host, clock); 800e5c63d91SLucas Stach 801e5c63d91SLucas Stach if (tegra_host->pad_calib_required) { 802e5c63d91SLucas Stach tegra_sdhci_pad_autocalib(host); 803e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 804e5c63d91SLucas Stach } 805a8e326a9SLucas Stach } 806a8e326a9SLucas Stach 80744350993SAapo Vienamo static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 80844350993SAapo Vienamo { 80944350993SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 81044350993SAapo Vienamo 81144350993SAapo Vienamo return clk_round_rate(pltfm_host->clk, UINT_MAX); 81244350993SAapo Vienamo } 81344350993SAapo Vienamo 814f5313aaaSAapo Vienamo static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 815f5313aaaSAapo Vienamo { 816f5313aaaSAapo Vienamo u32 val; 817f5313aaaSAapo Vienamo 818f5313aaaSAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 819f5313aaaSAapo Vienamo val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 820f5313aaaSAapo Vienamo val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 821f5313aaaSAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 822f5313aaaSAapo Vienamo } 823f5313aaaSAapo Vienamo 824bc5568bfSAapo Vienamo static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 825bc5568bfSAapo Vienamo { 826bc5568bfSAapo Vienamo u32 reg; 827bc5568bfSAapo Vienamo int err; 828bc5568bfSAapo Vienamo 829bc5568bfSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 830bc5568bfSAapo Vienamo reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 831bc5568bfSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 832bc5568bfSAapo Vienamo 833bc5568bfSAapo Vienamo /* 1 ms sleep, 5 ms timeout */ 834bc5568bfSAapo Vienamo err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 835bc5568bfSAapo Vienamo reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 836bc5568bfSAapo Vienamo 1000, 5000); 837bc5568bfSAapo Vienamo if (err) 838bc5568bfSAapo Vienamo dev_err(mmc_dev(host->mmc), 839bc5568bfSAapo Vienamo "HS400 delay line calibration timed out\n"); 840bc5568bfSAapo Vienamo } 841bc5568bfSAapo Vienamo 842ea8fc595SSowjanya Komatineni static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 843ea8fc595SSowjanya Komatineni u8 thd_low, u8 fixed_tap) 844ea8fc595SSowjanya Komatineni { 845ea8fc595SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 846ea8fc595SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 847ea8fc595SSowjanya Komatineni u32 val, tun_status; 848ea8fc595SSowjanya Komatineni u8 word, bit, edge1, tap, window; 849ea8fc595SSowjanya Komatineni bool tap_result; 850ea8fc595SSowjanya Komatineni bool start_fail = false; 851ea8fc595SSowjanya Komatineni bool start_pass = false; 852ea8fc595SSowjanya Komatineni bool end_pass = false; 853ea8fc595SSowjanya Komatineni bool first_fail = false; 854ea8fc595SSowjanya Komatineni bool first_pass = false; 855ea8fc595SSowjanya Komatineni u8 start_pass_tap = 0; 856ea8fc595SSowjanya Komatineni u8 end_pass_tap = 0; 857ea8fc595SSowjanya Komatineni u8 first_fail_tap = 0; 858ea8fc595SSowjanya Komatineni u8 first_pass_tap = 0; 859ea8fc595SSowjanya Komatineni u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 860ea8fc595SSowjanya Komatineni 861ea8fc595SSowjanya Komatineni /* 862ea8fc595SSowjanya Komatineni * Read auto-tuned results and extract good valid passing window by 863ea8fc595SSowjanya Komatineni * filtering out un-wanted bubble/partial/merged windows. 864ea8fc595SSowjanya Komatineni */ 865ea8fc595SSowjanya Komatineni for (word = 0; word < total_tuning_words; word++) { 866ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 867ea8fc595SSowjanya Komatineni val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 868ea8fc595SSowjanya Komatineni val |= word; 869ea8fc595SSowjanya Komatineni sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 870ea8fc595SSowjanya Komatineni tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 871ea8fc595SSowjanya Komatineni bit = 0; 872ea8fc595SSowjanya Komatineni while (bit < TUNING_WORD_BIT_SIZE) { 873ea8fc595SSowjanya Komatineni tap = word * TUNING_WORD_BIT_SIZE + bit; 874ea8fc595SSowjanya Komatineni tap_result = tun_status & (1 << bit); 875ea8fc595SSowjanya Komatineni if (!tap_result && !start_fail) { 876ea8fc595SSowjanya Komatineni start_fail = true; 877ea8fc595SSowjanya Komatineni if (!first_fail) { 878ea8fc595SSowjanya Komatineni first_fail_tap = tap; 879ea8fc595SSowjanya Komatineni first_fail = true; 880ea8fc595SSowjanya Komatineni } 881ea8fc595SSowjanya Komatineni 882ea8fc595SSowjanya Komatineni } else if (tap_result && start_fail && !start_pass) { 883ea8fc595SSowjanya Komatineni start_pass_tap = tap; 884ea8fc595SSowjanya Komatineni start_pass = true; 885ea8fc595SSowjanya Komatineni if (!first_pass) { 886ea8fc595SSowjanya Komatineni first_pass_tap = tap; 887ea8fc595SSowjanya Komatineni first_pass = true; 888ea8fc595SSowjanya Komatineni } 889ea8fc595SSowjanya Komatineni 890ea8fc595SSowjanya Komatineni } else if (!tap_result && start_fail && start_pass && 891ea8fc595SSowjanya Komatineni !end_pass) { 892ea8fc595SSowjanya Komatineni end_pass_tap = tap - 1; 893ea8fc595SSowjanya Komatineni end_pass = true; 894ea8fc595SSowjanya Komatineni } else if (tap_result && start_pass && start_fail && 895ea8fc595SSowjanya Komatineni end_pass) { 896ea8fc595SSowjanya Komatineni window = end_pass_tap - start_pass_tap; 897ea8fc595SSowjanya Komatineni /* discard merged window and bubble window */ 898ea8fc595SSowjanya Komatineni if (window >= thd_up || window < thd_low) { 899ea8fc595SSowjanya Komatineni start_pass_tap = tap; 900ea8fc595SSowjanya Komatineni end_pass = false; 901ea8fc595SSowjanya Komatineni } else { 902ea8fc595SSowjanya Komatineni /* set tap at middle of valid window */ 903ea8fc595SSowjanya Komatineni tap = start_pass_tap + window / 2; 904ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = tap; 905ea8fc595SSowjanya Komatineni return; 906ea8fc595SSowjanya Komatineni } 907ea8fc595SSowjanya Komatineni } 908ea8fc595SSowjanya Komatineni 909ea8fc595SSowjanya Komatineni bit++; 910ea8fc595SSowjanya Komatineni } 911ea8fc595SSowjanya Komatineni } 912ea8fc595SSowjanya Komatineni 913ea8fc595SSowjanya Komatineni if (!first_fail) { 914d96dc68eSDan Carpenter WARN(1, "no edge detected, continue with hw tuned delay.\n"); 915ea8fc595SSowjanya Komatineni } else if (first_pass) { 916ea8fc595SSowjanya Komatineni /* set tap location at fixed tap relative to the first edge */ 917ea8fc595SSowjanya Komatineni edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 918ea8fc595SSowjanya Komatineni if (edge1 - 1 > fixed_tap) 919ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = edge1 - fixed_tap; 920ea8fc595SSowjanya Komatineni else 921ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = edge1 + fixed_tap; 922ea8fc595SSowjanya Komatineni } 923ea8fc595SSowjanya Komatineni } 924ea8fc595SSowjanya Komatineni 925ea8fc595SSowjanya Komatineni static void tegra_sdhci_post_tuning(struct sdhci_host *host) 926ea8fc595SSowjanya Komatineni { 927ea8fc595SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 928ea8fc595SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 929ea8fc595SSowjanya Komatineni const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 930ea8fc595SSowjanya Komatineni u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 931ea8fc595SSowjanya Komatineni u8 fixed_tap, start_tap, end_tap, window_width; 932ea8fc595SSowjanya Komatineni u8 thdupper, thdlower; 933ea8fc595SSowjanya Komatineni u8 num_iter; 934ea8fc595SSowjanya Komatineni u32 clk_rate_mhz, period_ps, bestcase, worstcase; 935ea8fc595SSowjanya Komatineni 936ea8fc595SSowjanya Komatineni /* retain HW tuned tap to use incase if no correction is needed */ 937ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 938ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 939ea8fc595SSowjanya Komatineni SDHCI_CLOCK_CTRL_TAP_SHIFT; 940ea8fc595SSowjanya Komatineni if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 941ea8fc595SSowjanya Komatineni min_tap_dly = soc_data->min_tap_delay; 942ea8fc595SSowjanya Komatineni max_tap_dly = soc_data->max_tap_delay; 943ea8fc595SSowjanya Komatineni clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 944ea8fc595SSowjanya Komatineni period_ps = USEC_PER_SEC / clk_rate_mhz; 945ea8fc595SSowjanya Komatineni bestcase = period_ps / min_tap_dly; 946ea8fc595SSowjanya Komatineni worstcase = period_ps / max_tap_dly; 947ea8fc595SSowjanya Komatineni /* 948ea8fc595SSowjanya Komatineni * Upper and Lower bound thresholds used to detect merged and 949ea8fc595SSowjanya Komatineni * bubble windows 950ea8fc595SSowjanya Komatineni */ 951ea8fc595SSowjanya Komatineni thdupper = (2 * worstcase + bestcase) / 2; 952ea8fc595SSowjanya Komatineni thdlower = worstcase / 4; 953ea8fc595SSowjanya Komatineni /* 954ea8fc595SSowjanya Komatineni * fixed tap is used when HW tuning result contains single edge 955ea8fc595SSowjanya Komatineni * and tap is set at fixed tap delay relative to the first edge 956ea8fc595SSowjanya Komatineni */ 957ea8fc595SSowjanya Komatineni avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 958ea8fc595SSowjanya Komatineni fixed_tap = avg_tap_dly / 2; 959ea8fc595SSowjanya Komatineni 960ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 961ea8fc595SSowjanya Komatineni start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 962ea8fc595SSowjanya Komatineni end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 963ea8fc595SSowjanya Komatineni SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 964ea8fc595SSowjanya Komatineni window_width = end_tap - start_tap; 965ea8fc595SSowjanya Komatineni num_iter = host->tuning_loop_count; 966ea8fc595SSowjanya Komatineni /* 967ea8fc595SSowjanya Komatineni * partial window includes edges of the tuning range. 968ea8fc595SSowjanya Komatineni * merged window includes more taps so window width is higher 969ea8fc595SSowjanya Komatineni * than upper threshold. 970ea8fc595SSowjanya Komatineni */ 971ea8fc595SSowjanya Komatineni if (start_tap == 0 || (end_tap == (num_iter - 1)) || 972ea8fc595SSowjanya Komatineni (end_tap == num_iter - 2) || window_width >= thdupper) { 973ea8fc595SSowjanya Komatineni pr_debug("%s: Apply tuning correction\n", 974ea8fc595SSowjanya Komatineni mmc_hostname(host->mmc)); 975ea8fc595SSowjanya Komatineni tegra_sdhci_tap_correction(host, thdupper, thdlower, 976ea8fc595SSowjanya Komatineni fixed_tap); 977ea8fc595SSowjanya Komatineni } 978ea8fc595SSowjanya Komatineni } 979ea8fc595SSowjanya Komatineni 980ea8fc595SSowjanya Komatineni tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 981ea8fc595SSowjanya Komatineni } 982ea8fc595SSowjanya Komatineni 983ea8fc595SSowjanya Komatineni static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 984ea8fc595SSowjanya Komatineni { 985ea8fc595SSowjanya Komatineni struct sdhci_host *host = mmc_priv(mmc); 986ea8fc595SSowjanya Komatineni int err; 987ea8fc595SSowjanya Komatineni 988ea8fc595SSowjanya Komatineni err = sdhci_execute_tuning(mmc, opcode); 989ea8fc595SSowjanya Komatineni if (!err && !host->tuning_err) 990ea8fc595SSowjanya Komatineni tegra_sdhci_post_tuning(host); 991ea8fc595SSowjanya Komatineni 992ea8fc595SSowjanya Komatineni return err; 993ea8fc595SSowjanya Komatineni } 994ea8fc595SSowjanya Komatineni 995c2c09678SAapo Vienamo static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 996c2c09678SAapo Vienamo unsigned timing) 997c3c2384cSLucas Stach { 998d4501d8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 999d4501d8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1000c2c09678SAapo Vienamo bool set_default_tap = false; 1001f5313aaaSAapo Vienamo bool set_dqs_trim = false; 1002bc5568bfSAapo Vienamo bool do_hs400_dll_cal = false; 1003ea8fc595SSowjanya Komatineni u8 iter = TRIES_256; 1004ea8fc595SSowjanya Komatineni u32 val; 1005c3c2384cSLucas Stach 100692cd1667SSowjanya Komatineni tegra_host->ddr_signaling = false; 1007c2c09678SAapo Vienamo switch (timing) { 1008c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR50: 1009ea8fc595SSowjanya Komatineni break; 1010c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR104: 1011c2c09678SAapo Vienamo case MMC_TIMING_MMC_HS200: 1012c2c09678SAapo Vienamo /* Don't set default tap on tunable modes. */ 1013ea8fc595SSowjanya Komatineni iter = TRIES_128; 1014c2c09678SAapo Vienamo break; 1015f5313aaaSAapo Vienamo case MMC_TIMING_MMC_HS400: 1016f5313aaaSAapo Vienamo set_dqs_trim = true; 1017bc5568bfSAapo Vienamo do_hs400_dll_cal = true; 1018ea8fc595SSowjanya Komatineni iter = TRIES_128; 1019f5313aaaSAapo Vienamo break; 1020c2c09678SAapo Vienamo case MMC_TIMING_MMC_DDR52: 1021c2c09678SAapo Vienamo case MMC_TIMING_UHS_DDR50: 1022c2c09678SAapo Vienamo tegra_host->ddr_signaling = true; 1023c2c09678SAapo Vienamo set_default_tap = true; 1024c2c09678SAapo Vienamo break; 1025c2c09678SAapo Vienamo default: 1026c2c09678SAapo Vienamo set_default_tap = true; 1027c2c09678SAapo Vienamo break; 1028d4501d8eSAapo Vienamo } 1029c2c09678SAapo Vienamo 1030ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 1031ea8fc595SSowjanya Komatineni val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 1032ea8fc595SSowjanya Komatineni SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 1033ea8fc595SSowjanya Komatineni SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 1034ea8fc595SSowjanya Komatineni val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 1035ea8fc595SSowjanya Komatineni 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 1036ea8fc595SSowjanya Komatineni 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 1037ea8fc595SSowjanya Komatineni sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 1038ea8fc595SSowjanya Komatineni sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 1039ea8fc595SSowjanya Komatineni 1040ea8fc595SSowjanya Komatineni host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 1041ea8fc595SSowjanya Komatineni 1042c2c09678SAapo Vienamo sdhci_set_uhs_signaling(host, timing); 1043c2c09678SAapo Vienamo 1044c2c09678SAapo Vienamo tegra_sdhci_pad_autocalib(host); 1045c2c09678SAapo Vienamo 1046ea8fc595SSowjanya Komatineni if (tegra_host->tuned_tap_delay && !set_default_tap) 1047ea8fc595SSowjanya Komatineni tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1048ea8fc595SSowjanya Komatineni else 1049c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 1050f5313aaaSAapo Vienamo 1051f5313aaaSAapo Vienamo if (set_dqs_trim) 1052f5313aaaSAapo Vienamo tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1053bc5568bfSAapo Vienamo 1054bc5568bfSAapo Vienamo if (do_hs400_dll_cal) 1055bc5568bfSAapo Vienamo tegra_sdhci_hs400_dll_cal(host); 1056c3c2384cSLucas Stach } 1057c3c2384cSLucas Stach 1058c3c2384cSLucas Stach static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1059c3c2384cSLucas Stach { 1060c3c2384cSLucas Stach unsigned int min, max; 1061c3c2384cSLucas Stach 1062c3c2384cSLucas Stach /* 1063c3c2384cSLucas Stach * Start search for minimum tap value at 10, as smaller values are 1064c3c2384cSLucas Stach * may wrongly be reported as working but fail at higher speeds, 1065c3c2384cSLucas Stach * according to the TRM. 1066c3c2384cSLucas Stach */ 1067c3c2384cSLucas Stach min = 10; 1068c3c2384cSLucas Stach while (min < 255) { 1069c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min); 1070c3c2384cSLucas Stach if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1071c3c2384cSLucas Stach break; 1072c3c2384cSLucas Stach min++; 1073c3c2384cSLucas Stach } 1074c3c2384cSLucas Stach 1075c3c2384cSLucas Stach /* Find the maximum tap value that still passes. */ 1076c3c2384cSLucas Stach max = min + 1; 1077c3c2384cSLucas Stach while (max < 255) { 1078c3c2384cSLucas Stach tegra_sdhci_set_tap(host, max); 1079c3c2384cSLucas Stach if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1080c3c2384cSLucas Stach max--; 1081c3c2384cSLucas Stach break; 1082c3c2384cSLucas Stach } 1083c3c2384cSLucas Stach max++; 1084c3c2384cSLucas Stach } 1085c3c2384cSLucas Stach 1086c3c2384cSLucas Stach /* The TRM states the ideal tap value is at 75% in the passing range. */ 1087c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1088c3c2384cSLucas Stach 1089c3c2384cSLucas Stach return mmc_send_tuning(host->mmc, opcode, NULL); 1090c3c2384cSLucas Stach } 1091c3c2384cSLucas Stach 109286ac2f8bSAapo Vienamo static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 109386ac2f8bSAapo Vienamo struct mmc_ios *ios) 109486ac2f8bSAapo Vienamo { 109586ac2f8bSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 109644babea2SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109744babea2SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 109886ac2f8bSAapo Vienamo int ret = 0; 109986ac2f8bSAapo Vienamo 110086ac2f8bSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1101de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 110286ac2f8bSAapo Vienamo if (ret < 0) 110386ac2f8bSAapo Vienamo return ret; 110486ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 110586ac2f8bSAapo Vienamo } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 110686ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 110786ac2f8bSAapo Vienamo if (ret < 0) 110886ac2f8bSAapo Vienamo return ret; 1109de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 111086ac2f8bSAapo Vienamo } 111186ac2f8bSAapo Vienamo 111244babea2SAapo Vienamo if (tegra_host->pad_calib_required) 111344babea2SAapo Vienamo tegra_sdhci_pad_autocalib(host); 111444babea2SAapo Vienamo 111586ac2f8bSAapo Vienamo return ret; 111686ac2f8bSAapo Vienamo } 111786ac2f8bSAapo Vienamo 111886ac2f8bSAapo Vienamo static int tegra_sdhci_init_pinctrl_info(struct device *dev, 111986ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host) 112086ac2f8bSAapo Vienamo { 112186ac2f8bSAapo Vienamo tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 112286ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 112386ac2f8bSAapo Vienamo dev_dbg(dev, "No pinctrl info, err: %ld\n", 112486ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_sdmmc)); 112586ac2f8bSAapo Vienamo return -1; 112686ac2f8bSAapo Vienamo } 112786ac2f8bSAapo Vienamo 1128de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1129de25fa5aSSowjanya Komatineni tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1130de25fa5aSSowjanya Komatineni if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1131de25fa5aSSowjanya Komatineni if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1132de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv = NULL; 1133de25fa5aSSowjanya Komatineni } 1134de25fa5aSSowjanya Komatineni 1135de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1136de25fa5aSSowjanya Komatineni tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1137de25fa5aSSowjanya Komatineni if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1138de25fa5aSSowjanya Komatineni if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1139de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv = NULL; 1140de25fa5aSSowjanya Komatineni } 1141de25fa5aSSowjanya Komatineni 114286ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3 = 114386ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 114486ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 114586ac2f8bSAapo Vienamo dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 114686ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 114786ac2f8bSAapo Vienamo return -1; 114886ac2f8bSAapo Vienamo } 114986ac2f8bSAapo Vienamo 115086ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8 = 115186ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 115286ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 115386ac2f8bSAapo Vienamo dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1154e5378247SYueHaibing PTR_ERR(tegra_host->pinctrl_state_1v8)); 115586ac2f8bSAapo Vienamo return -1; 115686ac2f8bSAapo Vienamo } 115786ac2f8bSAapo Vienamo 115886ac2f8bSAapo Vienamo tegra_host->pad_control_available = true; 115986ac2f8bSAapo Vienamo 116086ac2f8bSAapo Vienamo return 0; 116186ac2f8bSAapo Vienamo } 116286ac2f8bSAapo Vienamo 1163e5c63d91SLucas Stach static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1164e5c63d91SLucas Stach { 1165e5c63d91SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1166e5c63d91SLucas Stach struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1167e5c63d91SLucas Stach const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1168e5c63d91SLucas Stach 1169e5c63d91SLucas Stach if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1170e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 1171e5c63d91SLucas Stach } 1172e5c63d91SLucas Stach 1173b7754428SSowjanya Komatineni static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1174b7754428SSowjanya Komatineni { 1175b7754428SSowjanya Komatineni struct mmc_host *mmc = cq_host->mmc; 11765ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 1177b7754428SSowjanya Komatineni u8 ctrl; 1178b7754428SSowjanya Komatineni ktime_t timeout; 1179b7754428SSowjanya Komatineni bool timed_out; 1180b7754428SSowjanya Komatineni 1181b7754428SSowjanya Komatineni /* 1182b7754428SSowjanya Komatineni * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1183b7754428SSowjanya Komatineni * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1184b7754428SSowjanya Komatineni * to be re-configured. 1185b7754428SSowjanya Komatineni * Tegra CQHCI/SDHCI prevents write access to block size register when 1186b7754428SSowjanya Komatineni * CQE is unhalted. So handling CQE resume sequence here to configure 1187b7754428SSowjanya Komatineni * SDHCI block registers prior to exiting CQE halt state. 1188b7754428SSowjanya Komatineni */ 1189b7754428SSowjanya Komatineni if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1190b7754428SSowjanya Komatineni cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 11915ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1192b7754428SSowjanya Komatineni sdhci_cqe_enable(mmc); 1193b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1194b7754428SSowjanya Komatineni timeout = ktime_add_us(ktime_get(), 50); 1195b7754428SSowjanya Komatineni while (1) { 1196b7754428SSowjanya Komatineni timed_out = ktime_compare(ktime_get(), timeout) > 0; 1197b7754428SSowjanya Komatineni ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1198b7754428SSowjanya Komatineni if (!(ctrl & CQHCI_HALT) || timed_out) 1199b7754428SSowjanya Komatineni break; 1200b7754428SSowjanya Komatineni } 1201b7754428SSowjanya Komatineni /* 1202b7754428SSowjanya Komatineni * CQE usually resumes very quick, but incase if Tegra CQE 1203b7754428SSowjanya Komatineni * doesn't resume retry unhalt. 1204b7754428SSowjanya Komatineni */ 1205b7754428SSowjanya Komatineni if (timed_out) 1206b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1207b7754428SSowjanya Komatineni } else { 1208b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1209b7754428SSowjanya Komatineni } 1210b7754428SSowjanya Komatineni } 1211b7754428SSowjanya Komatineni 1212c6e7ab90SSowjanya Komatineni static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1213c6e7ab90SSowjanya Komatineni struct mmc_request *mrq, u64 *data) 1214c6e7ab90SSowjanya Komatineni { 1215c6e7ab90SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1216c6e7ab90SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1217c6e7ab90SSowjanya Komatineni const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1218c6e7ab90SSowjanya Komatineni 1219c6e7ab90SSowjanya Komatineni if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1220c6e7ab90SSowjanya Komatineni mrq->cmd->flags & MMC_RSP_R1B) 1221c6e7ab90SSowjanya Komatineni *data |= CQHCI_CMD_TIMING(1); 1222c6e7ab90SSowjanya Komatineni } 1223c6e7ab90SSowjanya Komatineni 12243c4019f9SSowjanya Komatineni static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 12253c4019f9SSowjanya Komatineni { 12263c4019f9SSowjanya Komatineni struct cqhci_host *cq_host = mmc->cqe_private; 12275ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 1228b7754428SSowjanya Komatineni u32 val; 12293c4019f9SSowjanya Komatineni 12303c4019f9SSowjanya Komatineni /* 1231b7754428SSowjanya Komatineni * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1232b7754428SSowjanya Komatineni * register when CQE is enabled and unhalted. 1233b7754428SSowjanya Komatineni * CQHCI driver enables CQE prior to activation, so disable CQE before 1234b7754428SSowjanya Komatineni * programming block size in sdhci controller and enable it back. 12353c4019f9SSowjanya Komatineni */ 1236b7754428SSowjanya Komatineni if (!cq_host->activated) { 1237b7754428SSowjanya Komatineni val = cqhci_readl(cq_host, CQHCI_CFG); 1238b7754428SSowjanya Komatineni if (val & CQHCI_ENABLE) 1239b7754428SSowjanya Komatineni cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1240b7754428SSowjanya Komatineni CQHCI_CFG); 12415ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 12423c4019f9SSowjanya Komatineni sdhci_cqe_enable(mmc); 1243b7754428SSowjanya Komatineni if (val & CQHCI_ENABLE) 1244b7754428SSowjanya Komatineni cqhci_writel(cq_host, val, CQHCI_CFG); 1245b7754428SSowjanya Komatineni } 12463c4019f9SSowjanya Komatineni 1247b7754428SSowjanya Komatineni /* 1248b7754428SSowjanya Komatineni * CMD CRC errors are seen sometimes with some eMMC devices when status 1249b7754428SSowjanya Komatineni * command is sent during transfer of last data block which is the 1250b7754428SSowjanya Komatineni * default case as send status command block counter (CBC) is 1. 1251b7754428SSowjanya Komatineni * Recommended fix to set CBC to 0 allowing send status command only 1252b7754428SSowjanya Komatineni * when data lines are idle. 1253b7754428SSowjanya Komatineni */ 1254b7754428SSowjanya Komatineni val = cqhci_readl(cq_host, CQHCI_SSC1); 1255b7754428SSowjanya Komatineni val &= ~CQHCI_SSC1_CBC_MASK; 1256b7754428SSowjanya Komatineni cqhci_writel(cq_host, val, CQHCI_SSC1); 12573c4019f9SSowjanya Komatineni } 12583c4019f9SSowjanya Komatineni 12593c4019f9SSowjanya Komatineni static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 12603c4019f9SSowjanya Komatineni { 12613c4019f9SSowjanya Komatineni sdhci_dumpregs(mmc_priv(mmc)); 12623c4019f9SSowjanya Komatineni } 12633c4019f9SSowjanya Komatineni 12643c4019f9SSowjanya Komatineni static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 12653c4019f9SSowjanya Komatineni { 12663c4019f9SSowjanya Komatineni int cmd_error = 0; 12673c4019f9SSowjanya Komatineni int data_error = 0; 12683c4019f9SSowjanya Komatineni 12693c4019f9SSowjanya Komatineni if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 12703c4019f9SSowjanya Komatineni return intmask; 12713c4019f9SSowjanya Komatineni 12723c4019f9SSowjanya Komatineni cqhci_irq(host->mmc, intmask, cmd_error, data_error); 12733c4019f9SSowjanya Komatineni 12743c4019f9SSowjanya Komatineni return 0; 12753c4019f9SSowjanya Komatineni } 12763c4019f9SSowjanya Komatineni 12775e958e4aSSowjanya Komatineni static void tegra_sdhci_set_timeout(struct sdhci_host *host, 12785e958e4aSSowjanya Komatineni struct mmc_command *cmd) 12795e958e4aSSowjanya Komatineni { 12805e958e4aSSowjanya Komatineni u32 val; 12815e958e4aSSowjanya Komatineni 12825e958e4aSSowjanya Komatineni /* 12835e958e4aSSowjanya Komatineni * HW busy detection timeout is based on programmed data timeout 12845e958e4aSSowjanya Komatineni * counter and maximum supported timeout is 11s which may not be 12855e958e4aSSowjanya Komatineni * enough for long operations like cache flush, sleep awake, erase. 12865e958e4aSSowjanya Komatineni * 12875e958e4aSSowjanya Komatineni * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 12885e958e4aSSowjanya Komatineni * host controller to wait for busy state until the card is busy 12895e958e4aSSowjanya Komatineni * without HW timeout. 12905e958e4aSSowjanya Komatineni * 12915e958e4aSSowjanya Komatineni * So, use infinite busy wait mode for operations that may take 12925e958e4aSSowjanya Komatineni * more than maximum HW busy timeout of 11s otherwise use finite 12935e958e4aSSowjanya Komatineni * busy wait mode. 12945e958e4aSSowjanya Komatineni */ 12955e958e4aSSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1296fcc541feSWolfram Sang if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) 12975e958e4aSSowjanya Komatineni val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 12985e958e4aSSowjanya Komatineni else 12995e958e4aSSowjanya Komatineni val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 13005e958e4aSSowjanya Komatineni sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 13015e958e4aSSowjanya Komatineni 13025e958e4aSSowjanya Komatineni __sdhci_set_timeout(host, cmd); 13035e958e4aSSowjanya Komatineni } 13045e958e4aSSowjanya Komatineni 13055ec6fa5aSAniruddha Tvs Rao static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc) 13065ec6fa5aSAniruddha Tvs Rao { 13075ec6fa5aSAniruddha Tvs Rao struct cqhci_host *cq_host = mmc->cqe_private; 13085ec6fa5aSAniruddha Tvs Rao u32 reg; 13095ec6fa5aSAniruddha Tvs Rao 13105ec6fa5aSAniruddha Tvs Rao reg = cqhci_readl(cq_host, CQHCI_CFG); 13115ec6fa5aSAniruddha Tvs Rao reg |= CQHCI_ENABLE; 13125ec6fa5aSAniruddha Tvs Rao cqhci_writel(cq_host, reg, CQHCI_CFG); 13135ec6fa5aSAniruddha Tvs Rao } 13145ec6fa5aSAniruddha Tvs Rao 13155ec6fa5aSAniruddha Tvs Rao static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc) 13165ec6fa5aSAniruddha Tvs Rao { 13175ec6fa5aSAniruddha Tvs Rao struct cqhci_host *cq_host = mmc->cqe_private; 13185ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 13195ec6fa5aSAniruddha Tvs Rao u32 reg; 13205ec6fa5aSAniruddha Tvs Rao 13215ec6fa5aSAniruddha Tvs Rao reg = cqhci_readl(cq_host, CQHCI_CFG); 13225ec6fa5aSAniruddha Tvs Rao reg &= ~CQHCI_ENABLE; 13235ec6fa5aSAniruddha Tvs Rao cqhci_writel(cq_host, reg, CQHCI_CFG); 13245ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 13255ec6fa5aSAniruddha Tvs Rao } 13265ec6fa5aSAniruddha Tvs Rao 13273c4019f9SSowjanya Komatineni static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1328b7754428SSowjanya Komatineni .write_l = tegra_cqhci_writel, 13293c4019f9SSowjanya Komatineni .enable = sdhci_tegra_cqe_enable, 13303c4019f9SSowjanya Komatineni .disable = sdhci_cqe_disable, 13313c4019f9SSowjanya Komatineni .dumpregs = sdhci_tegra_dumpregs, 1332c6e7ab90SSowjanya Komatineni .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 13335ec6fa5aSAniruddha Tvs Rao .pre_enable = sdhci_tegra_cqe_pre_enable, 13345ec6fa5aSAniruddha Tvs Rao .post_disable = sdhci_tegra_cqe_post_disable, 13353c4019f9SSowjanya Komatineni }; 13363c4019f9SSowjanya Komatineni 1337b960bc44SNicolin Chen static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1338b960bc44SNicolin Chen { 1339b960bc44SNicolin Chen struct sdhci_pltfm_host *platform = sdhci_priv(host); 1340b960bc44SNicolin Chen struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1341b960bc44SNicolin Chen const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1342b960bc44SNicolin Chen struct device *dev = mmc_dev(host->mmc); 1343b960bc44SNicolin Chen 1344b960bc44SNicolin Chen if (soc->dma_mask) 1345b960bc44SNicolin Chen return dma_set_mask_and_coherent(dev, soc->dma_mask); 1346b960bc44SNicolin Chen 1347b960bc44SNicolin Chen return 0; 1348b960bc44SNicolin Chen } 1349b960bc44SNicolin Chen 1350c915568dSLars-Peter Clausen static const struct sdhci_ops tegra_sdhci_ops = { 13510f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 135285d6509dSShawn Guo .read_w = tegra_sdhci_readw, 135385d6509dSShawn Guo .write_l = tegra_sdhci_writel, 1354a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 1355b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 135614b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 135703231f9bSRussell King .reset = tegra_sdhci_reset, 1358c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 1359a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1360e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 136144350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 136285d6509dSShawn Guo }; 136303d2bfc8SOlof Johansson 13641db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 136585d6509dSShawn Guo .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 136685d6509dSShawn Guo SDHCI_QUIRK_SINGLE_POWER_WRITE | 136785d6509dSShawn Guo SDHCI_QUIRK_NO_HISPD_BIT | 1368f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1369f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 137085d6509dSShawn Guo .ops = &tegra_sdhci_ops, 137185d6509dSShawn Guo }; 137285d6509dSShawn Guo 1373d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 13743e44a1a7SStephen Warren .pdata = &sdhci_tegra20_pdata, 1375b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 13763e44a1a7SStephen Warren .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 13771743fa54SDmitry Osipenko NVQUIRK_HAS_ANDROID_GPT_SECTOR | 13783e44a1a7SStephen Warren NVQUIRK_ENABLE_BLOCK_GAP_DET, 13793e44a1a7SStephen Warren }; 13803e44a1a7SStephen Warren 13811db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 13823e44a1a7SStephen Warren .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 13833e44a1a7SStephen Warren SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 13843e44a1a7SStephen Warren SDHCI_QUIRK_SINGLE_POWER_WRITE | 13853e44a1a7SStephen Warren SDHCI_QUIRK_NO_HISPD_BIT | 1386f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1387f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1388127407e3SStefan Agner .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1389726df1d5SStefan Agner SDHCI_QUIRK2_BROKEN_HS200 | 1390726df1d5SStefan Agner /* 1391726df1d5SStefan Agner * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1392726df1d5SStefan Agner * though no command operation was in progress." 1393726df1d5SStefan Agner * 1394726df1d5SStefan Agner * The exact reason is unknown, as the same hardware seems 1395726df1d5SStefan Agner * to support Auto CMD23 on a downstream 3.1 kernel. 1396726df1d5SStefan Agner */ 1397726df1d5SStefan Agner SDHCI_QUIRK2_ACMD23_BROKEN, 13983e44a1a7SStephen Warren .ops = &tegra_sdhci_ops, 13993e44a1a7SStephen Warren }; 14003e44a1a7SStephen Warren 1401d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 14023e44a1a7SStephen Warren .pdata = &sdhci_tegra30_pdata, 1403b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 14043145351aSAndrew Bresticker .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 14057ad2ed1dSLucas Stach NVQUIRK_ENABLE_SDR50 | 1406e5c63d91SLucas Stach NVQUIRK_ENABLE_SDR104 | 14071743fa54SDmitry Osipenko NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1408e5c63d91SLucas Stach NVQUIRK_HAS_PADCALIB, 14093e44a1a7SStephen Warren }; 14103e44a1a7SStephen Warren 141101df7ecdSRhyland Klein static const struct sdhci_ops tegra114_sdhci_ops = { 14120f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 141301df7ecdSRhyland Klein .read_w = tegra_sdhci_readw, 141401df7ecdSRhyland Klein .write_w = tegra_sdhci_writew, 141501df7ecdSRhyland Klein .write_l = tegra_sdhci_writel, 1416a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 1417b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 141814b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 141901df7ecdSRhyland Klein .reset = tegra_sdhci_reset, 1420c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 1421a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1422e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 142344350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 142401df7ecdSRhyland Klein }; 142501df7ecdSRhyland Klein 14261db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 14275ebf2552SRhyland Klein .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 14285ebf2552SRhyland Klein SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 14295ebf2552SRhyland Klein SDHCI_QUIRK_SINGLE_POWER_WRITE | 14305ebf2552SRhyland Klein SDHCI_QUIRK_NO_HISPD_BIT | 1431f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1432f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1433a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 143401df7ecdSRhyland Klein .ops = &tegra114_sdhci_ops, 14355ebf2552SRhyland Klein }; 14365ebf2552SRhyland Klein 1437d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 14385ebf2552SRhyland Klein .pdata = &sdhci_tegra114_pdata, 1439b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 14401743fa54SDmitry Osipenko .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 14417bf037d6SJon Hunter }; 14427bf037d6SJon Hunter 14434ae12588SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 14444ae12588SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 14454ae12588SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 14464ae12588SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 14474ae12588SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 14484ae12588SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 14494ae12588SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1450b960bc44SNicolin Chen .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 14514ae12588SThierry Reding .ops = &tegra114_sdhci_ops, 14524ae12588SThierry Reding }; 14534ae12588SThierry Reding 14544ae12588SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 14554ae12588SThierry Reding .pdata = &sdhci_tegra124_pdata, 1456b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(34), 14571743fa54SDmitry Osipenko .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 14584ae12588SThierry Reding }; 14594ae12588SThierry Reding 14601070e83aSAapo Vienamo static const struct sdhci_ops tegra210_sdhci_ops = { 14610f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 14621070e83aSAapo Vienamo .read_w = tegra_sdhci_readw, 146338a284d9SAapo Vienamo .write_w = tegra210_sdhci_writew, 14641070e83aSAapo Vienamo .write_l = tegra_sdhci_writel, 14651070e83aSAapo Vienamo .set_clock = tegra_sdhci_set_clock, 1466b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 14671070e83aSAapo Vienamo .set_bus_width = sdhci_set_bus_width, 14681070e83aSAapo Vienamo .reset = tegra_sdhci_reset, 14691070e83aSAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 14701070e83aSAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 14711070e83aSAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 14725e958e4aSSowjanya Komatineni .set_timeout = tegra_sdhci_set_timeout, 14731070e83aSAapo Vienamo }; 14741070e83aSAapo Vienamo 1475b5a84ecfSThierry Reding static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1476b5a84ecfSThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1477b5a84ecfSThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 1478b5a84ecfSThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 1479a8e326a9SLucas Stach SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1480a8e326a9SLucas Stach SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1481a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 14821070e83aSAapo Vienamo .ops = &tegra210_sdhci_ops, 1483b5a84ecfSThierry Reding }; 1484b5a84ecfSThierry Reding 1485b5a84ecfSThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1486b5a84ecfSThierry Reding .pdata = &sdhci_tegra210_pdata, 1487b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(34), 1488d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1489d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 14903559d4a6SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 14913559d4a6SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 14928048822bSSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 14938048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK, 1494ea8fc595SSowjanya Komatineni .min_tap_delay = 106, 1495ea8fc595SSowjanya Komatineni .max_tap_delay = 185, 1496b5a84ecfSThierry Reding }; 1497b5a84ecfSThierry Reding 149838a284d9SAapo Vienamo static const struct sdhci_ops tegra186_sdhci_ops = { 14990f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 150038a284d9SAapo Vienamo .read_w = tegra_sdhci_readw, 150138a284d9SAapo Vienamo .write_l = tegra_sdhci_writel, 150238a284d9SAapo Vienamo .set_clock = tegra_sdhci_set_clock, 1503b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 150438a284d9SAapo Vienamo .set_bus_width = sdhci_set_bus_width, 150538a284d9SAapo Vienamo .reset = tegra_sdhci_reset, 150638a284d9SAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 150738a284d9SAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 150838a284d9SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 15093c4019f9SSowjanya Komatineni .irq = sdhci_tegra_cqhci_irq, 15105e958e4aSSowjanya Komatineni .set_timeout = tegra_sdhci_set_timeout, 151138a284d9SAapo Vienamo }; 151238a284d9SAapo Vienamo 15134346b7c7SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 15144346b7c7SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 15154346b7c7SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 15164346b7c7SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 15174346b7c7SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 15184346b7c7SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1519b960bc44SNicolin Chen .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 152038a284d9SAapo Vienamo .ops = &tegra186_sdhci_ops, 15214346b7c7SThierry Reding }; 15224346b7c7SThierry Reding 15234346b7c7SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 15244346b7c7SThierry Reding .pdata = &sdhci_tegra186_pdata, 1525b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(40), 1526d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1527d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 15282ad50051SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 15292ad50051SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 1530c6e7ab90SSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 15318048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK | 1532c6e7ab90SSowjanya Komatineni NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1533ea8fc595SSowjanya Komatineni .min_tap_delay = 84, 1534ea8fc595SSowjanya Komatineni .max_tap_delay = 136, 1535ea8fc595SSowjanya Komatineni }; 1536ea8fc595SSowjanya Komatineni 1537ea8fc595SSowjanya Komatineni static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1538ea8fc595SSowjanya Komatineni .pdata = &sdhci_tegra186_pdata, 1539b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(39), 1540ea8fc595SSowjanya Komatineni .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1541ea8fc595SSowjanya Komatineni NVQUIRK_HAS_PADCALIB | 1542ea8fc595SSowjanya Komatineni NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1543ea8fc595SSowjanya Komatineni NVQUIRK_ENABLE_SDR50 | 15448048822bSSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 15458048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK, 1546ea8fc595SSowjanya Komatineni .min_tap_delay = 96, 1547ea8fc595SSowjanya Komatineni .max_tap_delay = 139, 15484346b7c7SThierry Reding }; 15494346b7c7SThierry Reding 1550498d83e7SBill Pemberton static const struct of_device_id sdhci_tegra_dt_match[] = { 1551ea8fc595SSowjanya Komatineni { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 15524346b7c7SThierry Reding { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1553b5a84ecfSThierry Reding { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 15544ae12588SThierry Reding { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 15555ebf2552SRhyland Klein { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 15563e44a1a7SStephen Warren { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 15573e44a1a7SStephen Warren { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1558275173b2SGrant Likely {} 1559275173b2SGrant Likely }; 1560e4404fabSArnd Bergmann MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1561275173b2SGrant Likely 15623c4019f9SSowjanya Komatineni static int sdhci_tegra_add_host(struct sdhci_host *host) 15633c4019f9SSowjanya Komatineni { 15643c4019f9SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 15653c4019f9SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 15663c4019f9SSowjanya Komatineni struct cqhci_host *cq_host; 15673c4019f9SSowjanya Komatineni bool dma64; 15683c4019f9SSowjanya Komatineni int ret; 15693c4019f9SSowjanya Komatineni 15703c4019f9SSowjanya Komatineni if (!tegra_host->enable_hwcq) 15713c4019f9SSowjanya Komatineni return sdhci_add_host(host); 15723c4019f9SSowjanya Komatineni 15733c4019f9SSowjanya Komatineni sdhci_enable_v4_mode(host); 15743c4019f9SSowjanya Komatineni 15753c4019f9SSowjanya Komatineni ret = sdhci_setup_host(host); 15763c4019f9SSowjanya Komatineni if (ret) 15773c4019f9SSowjanya Komatineni return ret; 15783c4019f9SSowjanya Komatineni 15793c4019f9SSowjanya Komatineni host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 15803c4019f9SSowjanya Komatineni 1581bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), 15823c4019f9SSowjanya Komatineni sizeof(*cq_host), GFP_KERNEL); 15833c4019f9SSowjanya Komatineni if (!cq_host) { 15843c4019f9SSowjanya Komatineni ret = -ENOMEM; 15853c4019f9SSowjanya Komatineni goto cleanup; 15863c4019f9SSowjanya Komatineni } 15873c4019f9SSowjanya Komatineni 15883c4019f9SSowjanya Komatineni cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 15893c4019f9SSowjanya Komatineni cq_host->ops = &sdhci_tegra_cqhci_ops; 15903c4019f9SSowjanya Komatineni 15913c4019f9SSowjanya Komatineni dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 15923c4019f9SSowjanya Komatineni if (dma64) 15933c4019f9SSowjanya Komatineni cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 15943c4019f9SSowjanya Komatineni 15953c4019f9SSowjanya Komatineni ret = cqhci_init(cq_host, host->mmc, dma64); 15963c4019f9SSowjanya Komatineni if (ret) 15973c4019f9SSowjanya Komatineni goto cleanup; 15983c4019f9SSowjanya Komatineni 15993c4019f9SSowjanya Komatineni ret = __sdhci_add_host(host); 16003c4019f9SSowjanya Komatineni if (ret) 16013c4019f9SSowjanya Komatineni goto cleanup; 16023c4019f9SSowjanya Komatineni 16033c4019f9SSowjanya Komatineni return 0; 16043c4019f9SSowjanya Komatineni 16053c4019f9SSowjanya Komatineni cleanup: 16063c4019f9SSowjanya Komatineni sdhci_cleanup_host(host); 16073c4019f9SSowjanya Komatineni return ret; 16083c4019f9SSowjanya Komatineni } 16093c4019f9SSowjanya Komatineni 1610c3be1efdSBill Pemberton static int sdhci_tegra_probe(struct platform_device *pdev) 161103d2bfc8SOlof Johansson { 16123e44a1a7SStephen Warren const struct of_device_id *match; 16133e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 16143e44a1a7SStephen Warren struct sdhci_host *host; 161585d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 16163e44a1a7SStephen Warren struct sdhci_tegra *tegra_host; 161703d2bfc8SOlof Johansson struct clk *clk; 161803d2bfc8SOlof Johansson int rc; 161903d2bfc8SOlof Johansson 16203e44a1a7SStephen Warren match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1621b37f9d98SJoseph Lo if (!match) 1622b37f9d98SJoseph Lo return -EINVAL; 16233e44a1a7SStephen Warren soc_data = match->data; 16243e44a1a7SStephen Warren 16250734e79cSJisheng Zhang host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 162685d6509dSShawn Guo if (IS_ERR(host)) 162785d6509dSShawn Guo return PTR_ERR(host); 162885d6509dSShawn Guo pltfm_host = sdhci_priv(host); 162985d6509dSShawn Guo 16300734e79cSJisheng Zhang tegra_host = sdhci_pltfm_priv(pltfm_host); 1631a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 1632e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 163386ac2f8bSAapo Vienamo tegra_host->pad_control_available = false; 16343e44a1a7SStephen Warren tegra_host->soc_data = soc_data; 1635275173b2SGrant Likely 16361743fa54SDmitry Osipenko if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) 16371743fa54SDmitry Osipenko host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; 16381743fa54SDmitry Osipenko 163986ac2f8bSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 164086ac2f8bSAapo Vienamo rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 164186ac2f8bSAapo Vienamo if (rc == 0) 164286ac2f8bSAapo Vienamo host->mmc_host_ops.start_signal_voltage_switch = 164386ac2f8bSAapo Vienamo sdhci_tegra_start_signal_voltage_switch; 164486ac2f8bSAapo Vienamo } 164586ac2f8bSAapo Vienamo 164661dad40eSAapo Vienamo /* Hook to periodically rerun pad calibration */ 164761dad40eSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 164861dad40eSAapo Vienamo host->mmc_host_ops.request = tegra_sdhci_request; 164961dad40eSAapo Vienamo 1650dfc9700cSAapo Vienamo host->mmc_host_ops.hs400_enhanced_strobe = 1651dfc9700cSAapo Vienamo tegra_sdhci_hs400_enhanced_strobe; 1652dfc9700cSAapo Vienamo 1653ea8fc595SSowjanya Komatineni if (!host->ops->platform_execute_tuning) 1654ea8fc595SSowjanya Komatineni host->mmc_host_ops.execute_tuning = 1655ea8fc595SSowjanya Komatineni tegra_sdhci_execute_hw_tuning; 1656ea8fc595SSowjanya Komatineni 16572391b340SMylene JOSSERAND rc = mmc_of_parse(host->mmc); 165847caa84fSSimon Baatz if (rc) 165947caa84fSSimon Baatz goto err_parse_dt; 16600e786102SStephen Warren 16617ad2ed1dSLucas Stach if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1662c3c2384cSLucas Stach host->mmc->caps |= MMC_CAP_1_8V_DDR; 1663c3c2384cSLucas Stach 1664ff124c31SSowjanya Komatineni /* HW busy detection is supported, but R1B responses are required. */ 1665ff124c31SSowjanya Komatineni host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1666d2f8bfa4SUlf Hansson 16673c4019f9SSowjanya Komatineni tegra_sdhci_parse_dt(host); 166885c0da17SAapo Vienamo 16692391b340SMylene JOSSERAND tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 16702391b340SMylene JOSSERAND GPIOD_OUT_HIGH); 16712391b340SMylene JOSSERAND if (IS_ERR(tegra_host->power_gpio)) { 16722391b340SMylene JOSSERAND rc = PTR_ERR(tegra_host->power_gpio); 167385d6509dSShawn Guo goto err_power_req; 167403d2bfc8SOlof Johansson } 167503d2bfc8SOlof Johansson 16768048822bSSowjanya Komatineni /* 16778048822bSSowjanya Komatineni * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host 16788048822bSSowjanya Komatineni * timeout clock and SW can choose TMCLK or SDCLK for hardware 16798048822bSSowjanya Komatineni * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of 16808048822bSSowjanya Komatineni * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL. 16818048822bSSowjanya Komatineni * 16828048822bSSowjanya Komatineni * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses 16838048822bSSowjanya Komatineni * 12Mhz TMCLK which is advertised in host capability register. 16848048822bSSowjanya Komatineni * With TMCLK of 12Mhz provides maximum data timeout period that can 16858048822bSSowjanya Komatineni * be achieved is 11s better than using SDCLK for data timeout. 16868048822bSSowjanya Komatineni * 16878048822bSSowjanya Komatineni * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's 16888048822bSSowjanya Komatineni * supporting separate TMCLK. 16898048822bSSowjanya Komatineni */ 16908048822bSSowjanya Komatineni 16918048822bSSowjanya Komatineni if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { 16928048822bSSowjanya Komatineni clk = devm_clk_get(&pdev->dev, "tmclk"); 16938048822bSSowjanya Komatineni if (IS_ERR(clk)) { 16948048822bSSowjanya Komatineni rc = PTR_ERR(clk); 16958048822bSSowjanya Komatineni if (rc == -EPROBE_DEFER) 16968048822bSSowjanya Komatineni goto err_power_req; 16978048822bSSowjanya Komatineni 16988048822bSSowjanya Komatineni dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 16998048822bSSowjanya Komatineni clk = NULL; 17008048822bSSowjanya Komatineni } 17018048822bSSowjanya Komatineni 17028048822bSSowjanya Komatineni clk_set_rate(clk, 12000000); 17038048822bSSowjanya Komatineni rc = clk_prepare_enable(clk); 17048048822bSSowjanya Komatineni if (rc) { 17058048822bSSowjanya Komatineni dev_err(&pdev->dev, 17068048822bSSowjanya Komatineni "failed to enable tmclk: %d\n", rc); 17078048822bSSowjanya Komatineni goto err_power_req; 17088048822bSSowjanya Komatineni } 17098048822bSSowjanya Komatineni 17108048822bSSowjanya Komatineni tegra_host->tmclk = clk; 17118048822bSSowjanya Komatineni } 17128048822bSSowjanya Komatineni 1713e4f79d9cSKevin Hao clk = devm_clk_get(mmc_dev(host->mmc), NULL); 171403d2bfc8SOlof Johansson if (IS_ERR(clk)) { 1715180a4665SKrzysztof Kozlowski rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), 1716180a4665SKrzysztof Kozlowski "failed to get clock\n"); 171785d6509dSShawn Guo goto err_clk_get; 171803d2bfc8SOlof Johansson } 171903d2bfc8SOlof Johansson pltfm_host->clk = clk; 172003d2bfc8SOlof Johansson 17212cd6c49dSPhilipp Zabel tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 17222cd6c49dSPhilipp Zabel "sdhci"); 172320567be9SThierry Reding if (IS_ERR(tegra_host->rst)) { 172420567be9SThierry Reding rc = PTR_ERR(tegra_host->rst); 172520567be9SThierry Reding dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 172620567be9SThierry Reding goto err_rst_get; 172720567be9SThierry Reding } 172820567be9SThierry Reding 1729*d618978dSDmitry Osipenko rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 173020567be9SThierry Reding if (rc) 173120567be9SThierry Reding goto err_rst_get; 173220567be9SThierry Reding 1733*d618978dSDmitry Osipenko pm_runtime_enable(&pdev->dev); 1734*d618978dSDmitry Osipenko rc = pm_runtime_resume_and_get(&pdev->dev); 1735*d618978dSDmitry Osipenko if (rc) 1736*d618978dSDmitry Osipenko goto err_pm_get; 1737*d618978dSDmitry Osipenko 1738*d618978dSDmitry Osipenko rc = reset_control_assert(tegra_host->rst); 1739*d618978dSDmitry Osipenko if (rc) 1740*d618978dSDmitry Osipenko goto err_rst_assert; 1741*d618978dSDmitry Osipenko 174220567be9SThierry Reding usleep_range(2000, 4000); 174320567be9SThierry Reding 174420567be9SThierry Reding rc = reset_control_deassert(tegra_host->rst); 174520567be9SThierry Reding if (rc) 1746*d618978dSDmitry Osipenko goto err_rst_assert; 174720567be9SThierry Reding 174820567be9SThierry Reding usleep_range(2000, 4000); 174920567be9SThierry Reding 17503c4019f9SSowjanya Komatineni rc = sdhci_tegra_add_host(host); 175185d6509dSShawn Guo if (rc) 175285d6509dSShawn Guo goto err_add_host; 175385d6509dSShawn Guo 175403d2bfc8SOlof Johansson return 0; 175503d2bfc8SOlof Johansson 175685d6509dSShawn Guo err_add_host: 175720567be9SThierry Reding reset_control_assert(tegra_host->rst); 1758*d618978dSDmitry Osipenko err_rst_assert: 1759*d618978dSDmitry Osipenko pm_runtime_put_sync_suspend(&pdev->dev); 1760*d618978dSDmitry Osipenko err_pm_get: 1761*d618978dSDmitry Osipenko pm_runtime_disable(&pdev->dev); 176220567be9SThierry Reding err_rst_get: 176385d6509dSShawn Guo err_clk_get: 17648048822bSSowjanya Komatineni clk_disable_unprepare(tegra_host->tmclk); 176585d6509dSShawn Guo err_power_req: 176647caa84fSSimon Baatz err_parse_dt: 176785d6509dSShawn Guo sdhci_pltfm_free(pdev); 176803d2bfc8SOlof Johansson return rc; 176903d2bfc8SOlof Johansson } 177003d2bfc8SOlof Johansson 177120567be9SThierry Reding static int sdhci_tegra_remove(struct platform_device *pdev) 177220567be9SThierry Reding { 177320567be9SThierry Reding struct sdhci_host *host = platform_get_drvdata(pdev); 177420567be9SThierry Reding struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177520567be9SThierry Reding struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 177620567be9SThierry Reding 177720567be9SThierry Reding sdhci_remove_host(host, 0); 177820567be9SThierry Reding 177920567be9SThierry Reding reset_control_assert(tegra_host->rst); 178020567be9SThierry Reding usleep_range(2000, 4000); 178120567be9SThierry Reding 1782*d618978dSDmitry Osipenko pm_runtime_put_sync_suspend(&pdev->dev); 1783*d618978dSDmitry Osipenko pm_runtime_force_suspend(&pdev->dev); 1784*d618978dSDmitry Osipenko 1785*d618978dSDmitry Osipenko clk_disable_unprepare(tegra_host->tmclk); 178620567be9SThierry Reding sdhci_pltfm_free(pdev); 178720567be9SThierry Reding 178820567be9SThierry Reding return 0; 178920567be9SThierry Reding } 179020567be9SThierry Reding 1791*d618978dSDmitry Osipenko static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev) 179271c733c4SSowjanya Komatineni { 179371c733c4SSowjanya Komatineni struct sdhci_host *host = dev_get_drvdata(dev); 179471c733c4SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1795*d618978dSDmitry Osipenko 1796*d618978dSDmitry Osipenko clk_disable_unprepare(pltfm_host->clk); 1797*d618978dSDmitry Osipenko 1798*d618978dSDmitry Osipenko return 0; 1799*d618978dSDmitry Osipenko } 1800*d618978dSDmitry Osipenko 1801*d618978dSDmitry Osipenko static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev) 1802*d618978dSDmitry Osipenko { 1803*d618978dSDmitry Osipenko struct sdhci_host *host = dev_get_drvdata(dev); 1804*d618978dSDmitry Osipenko struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1805*d618978dSDmitry Osipenko 1806*d618978dSDmitry Osipenko return clk_prepare_enable(pltfm_host->clk); 1807*d618978dSDmitry Osipenko } 1808*d618978dSDmitry Osipenko 1809*d618978dSDmitry Osipenko #ifdef CONFIG_PM_SLEEP 1810*d618978dSDmitry Osipenko static int sdhci_tegra_suspend(struct device *dev) 1811*d618978dSDmitry Osipenko { 1812*d618978dSDmitry Osipenko struct sdhci_host *host = dev_get_drvdata(dev); 181371c733c4SSowjanya Komatineni int ret; 181471c733c4SSowjanya Komatineni 181571c733c4SSowjanya Komatineni if (host->mmc->caps2 & MMC_CAP2_CQE) { 181671c733c4SSowjanya Komatineni ret = cqhci_suspend(host->mmc); 181771c733c4SSowjanya Komatineni if (ret) 181871c733c4SSowjanya Komatineni return ret; 181971c733c4SSowjanya Komatineni } 182071c733c4SSowjanya Komatineni 182171c733c4SSowjanya Komatineni ret = sdhci_suspend_host(host); 182271c733c4SSowjanya Komatineni if (ret) { 182371c733c4SSowjanya Komatineni cqhci_resume(host->mmc); 182471c733c4SSowjanya Komatineni return ret; 182571c733c4SSowjanya Komatineni } 182671c733c4SSowjanya Komatineni 1827*d618978dSDmitry Osipenko ret = pm_runtime_force_suspend(dev); 1828*d618978dSDmitry Osipenko if (ret) { 1829*d618978dSDmitry Osipenko sdhci_resume_host(host); 1830*d618978dSDmitry Osipenko cqhci_resume(host->mmc); 1831*d618978dSDmitry Osipenko return ret; 1832*d618978dSDmitry Osipenko } 1833*d618978dSDmitry Osipenko 183471c733c4SSowjanya Komatineni return 0; 183571c733c4SSowjanya Komatineni } 183671c733c4SSowjanya Komatineni 1837*d618978dSDmitry Osipenko static int sdhci_tegra_resume(struct device *dev) 183871c733c4SSowjanya Komatineni { 183971c733c4SSowjanya Komatineni struct sdhci_host *host = dev_get_drvdata(dev); 184071c733c4SSowjanya Komatineni int ret; 184171c733c4SSowjanya Komatineni 1842*d618978dSDmitry Osipenko ret = pm_runtime_force_resume(dev); 184371c733c4SSowjanya Komatineni if (ret) 184471c733c4SSowjanya Komatineni return ret; 184571c733c4SSowjanya Komatineni 184671c733c4SSowjanya Komatineni ret = sdhci_resume_host(host); 184771c733c4SSowjanya Komatineni if (ret) 184871c733c4SSowjanya Komatineni goto disable_clk; 184971c733c4SSowjanya Komatineni 185071c733c4SSowjanya Komatineni if (host->mmc->caps2 & MMC_CAP2_CQE) { 185171c733c4SSowjanya Komatineni ret = cqhci_resume(host->mmc); 185271c733c4SSowjanya Komatineni if (ret) 185371c733c4SSowjanya Komatineni goto suspend_host; 185471c733c4SSowjanya Komatineni } 185571c733c4SSowjanya Komatineni 185671c733c4SSowjanya Komatineni return 0; 185771c733c4SSowjanya Komatineni 185871c733c4SSowjanya Komatineni suspend_host: 185971c733c4SSowjanya Komatineni sdhci_suspend_host(host); 186071c733c4SSowjanya Komatineni disable_clk: 1861*d618978dSDmitry Osipenko pm_runtime_force_suspend(dev); 186271c733c4SSowjanya Komatineni return ret; 186371c733c4SSowjanya Komatineni } 186471c733c4SSowjanya Komatineni #endif 186571c733c4SSowjanya Komatineni 1866*d618978dSDmitry Osipenko static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = { 1867*d618978dSDmitry Osipenko SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume, 1868*d618978dSDmitry Osipenko NULL) 1869*d618978dSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume) 1870*d618978dSDmitry Osipenko }; 187171c733c4SSowjanya Komatineni 187285d6509dSShawn Guo static struct platform_driver sdhci_tegra_driver = { 187385d6509dSShawn Guo .driver = { 187485d6509dSShawn Guo .name = "sdhci-tegra", 187521b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1876275173b2SGrant Likely .of_match_table = sdhci_tegra_dt_match, 187771c733c4SSowjanya Komatineni .pm = &sdhci_tegra_dev_pm_ops, 187885d6509dSShawn Guo }, 187985d6509dSShawn Guo .probe = sdhci_tegra_probe, 188020567be9SThierry Reding .remove = sdhci_tegra_remove, 188103d2bfc8SOlof Johansson }; 188203d2bfc8SOlof Johansson 1883d1f81a64SAxel Lin module_platform_driver(sdhci_tegra_driver); 188485d6509dSShawn Guo 188585d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Tegra"); 188685d6509dSShawn Guo MODULE_AUTHOR("Google, Inc."); 188785d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1888