19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 203d2bfc8SOlof Johansson /* 303d2bfc8SOlof Johansson * Copyright (C) 2010 Google, Inc. 403d2bfc8SOlof Johansson */ 503d2bfc8SOlof Johansson 6e5c63d91SLucas Stach #include <linux/delay.h> 7b960bc44SNicolin Chen #include <linux/dma-mapping.h> 803d2bfc8SOlof Johansson #include <linux/err.h> 996547f5dSPaul Gortmaker #include <linux/module.h> 1003d2bfc8SOlof Johansson #include <linux/init.h> 11e7c07148SAapo Vienamo #include <linux/iopoll.h> 1203d2bfc8SOlof Johansson #include <linux/platform_device.h> 1303d2bfc8SOlof Johansson #include <linux/clk.h> 1403d2bfc8SOlof Johansson #include <linux/io.h> 1555cd65e4SStephen Warren #include <linux/of.h> 163e44a1a7SStephen Warren #include <linux/of_device.h> 1786ac2f8bSAapo Vienamo #include <linux/pinctrl/consumer.h> 1886ac2f8bSAapo Vienamo #include <linux/regulator/consumer.h> 1920567be9SThierry Reding #include <linux/reset.h> 2003d2bfc8SOlof Johansson #include <linux/mmc/card.h> 2103d2bfc8SOlof Johansson #include <linux/mmc/host.h> 22c3c2384cSLucas Stach #include <linux/mmc/mmc.h> 230aacd23fSJoseph Lo #include <linux/mmc/slot-gpio.h> 242391b340SMylene JOSSERAND #include <linux/gpio/consumer.h> 2561dad40eSAapo Vienamo #include <linux/ktime.h> 2603d2bfc8SOlof Johansson 2703d2bfc8SOlof Johansson #include "sdhci-pltfm.h" 283c4019f9SSowjanya Komatineni #include "cqhci.h" 2903d2bfc8SOlof Johansson 30ca5879d3SPavan Kunapuli /* Tegra SDHOST controller vendor register definitions */ 3174cd42bcSLucas Stach #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 32c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 33c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 3441a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 3541a0b8d7SAapo Vienamo #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 36c3c2384cSLucas Stach #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 3774cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 3874cd42bcSLucas Stach #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 3974cd42bcSLucas Stach 40dfc9700cSAapo Vienamo #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 41dfc9700cSAapo Vienamo #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 42dfc9700cSAapo Vienamo 43f5313aaaSAapo Vienamo #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 44f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 45f5313aaaSAapo Vienamo #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 46f5313aaaSAapo Vienamo 47ca5879d3SPavan Kunapuli #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 485e958e4aSSowjanya Komatineni #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 493145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 503145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 51ca5879d3SPavan Kunapuli #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 523145351aSAndrew Bresticker #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 53ca5879d3SPavan Kunapuli 54bc5568bfSAapo Vienamo #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 55bc5568bfSAapo Vienamo #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 56bc5568bfSAapo Vienamo 57bc5568bfSAapo Vienamo #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 58bc5568bfSAapo Vienamo #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 59bc5568bfSAapo Vienamo 60d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 61d4501d8eSAapo Vienamo #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 62ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 63ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 64ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 65ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 66ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 67ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 68ea8fc595SSowjanya Komatineni #define TRIES_128 2 69ea8fc595SSowjanya Komatineni #define TRIES_256 4 70ea8fc595SSowjanya Komatineni #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 71ea8fc595SSowjanya Komatineni 72ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 73ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 74ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 75ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 76ea8fc595SSowjanya Komatineni #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 77ea8fc595SSowjanya Komatineni #define TUNING_WORD_BIT_SIZE 32 78d4501d8eSAapo Vienamo 79e5c63d91SLucas Stach #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 80e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_START BIT(31) 81e5c63d91SLucas Stach #define SDHCI_AUTO_CAL_ENABLE BIT(29) 8251b77c8eSAapo Vienamo #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 83e5c63d91SLucas Stach 849d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 859d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 869d548f11SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 87212b0cf1SAapo Vienamo #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 88de25fa5aSSowjanya Komatineni #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 899d548f11SAapo Vienamo 90e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 91e7c07148SAapo Vienamo #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 92e7c07148SAapo Vienamo 933e44a1a7SStephen Warren #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 943e44a1a7SStephen Warren #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 95ca5879d3SPavan Kunapuli #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 967ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR50 BIT(3) 977ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_SDR104 BIT(4) 987ad2ed1dSLucas Stach #define NVQUIRK_ENABLE_DDR50 BIT(5) 9947fad46bSSowjanya Komatineni /* 10047fad46bSSowjanya Komatineni * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads 10147fad46bSSowjanya Komatineni * drive strength. 10247fad46bSSowjanya Komatineni */ 103e5c63d91SLucas Stach #define NVQUIRK_HAS_PADCALIB BIT(6) 10447fad46bSSowjanya Komatineni /* 10547fad46bSSowjanya Komatineni * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. 10647fad46bSSowjanya Komatineni * 3V3/1V8 pad selection happens through pinctrl state selection depending 10747fad46bSSowjanya Komatineni * on the signaling mode. 10847fad46bSSowjanya Komatineni */ 10986ac2f8bSAapo Vienamo #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 110d4501d8eSAapo Vienamo #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 111c6e7ab90SSowjanya Komatineni #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 1123e44a1a7SStephen Warren 1138048822bSSowjanya Komatineni /* 1148048822bSSowjanya Komatineni * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra 1158048822bSSowjanya Komatineni * SDMMC hardware data timeout. 1168048822bSSowjanya Komatineni */ 1178048822bSSowjanya Komatineni #define NVQUIRK_HAS_TMCLK BIT(10) 1188048822bSSowjanya Komatineni 1191743fa54SDmitry Osipenko #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 1201743fa54SDmitry Osipenko 1213c4019f9SSowjanya Komatineni /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 1223c4019f9SSowjanya Komatineni #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 1233c4019f9SSowjanya Komatineni 1245ec6fa5aSAniruddha Tvs Rao #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 1255ec6fa5aSAniruddha Tvs Rao SDHCI_TRNS_BLK_CNT_EN | \ 1265ec6fa5aSAniruddha Tvs Rao SDHCI_TRNS_DMA) 1275ec6fa5aSAniruddha Tvs Rao 1283e44a1a7SStephen Warren struct sdhci_tegra_soc_data { 1291db5eebfSLars-Peter Clausen const struct sdhci_pltfm_data *pdata; 130b960bc44SNicolin Chen u64 dma_mask; 1313e44a1a7SStephen Warren u32 nvquirks; 132ea8fc595SSowjanya Komatineni u8 min_tap_delay; 133ea8fc595SSowjanya Komatineni u8 max_tap_delay; 1343e44a1a7SStephen Warren }; 1353e44a1a7SStephen Warren 13651b77c8eSAapo Vienamo /* Magic pull up and pull down pad calibration offsets */ 13751b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets { 13851b77c8eSAapo Vienamo u32 pull_up_3v3; 13951b77c8eSAapo Vienamo u32 pull_down_3v3; 14051b77c8eSAapo Vienamo u32 pull_up_3v3_timeout; 14151b77c8eSAapo Vienamo u32 pull_down_3v3_timeout; 14251b77c8eSAapo Vienamo u32 pull_up_1v8; 14351b77c8eSAapo Vienamo u32 pull_down_1v8; 14451b77c8eSAapo Vienamo u32 pull_up_1v8_timeout; 14551b77c8eSAapo Vienamo u32 pull_down_1v8_timeout; 14651b77c8eSAapo Vienamo u32 pull_up_sdr104; 14751b77c8eSAapo Vienamo u32 pull_down_sdr104; 14851b77c8eSAapo Vienamo u32 pull_up_hs400; 14951b77c8eSAapo Vienamo u32 pull_down_hs400; 15051b77c8eSAapo Vienamo }; 15151b77c8eSAapo Vienamo 1523e44a1a7SStephen Warren struct sdhci_tegra { 1533e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 1542391b340SMylene JOSSERAND struct gpio_desc *power_gpio; 1558048822bSSowjanya Komatineni struct clk *tmclk; 156a8e326a9SLucas Stach bool ddr_signaling; 157e5c63d91SLucas Stach bool pad_calib_required; 15886ac2f8bSAapo Vienamo bool pad_control_available; 15920567be9SThierry Reding 16020567be9SThierry Reding struct reset_control *rst; 16186ac2f8bSAapo Vienamo struct pinctrl *pinctrl_sdmmc; 16286ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_3v3; 16386ac2f8bSAapo Vienamo struct pinctrl_state *pinctrl_state_1v8; 164de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_state_3v3_drv; 165de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_state_1v8_drv; 16651b77c8eSAapo Vienamo 16751b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets autocal_offsets; 16861dad40eSAapo Vienamo ktime_t last_calib; 16985c0da17SAapo Vienamo 17085c0da17SAapo Vienamo u32 default_tap; 17185c0da17SAapo Vienamo u32 default_trim; 172f5313aaaSAapo Vienamo u32 dqs_trim; 1733c4019f9SSowjanya Komatineni bool enable_hwcq; 174ea8fc595SSowjanya Komatineni unsigned long curr_clk_rate; 175ea8fc595SSowjanya Komatineni u8 tuned_tap_delay; 1763e44a1a7SStephen Warren }; 1773e44a1a7SStephen Warren 17803d2bfc8SOlof Johansson static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 17903d2bfc8SOlof Johansson { 1803e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1810734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1823e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1833e44a1a7SStephen Warren 1843e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 1853e44a1a7SStephen Warren (reg == SDHCI_HOST_VERSION))) { 18603d2bfc8SOlof Johansson /* Erratum: Version register is invalid in HW. */ 18703d2bfc8SOlof Johansson return SDHCI_SPEC_200; 18803d2bfc8SOlof Johansson } 18903d2bfc8SOlof Johansson 19003d2bfc8SOlof Johansson return readw(host->ioaddr + reg); 19103d2bfc8SOlof Johansson } 19203d2bfc8SOlof Johansson 193352ee868SPavan Kunapuli static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 194352ee868SPavan Kunapuli { 195352ee868SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 196352ee868SPavan Kunapuli 197352ee868SPavan Kunapuli switch (reg) { 198352ee868SPavan Kunapuli case SDHCI_TRANSFER_MODE: 199352ee868SPavan Kunapuli /* 200352ee868SPavan Kunapuli * Postpone this write, we must do it together with a 201352ee868SPavan Kunapuli * command write that is down below. 202352ee868SPavan Kunapuli */ 203352ee868SPavan Kunapuli pltfm_host->xfer_mode_shadow = val; 204352ee868SPavan Kunapuli return; 205352ee868SPavan Kunapuli case SDHCI_COMMAND: 206352ee868SPavan Kunapuli writel((val << 16) | pltfm_host->xfer_mode_shadow, 207352ee868SPavan Kunapuli host->ioaddr + SDHCI_TRANSFER_MODE); 208352ee868SPavan Kunapuli return; 209352ee868SPavan Kunapuli } 210352ee868SPavan Kunapuli 211352ee868SPavan Kunapuli writew(val, host->ioaddr + reg); 212352ee868SPavan Kunapuli } 213352ee868SPavan Kunapuli 21403d2bfc8SOlof Johansson static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 21503d2bfc8SOlof Johansson { 2163e44a1a7SStephen Warren struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2170734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 2183e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 2193e44a1a7SStephen Warren 22003d2bfc8SOlof Johansson /* Seems like we're getting spurious timeout and crc errors, so 22103d2bfc8SOlof Johansson * disable signalling of them. In case of real errors software 22203d2bfc8SOlof Johansson * timers should take care of eventually detecting them. 22303d2bfc8SOlof Johansson */ 22403d2bfc8SOlof Johansson if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 22503d2bfc8SOlof Johansson val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 22603d2bfc8SOlof Johansson 22703d2bfc8SOlof Johansson writel(val, host->ioaddr + reg); 22803d2bfc8SOlof Johansson 2293e44a1a7SStephen Warren if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 2303e44a1a7SStephen Warren (reg == SDHCI_INT_ENABLE))) { 23103d2bfc8SOlof Johansson /* Erratum: Must enable block gap interrupt detection */ 23203d2bfc8SOlof Johansson u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 23303d2bfc8SOlof Johansson if (val & SDHCI_INT_CARD_INT) 23403d2bfc8SOlof Johansson gap_ctrl |= 0x8; 23503d2bfc8SOlof Johansson else 23603d2bfc8SOlof Johansson gap_ctrl &= ~0x8; 23703d2bfc8SOlof Johansson writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 23803d2bfc8SOlof Johansson } 23903d2bfc8SOlof Johansson } 24003d2bfc8SOlof Johansson 24138a284d9SAapo Vienamo static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 24238a284d9SAapo Vienamo { 24338a284d9SAapo Vienamo bool status; 24438a284d9SAapo Vienamo u32 reg; 24538a284d9SAapo Vienamo 24638a284d9SAapo Vienamo reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 24738a284d9SAapo Vienamo status = !!(reg & SDHCI_CLOCK_CARD_EN); 24838a284d9SAapo Vienamo 24938a284d9SAapo Vienamo if (status == enable) 25038a284d9SAapo Vienamo return status; 25138a284d9SAapo Vienamo 25238a284d9SAapo Vienamo if (enable) 25338a284d9SAapo Vienamo reg |= SDHCI_CLOCK_CARD_EN; 25438a284d9SAapo Vienamo else 25538a284d9SAapo Vienamo reg &= ~SDHCI_CLOCK_CARD_EN; 25638a284d9SAapo Vienamo 25738a284d9SAapo Vienamo sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 25838a284d9SAapo Vienamo 25938a284d9SAapo Vienamo return status; 26038a284d9SAapo Vienamo } 26138a284d9SAapo Vienamo 26238a284d9SAapo Vienamo static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 26338a284d9SAapo Vienamo { 26438a284d9SAapo Vienamo bool is_tuning_cmd = 0; 26538a284d9SAapo Vienamo bool clk_enabled; 26638a284d9SAapo Vienamo u8 cmd; 26738a284d9SAapo Vienamo 26838a284d9SAapo Vienamo if (reg == SDHCI_COMMAND) { 26938a284d9SAapo Vienamo cmd = SDHCI_GET_CMD(val); 27038a284d9SAapo Vienamo is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 27138a284d9SAapo Vienamo cmd == MMC_SEND_TUNING_BLOCK_HS200; 27238a284d9SAapo Vienamo } 27338a284d9SAapo Vienamo 27438a284d9SAapo Vienamo if (is_tuning_cmd) 27538a284d9SAapo Vienamo clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 27638a284d9SAapo Vienamo 27738a284d9SAapo Vienamo writew(val, host->ioaddr + reg); 27838a284d9SAapo Vienamo 27938a284d9SAapo Vienamo if (is_tuning_cmd) { 28038a284d9SAapo Vienamo udelay(1); 281ea8fc595SSowjanya Komatineni sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 28238a284d9SAapo Vienamo tegra_sdhci_configure_card_clk(host, clk_enabled); 28338a284d9SAapo Vienamo } 28438a284d9SAapo Vienamo } 28538a284d9SAapo Vienamo 2860f686ca9SDmitry Osipenko static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 2870f686ca9SDmitry Osipenko { 2880f686ca9SDmitry Osipenko /* 2890f686ca9SDmitry Osipenko * Write-enable shall be assumed if GPIO is missing in a board's 2900f686ca9SDmitry Osipenko * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 2910f686ca9SDmitry Osipenko * Tegra. 2920f686ca9SDmitry Osipenko */ 2930f686ca9SDmitry Osipenko return mmc_gpio_get_ro(host->mmc); 2940f686ca9SDmitry Osipenko } 2950f686ca9SDmitry Osipenko 29686ac2f8bSAapo Vienamo static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 29786ac2f8bSAapo Vienamo { 29886ac2f8bSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 29986ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 30086ac2f8bSAapo Vienamo int has_1v8, has_3v3; 30186ac2f8bSAapo Vienamo 30286ac2f8bSAapo Vienamo /* 30386ac2f8bSAapo Vienamo * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 30486ac2f8bSAapo Vienamo * voltage configuration in order to perform voltage switching. This 30586ac2f8bSAapo Vienamo * means that valid pinctrl info is required on SDHCI instances capable 30686ac2f8bSAapo Vienamo * of performing voltage switching. Whether or not an SDHCI instance is 30786ac2f8bSAapo Vienamo * capable of voltage switching is determined based on the regulator. 30886ac2f8bSAapo Vienamo */ 30986ac2f8bSAapo Vienamo 31086ac2f8bSAapo Vienamo if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 31186ac2f8bSAapo Vienamo return true; 31286ac2f8bSAapo Vienamo 31386ac2f8bSAapo Vienamo if (IS_ERR(host->mmc->supply.vqmmc)) 31486ac2f8bSAapo Vienamo return false; 31586ac2f8bSAapo Vienamo 31686ac2f8bSAapo Vienamo has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 31786ac2f8bSAapo Vienamo 1700000, 1950000); 31886ac2f8bSAapo Vienamo 31986ac2f8bSAapo Vienamo has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 32086ac2f8bSAapo Vienamo 2700000, 3600000); 32186ac2f8bSAapo Vienamo 32286ac2f8bSAapo Vienamo if (has_1v8 == 1 && has_3v3 == 1) 32386ac2f8bSAapo Vienamo return tegra_host->pad_control_available; 32486ac2f8bSAapo Vienamo 32586ac2f8bSAapo Vienamo /* Fixed voltage, no pad control required. */ 32686ac2f8bSAapo Vienamo return true; 32786ac2f8bSAapo Vienamo } 32886ac2f8bSAapo Vienamo 329c2c09678SAapo Vienamo static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 330c2c09678SAapo Vienamo { 331c2c09678SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 332c2c09678SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 333c2c09678SAapo Vienamo const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 334c2c09678SAapo Vienamo bool card_clk_enabled = false; 335c2c09678SAapo Vienamo u32 reg; 336c2c09678SAapo Vienamo 337c2c09678SAapo Vienamo /* 338c2c09678SAapo Vienamo * Touching the tap values is a bit tricky on some SoC generations. 339c2c09678SAapo Vienamo * The quirk enables a workaround for a glitch that sometimes occurs if 340c2c09678SAapo Vienamo * the tap values are changed. 341c2c09678SAapo Vienamo */ 342c2c09678SAapo Vienamo 343c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 344c2c09678SAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 345c2c09678SAapo Vienamo 346c2c09678SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 347c2c09678SAapo Vienamo reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 348c2c09678SAapo Vienamo reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 349c2c09678SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 350c2c09678SAapo Vienamo 351c2c09678SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 352c2c09678SAapo Vienamo card_clk_enabled) { 353c2c09678SAapo Vienamo udelay(1); 354c2c09678SAapo Vienamo sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 355c2c09678SAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 356c2c09678SAapo Vienamo } 357c2c09678SAapo Vienamo } 358c2c09678SAapo Vienamo 35903231f9bSRussell King static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 360ca5879d3SPavan Kunapuli { 361ca5879d3SPavan Kunapuli struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3620734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 363ca5879d3SPavan Kunapuli const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 3649d548f11SAapo Vienamo u32 misc_ctrl, clk_ctrl, pad_ctrl; 365ca5879d3SPavan Kunapuli 36603231f9bSRussell King sdhci_reset(host, mask); 36703231f9bSRussell King 368ca5879d3SPavan Kunapuli if (!(mask & SDHCI_RESET_ALL)) 369ca5879d3SPavan Kunapuli return; 370ca5879d3SPavan Kunapuli 371c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 372c2c09678SAapo Vienamo 3731b84def8SLucas Stach misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 3744f6aa326SJon Hunter clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 3754f6aa326SJon Hunter 3764f6aa326SJon Hunter misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 3774f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR50 | 3784f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_DDR50 | 3794f6aa326SJon Hunter SDHCI_MISC_CTRL_ENABLE_SDR104); 3804f6aa326SJon Hunter 38141a0b8d7SAapo Vienamo clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 38241a0b8d7SAapo Vienamo SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 3834f6aa326SJon Hunter 38486ac2f8bSAapo Vienamo if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 385ca5879d3SPavan Kunapuli /* Erratum: Enable SDHCI spec v3.00 support */ 3863145351aSAndrew Bresticker if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 387ca5879d3SPavan Kunapuli misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 3887ad2ed1dSLucas Stach /* Advertise UHS modes as supported by host */ 3897ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 3907ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 3917ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 3927ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 3937ad2ed1dSLucas Stach if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 3947ad2ed1dSLucas Stach misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 395f571389cSMichał Mirosław if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 396c3c2384cSLucas Stach clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 3974f6aa326SJon Hunter } 3984f6aa326SJon Hunter 39941a0b8d7SAapo Vienamo clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 40041a0b8d7SAapo Vienamo 4014f6aa326SJon Hunter sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 40274cd42bcSLucas Stach sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 40374cd42bcSLucas Stach 4049d548f11SAapo Vienamo if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 4059d548f11SAapo Vienamo pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 4069d548f11SAapo Vienamo pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 4079d548f11SAapo Vienamo pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 4089d548f11SAapo Vienamo sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 4099d548f11SAapo Vienamo 410e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 4119d548f11SAapo Vienamo } 412e5c63d91SLucas Stach 413a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 414ca5879d3SPavan Kunapuli } 415ca5879d3SPavan Kunapuli 416212b0cf1SAapo Vienamo static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 417212b0cf1SAapo Vienamo { 418212b0cf1SAapo Vienamo u32 val; 419212b0cf1SAapo Vienamo 420212b0cf1SAapo Vienamo /* 421212b0cf1SAapo Vienamo * Enable or disable the additional I/O pad used by the drive strength 422212b0cf1SAapo Vienamo * calibration process. 423212b0cf1SAapo Vienamo */ 424212b0cf1SAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 425212b0cf1SAapo Vienamo 426212b0cf1SAapo Vienamo if (enable) 427212b0cf1SAapo Vienamo val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 428212b0cf1SAapo Vienamo else 429212b0cf1SAapo Vienamo val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 430212b0cf1SAapo Vienamo 431212b0cf1SAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 432212b0cf1SAapo Vienamo 433212b0cf1SAapo Vienamo if (enable) 434212b0cf1SAapo Vienamo usleep_range(1, 2); 435212b0cf1SAapo Vienamo } 436212b0cf1SAapo Vienamo 43751b77c8eSAapo Vienamo static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 43851b77c8eSAapo Vienamo u16 pdpu) 43951b77c8eSAapo Vienamo { 44051b77c8eSAapo Vienamo u32 reg; 44151b77c8eSAapo Vienamo 44251b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 44351b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 44451b77c8eSAapo Vienamo reg |= pdpu; 44551b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 44651b77c8eSAapo Vienamo } 44751b77c8eSAapo Vienamo 448de25fa5aSSowjanya Komatineni static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 449de25fa5aSSowjanya Komatineni bool state_drvupdn) 450de25fa5aSSowjanya Komatineni { 451de25fa5aSSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 452de25fa5aSSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 453de25fa5aSSowjanya Komatineni struct sdhci_tegra_autocal_offsets *offsets = 454de25fa5aSSowjanya Komatineni &tegra_host->autocal_offsets; 455de25fa5aSSowjanya Komatineni struct pinctrl_state *pinctrl_drvupdn = NULL; 456de25fa5aSSowjanya Komatineni int ret = 0; 457de25fa5aSSowjanya Komatineni u8 drvup = 0, drvdn = 0; 458de25fa5aSSowjanya Komatineni u32 reg; 459de25fa5aSSowjanya Komatineni 460de25fa5aSSowjanya Komatineni if (!state_drvupdn) { 461de25fa5aSSowjanya Komatineni /* PADS Drive Strength */ 462de25fa5aSSowjanya Komatineni if (voltage == MMC_SIGNAL_VOLTAGE_180) { 463de25fa5aSSowjanya Komatineni if (tegra_host->pinctrl_state_1v8_drv) { 464de25fa5aSSowjanya Komatineni pinctrl_drvupdn = 465de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv; 466de25fa5aSSowjanya Komatineni } else { 467de25fa5aSSowjanya Komatineni drvup = offsets->pull_up_1v8_timeout; 468de25fa5aSSowjanya Komatineni drvdn = offsets->pull_down_1v8_timeout; 469de25fa5aSSowjanya Komatineni } 470de25fa5aSSowjanya Komatineni } else { 471de25fa5aSSowjanya Komatineni if (tegra_host->pinctrl_state_3v3_drv) { 472de25fa5aSSowjanya Komatineni pinctrl_drvupdn = 473de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv; 474de25fa5aSSowjanya Komatineni } else { 475de25fa5aSSowjanya Komatineni drvup = offsets->pull_up_3v3_timeout; 476de25fa5aSSowjanya Komatineni drvdn = offsets->pull_down_3v3_timeout; 477de25fa5aSSowjanya Komatineni } 478de25fa5aSSowjanya Komatineni } 479de25fa5aSSowjanya Komatineni 480de25fa5aSSowjanya Komatineni if (pinctrl_drvupdn != NULL) { 481de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 482de25fa5aSSowjanya Komatineni pinctrl_drvupdn); 483de25fa5aSSowjanya Komatineni if (ret < 0) 484de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 485de25fa5aSSowjanya Komatineni "failed pads drvupdn, ret: %d\n", ret); 486de25fa5aSSowjanya Komatineni } else if ((drvup) || (drvdn)) { 487de25fa5aSSowjanya Komatineni reg = sdhci_readl(host, 488de25fa5aSSowjanya Komatineni SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 489de25fa5aSSowjanya Komatineni reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 490de25fa5aSSowjanya Komatineni reg |= (drvup << 20) | (drvdn << 12); 491de25fa5aSSowjanya Komatineni sdhci_writel(host, reg, 492de25fa5aSSowjanya Komatineni SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 493de25fa5aSSowjanya Komatineni } 494de25fa5aSSowjanya Komatineni 495de25fa5aSSowjanya Komatineni } else { 496de25fa5aSSowjanya Komatineni /* Dual Voltage PADS Voltage selection */ 497de25fa5aSSowjanya Komatineni if (!tegra_host->pad_control_available) 498de25fa5aSSowjanya Komatineni return 0; 499de25fa5aSSowjanya Komatineni 500de25fa5aSSowjanya Komatineni if (voltage == MMC_SIGNAL_VOLTAGE_180) { 501de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 502de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8); 503de25fa5aSSowjanya Komatineni if (ret < 0) 504de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 505de25fa5aSSowjanya Komatineni "setting 1.8V failed, ret: %d\n", ret); 506de25fa5aSSowjanya Komatineni } else { 507de25fa5aSSowjanya Komatineni ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 508de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3); 509de25fa5aSSowjanya Komatineni if (ret < 0) 510de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 511de25fa5aSSowjanya Komatineni "setting 3.3V failed, ret: %d\n", ret); 512de25fa5aSSowjanya Komatineni } 513de25fa5aSSowjanya Komatineni } 514de25fa5aSSowjanya Komatineni 515de25fa5aSSowjanya Komatineni return ret; 516de25fa5aSSowjanya Komatineni } 517de25fa5aSSowjanya Komatineni 518e5c63d91SLucas Stach static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 519e5c63d91SLucas Stach { 52051b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 52151b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 52251b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets offsets = 52351b77c8eSAapo Vienamo tegra_host->autocal_offsets; 52451b77c8eSAapo Vienamo struct mmc_ios *ios = &host->mmc->ios; 525887bda8fSAapo Vienamo bool card_clk_enabled; 52651b77c8eSAapo Vienamo u16 pdpu; 527e7c07148SAapo Vienamo u32 reg; 528e7c07148SAapo Vienamo int ret; 529e5c63d91SLucas Stach 53051b77c8eSAapo Vienamo switch (ios->timing) { 53151b77c8eSAapo Vienamo case MMC_TIMING_UHS_SDR104: 53251b77c8eSAapo Vienamo pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 53351b77c8eSAapo Vienamo break; 53451b77c8eSAapo Vienamo case MMC_TIMING_MMC_HS400: 53551b77c8eSAapo Vienamo pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 53651b77c8eSAapo Vienamo break; 53751b77c8eSAapo Vienamo default: 53851b77c8eSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 53951b77c8eSAapo Vienamo pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 54051b77c8eSAapo Vienamo else 54151b77c8eSAapo Vienamo pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 54251b77c8eSAapo Vienamo } 54351b77c8eSAapo Vienamo 544de25fa5aSSowjanya Komatineni /* Set initial offset before auto-calibration */ 54551b77c8eSAapo Vienamo tegra_sdhci_set_pad_autocal_offset(host, pdpu); 54651b77c8eSAapo Vienamo 547887bda8fSAapo Vienamo card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 548887bda8fSAapo Vienamo 549212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, true); 550212b0cf1SAapo Vienamo 551e7c07148SAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 552e7c07148SAapo Vienamo reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 553e7c07148SAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 554e5c63d91SLucas Stach 555e7c07148SAapo Vienamo usleep_range(1, 2); 556e7c07148SAapo Vienamo /* 10 ms timeout */ 557e7c07148SAapo Vienamo ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 558e7c07148SAapo Vienamo reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 559e7c07148SAapo Vienamo 1000, 10000); 560e7c07148SAapo Vienamo 561212b0cf1SAapo Vienamo tegra_sdhci_configure_cal_pad(host, false); 562212b0cf1SAapo Vienamo 563887bda8fSAapo Vienamo tegra_sdhci_configure_card_clk(host, card_clk_enabled); 564887bda8fSAapo Vienamo 56551b77c8eSAapo Vienamo if (ret) { 566e7c07148SAapo Vienamo dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 56751b77c8eSAapo Vienamo 568de25fa5aSSowjanya Komatineni /* Disable automatic cal and use fixed Drive Strengths */ 56951b77c8eSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 57051b77c8eSAapo Vienamo reg &= ~SDHCI_AUTO_CAL_ENABLE; 57151b77c8eSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 57251b77c8eSAapo Vienamo 573de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 574de25fa5aSSowjanya Komatineni if (ret < 0) 575de25fa5aSSowjanya Komatineni dev_err(mmc_dev(host->mmc), 576de25fa5aSSowjanya Komatineni "Setting drive strengths failed: %d\n", ret); 57751b77c8eSAapo Vienamo } 57851b77c8eSAapo Vienamo } 57951b77c8eSAapo Vienamo 58051b77c8eSAapo Vienamo static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 58151b77c8eSAapo Vienamo { 58251b77c8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58351b77c8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 58451b77c8eSAapo Vienamo struct sdhci_tegra_autocal_offsets *autocal = 58551b77c8eSAapo Vienamo &tegra_host->autocal_offsets; 58651b77c8eSAapo Vienamo int err; 58751b77c8eSAapo Vienamo 588bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 58951b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3", 59051b77c8eSAapo Vienamo &autocal->pull_up_3v3); 59151b77c8eSAapo Vienamo if (err) 59251b77c8eSAapo Vienamo autocal->pull_up_3v3 = 0; 59351b77c8eSAapo Vienamo 594bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 59551b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3", 59651b77c8eSAapo Vienamo &autocal->pull_down_3v3); 59751b77c8eSAapo Vienamo if (err) 59851b77c8eSAapo Vienamo autocal->pull_down_3v3 = 0; 59951b77c8eSAapo Vienamo 600bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 60151b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8", 60251b77c8eSAapo Vienamo &autocal->pull_up_1v8); 60351b77c8eSAapo Vienamo if (err) 60451b77c8eSAapo Vienamo autocal->pull_up_1v8 = 0; 60551b77c8eSAapo Vienamo 606bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 60751b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8", 60851b77c8eSAapo Vienamo &autocal->pull_down_1v8); 60951b77c8eSAapo Vienamo if (err) 61051b77c8eSAapo Vienamo autocal->pull_down_1v8 = 0; 61151b77c8eSAapo Vienamo 612bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 613aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-up-offset-sdr104", 614aebbf577SSowjanya Komatineni &autocal->pull_up_sdr104); 615aebbf577SSowjanya Komatineni if (err) 616aebbf577SSowjanya Komatineni autocal->pull_up_sdr104 = autocal->pull_up_1v8; 617aebbf577SSowjanya Komatineni 618bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 619aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-down-offset-sdr104", 620aebbf577SSowjanya Komatineni &autocal->pull_down_sdr104); 621aebbf577SSowjanya Komatineni if (err) 622aebbf577SSowjanya Komatineni autocal->pull_down_sdr104 = autocal->pull_down_1v8; 623aebbf577SSowjanya Komatineni 624bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 625aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-up-offset-hs400", 626aebbf577SSowjanya Komatineni &autocal->pull_up_hs400); 627aebbf577SSowjanya Komatineni if (err) 628aebbf577SSowjanya Komatineni autocal->pull_up_hs400 = autocal->pull_up_1v8; 629aebbf577SSowjanya Komatineni 630bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 631aebbf577SSowjanya Komatineni "nvidia,pad-autocal-pull-down-offset-hs400", 632aebbf577SSowjanya Komatineni &autocal->pull_down_hs400); 633aebbf577SSowjanya Komatineni if (err) 634aebbf577SSowjanya Komatineni autocal->pull_down_hs400 = autocal->pull_down_1v8; 635aebbf577SSowjanya Komatineni 636aebbf577SSowjanya Komatineni /* 637aebbf577SSowjanya Komatineni * Different fail-safe drive strength values based on the signaling 638aebbf577SSowjanya Komatineni * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. 639aebbf577SSowjanya Komatineni * So, avoid reading below device tree properties for SoCs that don't 640aebbf577SSowjanya Komatineni * have NVQUIRK_NEEDS_PAD_CONTROL. 641aebbf577SSowjanya Komatineni */ 642aebbf577SSowjanya Komatineni if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 643aebbf577SSowjanya Komatineni return; 644aebbf577SSowjanya Komatineni 645bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 64651b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 6475ccf7f55SSowjanya Komatineni &autocal->pull_up_3v3_timeout); 648de25fa5aSSowjanya Komatineni if (err) { 649de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 650de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_3v3_drv == NULL)) 651de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 652de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 65351b77c8eSAapo Vienamo autocal->pull_up_3v3_timeout = 0; 654de25fa5aSSowjanya Komatineni } 65551b77c8eSAapo Vienamo 656bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 65751b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 6585ccf7f55SSowjanya Komatineni &autocal->pull_down_3v3_timeout); 659de25fa5aSSowjanya Komatineni if (err) { 660de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 661de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_3v3_drv == NULL)) 662de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 663de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 66451b77c8eSAapo Vienamo autocal->pull_down_3v3_timeout = 0; 665de25fa5aSSowjanya Komatineni } 66651b77c8eSAapo Vienamo 667bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 66851b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 6695ccf7f55SSowjanya Komatineni &autocal->pull_up_1v8_timeout); 670de25fa5aSSowjanya Komatineni if (err) { 671de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 672de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_1v8_drv == NULL)) 673de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 674de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 67551b77c8eSAapo Vienamo autocal->pull_up_1v8_timeout = 0; 676de25fa5aSSowjanya Komatineni } 67751b77c8eSAapo Vienamo 678bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), 67951b77c8eSAapo Vienamo "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 6805ccf7f55SSowjanya Komatineni &autocal->pull_down_1v8_timeout); 681de25fa5aSSowjanya Komatineni if (err) { 682de25fa5aSSowjanya Komatineni if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 683de25fa5aSSowjanya Komatineni (tegra_host->pinctrl_state_1v8_drv == NULL)) 684de25fa5aSSowjanya Komatineni pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 685de25fa5aSSowjanya Komatineni mmc_hostname(host->mmc)); 68651b77c8eSAapo Vienamo autocal->pull_down_1v8_timeout = 0; 687de25fa5aSSowjanya Komatineni } 688e5c63d91SLucas Stach } 689e5c63d91SLucas Stach 69061dad40eSAapo Vienamo static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 69161dad40eSAapo Vienamo { 69261dad40eSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 69361dad40eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69461dad40eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 69561dad40eSAapo Vienamo ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 69661dad40eSAapo Vienamo 69761dad40eSAapo Vienamo /* 100 ms calibration interval is specified in the TRM */ 69861dad40eSAapo Vienamo if (ktime_to_ms(since_calib) > 100) { 69961dad40eSAapo Vienamo tegra_sdhci_pad_autocalib(host); 70061dad40eSAapo Vienamo tegra_host->last_calib = ktime_get(); 70161dad40eSAapo Vienamo } 70261dad40eSAapo Vienamo 70361dad40eSAapo Vienamo sdhci_request(mmc, mrq); 70461dad40eSAapo Vienamo } 70561dad40eSAapo Vienamo 706f5313aaaSAapo Vienamo static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 70785c0da17SAapo Vienamo { 70885c0da17SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 70985c0da17SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 71085c0da17SAapo Vienamo int err; 71185c0da17SAapo Vienamo 712bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", 71385c0da17SAapo Vienamo &tegra_host->default_tap); 71485c0da17SAapo Vienamo if (err) 71585c0da17SAapo Vienamo tegra_host->default_tap = 0; 71685c0da17SAapo Vienamo 717bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", 71885c0da17SAapo Vienamo &tegra_host->default_trim); 71985c0da17SAapo Vienamo if (err) 72085c0da17SAapo Vienamo tegra_host->default_trim = 0; 721f5313aaaSAapo Vienamo 722bac53336SJisheng Zhang err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", 723f5313aaaSAapo Vienamo &tegra_host->dqs_trim); 724f5313aaaSAapo Vienamo if (err) 725f5313aaaSAapo Vienamo tegra_host->dqs_trim = 0x11; 72685c0da17SAapo Vienamo } 72785c0da17SAapo Vienamo 7283c4019f9SSowjanya Komatineni static void tegra_sdhci_parse_dt(struct sdhci_host *host) 7293c4019f9SSowjanya Komatineni { 7303c4019f9SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7313c4019f9SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 7323c4019f9SSowjanya Komatineni 733bac53336SJisheng Zhang if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) 7343c4019f9SSowjanya Komatineni tegra_host->enable_hwcq = true; 7353c4019f9SSowjanya Komatineni else 7363c4019f9SSowjanya Komatineni tegra_host->enable_hwcq = false; 7373c4019f9SSowjanya Komatineni 7383c4019f9SSowjanya Komatineni tegra_sdhci_parse_pad_autocal_dt(host); 7393c4019f9SSowjanya Komatineni tegra_sdhci_parse_tap_and_trim(host); 7403c4019f9SSowjanya Komatineni } 7413c4019f9SSowjanya Komatineni 742a8e326a9SLucas Stach static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 743a8e326a9SLucas Stach { 744a8e326a9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 7450734e79cSJisheng Zhang struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 746a8e326a9SLucas Stach unsigned long host_clk; 747a8e326a9SLucas Stach 748a8e326a9SLucas Stach if (!clock) 7493491b690SLucas Stach return sdhci_set_clock(host, clock); 750a8e326a9SLucas Stach 75157d1654eSAapo Vienamo /* 75257d1654eSAapo Vienamo * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 75357d1654eSAapo Vienamo * divider to be configured to divided the host clock by two. The SDHCI 75457d1654eSAapo Vienamo * clock divider is calculated as part of sdhci_set_clock() by 75557d1654eSAapo Vienamo * sdhci_calc_clk(). The divider is calculated from host->max_clk and 75657d1654eSAapo Vienamo * the requested clock rate. 75757d1654eSAapo Vienamo * 75857d1654eSAapo Vienamo * By setting the host->max_clk to clock * 2 the divider calculation 75957d1654eSAapo Vienamo * will always result in the correct value for DDR50/52 modes, 76057d1654eSAapo Vienamo * regardless of clock rate rounding, which may happen if the value 76157d1654eSAapo Vienamo * from clk_get_rate() is used. 76257d1654eSAapo Vienamo */ 763a8e326a9SLucas Stach host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 764a8e326a9SLucas Stach clk_set_rate(pltfm_host->clk, host_clk); 765ea8fc595SSowjanya Komatineni tegra_host->curr_clk_rate = host_clk; 76657d1654eSAapo Vienamo if (tegra_host->ddr_signaling) 76757d1654eSAapo Vienamo host->max_clk = host_clk; 76857d1654eSAapo Vienamo else 769a8e326a9SLucas Stach host->max_clk = clk_get_rate(pltfm_host->clk); 770a8e326a9SLucas Stach 771e5c63d91SLucas Stach sdhci_set_clock(host, clock); 772e5c63d91SLucas Stach 773e5c63d91SLucas Stach if (tegra_host->pad_calib_required) { 774e5c63d91SLucas Stach tegra_sdhci_pad_autocalib(host); 775e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 776e5c63d91SLucas Stach } 777a8e326a9SLucas Stach } 778a8e326a9SLucas Stach 779*4fc7261dSPrathamesh Shete static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 780*4fc7261dSPrathamesh Shete struct mmc_ios *ios) 781*4fc7261dSPrathamesh Shete { 782*4fc7261dSPrathamesh Shete struct sdhci_host *host = mmc_priv(mmc); 783*4fc7261dSPrathamesh Shete u32 val; 784*4fc7261dSPrathamesh Shete 785*4fc7261dSPrathamesh Shete val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 786*4fc7261dSPrathamesh Shete 787*4fc7261dSPrathamesh Shete if (ios->enhanced_strobe) { 788*4fc7261dSPrathamesh Shete val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 789*4fc7261dSPrathamesh Shete /* 790*4fc7261dSPrathamesh Shete * When CMD13 is sent from mmc_select_hs400es() after 791*4fc7261dSPrathamesh Shete * switching to HS400ES mode, the bus is operating at 792*4fc7261dSPrathamesh Shete * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. 793*4fc7261dSPrathamesh Shete * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI 794*4fc7261dSPrathamesh Shete * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host 795*4fc7261dSPrathamesh Shete * controller CAR clock and the interface clock are rate matched. 796*4fc7261dSPrathamesh Shete */ 797*4fc7261dSPrathamesh Shete tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); 798*4fc7261dSPrathamesh Shete } else { 799*4fc7261dSPrathamesh Shete val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 800*4fc7261dSPrathamesh Shete } 801*4fc7261dSPrathamesh Shete 802*4fc7261dSPrathamesh Shete sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 803*4fc7261dSPrathamesh Shete } 804*4fc7261dSPrathamesh Shete 80544350993SAapo Vienamo static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 80644350993SAapo Vienamo { 80744350993SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 80844350993SAapo Vienamo 80944350993SAapo Vienamo return clk_round_rate(pltfm_host->clk, UINT_MAX); 81044350993SAapo Vienamo } 81144350993SAapo Vienamo 812f5313aaaSAapo Vienamo static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 813f5313aaaSAapo Vienamo { 814f5313aaaSAapo Vienamo u32 val; 815f5313aaaSAapo Vienamo 816f5313aaaSAapo Vienamo val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 817f5313aaaSAapo Vienamo val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 818f5313aaaSAapo Vienamo val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 819f5313aaaSAapo Vienamo sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 820f5313aaaSAapo Vienamo } 821f5313aaaSAapo Vienamo 822bc5568bfSAapo Vienamo static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 823bc5568bfSAapo Vienamo { 824bc5568bfSAapo Vienamo u32 reg; 825bc5568bfSAapo Vienamo int err; 826bc5568bfSAapo Vienamo 827bc5568bfSAapo Vienamo reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 828bc5568bfSAapo Vienamo reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 829bc5568bfSAapo Vienamo sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 830bc5568bfSAapo Vienamo 831bc5568bfSAapo Vienamo /* 1 ms sleep, 5 ms timeout */ 832bc5568bfSAapo Vienamo err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 833bc5568bfSAapo Vienamo reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 834bc5568bfSAapo Vienamo 1000, 5000); 835bc5568bfSAapo Vienamo if (err) 836bc5568bfSAapo Vienamo dev_err(mmc_dev(host->mmc), 837bc5568bfSAapo Vienamo "HS400 delay line calibration timed out\n"); 838bc5568bfSAapo Vienamo } 839bc5568bfSAapo Vienamo 840ea8fc595SSowjanya Komatineni static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 841ea8fc595SSowjanya Komatineni u8 thd_low, u8 fixed_tap) 842ea8fc595SSowjanya Komatineni { 843ea8fc595SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 844ea8fc595SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 845ea8fc595SSowjanya Komatineni u32 val, tun_status; 846ea8fc595SSowjanya Komatineni u8 word, bit, edge1, tap, window; 847ea8fc595SSowjanya Komatineni bool tap_result; 848ea8fc595SSowjanya Komatineni bool start_fail = false; 849ea8fc595SSowjanya Komatineni bool start_pass = false; 850ea8fc595SSowjanya Komatineni bool end_pass = false; 851ea8fc595SSowjanya Komatineni bool first_fail = false; 852ea8fc595SSowjanya Komatineni bool first_pass = false; 853ea8fc595SSowjanya Komatineni u8 start_pass_tap = 0; 854ea8fc595SSowjanya Komatineni u8 end_pass_tap = 0; 855ea8fc595SSowjanya Komatineni u8 first_fail_tap = 0; 856ea8fc595SSowjanya Komatineni u8 first_pass_tap = 0; 857ea8fc595SSowjanya Komatineni u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 858ea8fc595SSowjanya Komatineni 859ea8fc595SSowjanya Komatineni /* 860ea8fc595SSowjanya Komatineni * Read auto-tuned results and extract good valid passing window by 861ea8fc595SSowjanya Komatineni * filtering out un-wanted bubble/partial/merged windows. 862ea8fc595SSowjanya Komatineni */ 863ea8fc595SSowjanya Komatineni for (word = 0; word < total_tuning_words; word++) { 864ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 865ea8fc595SSowjanya Komatineni val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 866ea8fc595SSowjanya Komatineni val |= word; 867ea8fc595SSowjanya Komatineni sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 868ea8fc595SSowjanya Komatineni tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 869ea8fc595SSowjanya Komatineni bit = 0; 870ea8fc595SSowjanya Komatineni while (bit < TUNING_WORD_BIT_SIZE) { 871ea8fc595SSowjanya Komatineni tap = word * TUNING_WORD_BIT_SIZE + bit; 872ea8fc595SSowjanya Komatineni tap_result = tun_status & (1 << bit); 873ea8fc595SSowjanya Komatineni if (!tap_result && !start_fail) { 874ea8fc595SSowjanya Komatineni start_fail = true; 875ea8fc595SSowjanya Komatineni if (!first_fail) { 876ea8fc595SSowjanya Komatineni first_fail_tap = tap; 877ea8fc595SSowjanya Komatineni first_fail = true; 878ea8fc595SSowjanya Komatineni } 879ea8fc595SSowjanya Komatineni 880ea8fc595SSowjanya Komatineni } else if (tap_result && start_fail && !start_pass) { 881ea8fc595SSowjanya Komatineni start_pass_tap = tap; 882ea8fc595SSowjanya Komatineni start_pass = true; 883ea8fc595SSowjanya Komatineni if (!first_pass) { 884ea8fc595SSowjanya Komatineni first_pass_tap = tap; 885ea8fc595SSowjanya Komatineni first_pass = true; 886ea8fc595SSowjanya Komatineni } 887ea8fc595SSowjanya Komatineni 888ea8fc595SSowjanya Komatineni } else if (!tap_result && start_fail && start_pass && 889ea8fc595SSowjanya Komatineni !end_pass) { 890ea8fc595SSowjanya Komatineni end_pass_tap = tap - 1; 891ea8fc595SSowjanya Komatineni end_pass = true; 892ea8fc595SSowjanya Komatineni } else if (tap_result && start_pass && start_fail && 893ea8fc595SSowjanya Komatineni end_pass) { 894ea8fc595SSowjanya Komatineni window = end_pass_tap - start_pass_tap; 895ea8fc595SSowjanya Komatineni /* discard merged window and bubble window */ 896ea8fc595SSowjanya Komatineni if (window >= thd_up || window < thd_low) { 897ea8fc595SSowjanya Komatineni start_pass_tap = tap; 898ea8fc595SSowjanya Komatineni end_pass = false; 899ea8fc595SSowjanya Komatineni } else { 900ea8fc595SSowjanya Komatineni /* set tap at middle of valid window */ 901ea8fc595SSowjanya Komatineni tap = start_pass_tap + window / 2; 902ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = tap; 903ea8fc595SSowjanya Komatineni return; 904ea8fc595SSowjanya Komatineni } 905ea8fc595SSowjanya Komatineni } 906ea8fc595SSowjanya Komatineni 907ea8fc595SSowjanya Komatineni bit++; 908ea8fc595SSowjanya Komatineni } 909ea8fc595SSowjanya Komatineni } 910ea8fc595SSowjanya Komatineni 911ea8fc595SSowjanya Komatineni if (!first_fail) { 912d96dc68eSDan Carpenter WARN(1, "no edge detected, continue with hw tuned delay.\n"); 913ea8fc595SSowjanya Komatineni } else if (first_pass) { 914ea8fc595SSowjanya Komatineni /* set tap location at fixed tap relative to the first edge */ 915ea8fc595SSowjanya Komatineni edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 916ea8fc595SSowjanya Komatineni if (edge1 - 1 > fixed_tap) 917ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = edge1 - fixed_tap; 918ea8fc595SSowjanya Komatineni else 919ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = edge1 + fixed_tap; 920ea8fc595SSowjanya Komatineni } 921ea8fc595SSowjanya Komatineni } 922ea8fc595SSowjanya Komatineni 923ea8fc595SSowjanya Komatineni static void tegra_sdhci_post_tuning(struct sdhci_host *host) 924ea8fc595SSowjanya Komatineni { 925ea8fc595SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 926ea8fc595SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 927ea8fc595SSowjanya Komatineni const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 928ea8fc595SSowjanya Komatineni u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 929ea8fc595SSowjanya Komatineni u8 fixed_tap, start_tap, end_tap, window_width; 930ea8fc595SSowjanya Komatineni u8 thdupper, thdlower; 931ea8fc595SSowjanya Komatineni u8 num_iter; 932ea8fc595SSowjanya Komatineni u32 clk_rate_mhz, period_ps, bestcase, worstcase; 933ea8fc595SSowjanya Komatineni 934ea8fc595SSowjanya Komatineni /* retain HW tuned tap to use incase if no correction is needed */ 935ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 936ea8fc595SSowjanya Komatineni tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 937ea8fc595SSowjanya Komatineni SDHCI_CLOCK_CTRL_TAP_SHIFT; 938ea8fc595SSowjanya Komatineni if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 939ea8fc595SSowjanya Komatineni min_tap_dly = soc_data->min_tap_delay; 940ea8fc595SSowjanya Komatineni max_tap_dly = soc_data->max_tap_delay; 941ea8fc595SSowjanya Komatineni clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 942ea8fc595SSowjanya Komatineni period_ps = USEC_PER_SEC / clk_rate_mhz; 943ea8fc595SSowjanya Komatineni bestcase = period_ps / min_tap_dly; 944ea8fc595SSowjanya Komatineni worstcase = period_ps / max_tap_dly; 945ea8fc595SSowjanya Komatineni /* 946ea8fc595SSowjanya Komatineni * Upper and Lower bound thresholds used to detect merged and 947ea8fc595SSowjanya Komatineni * bubble windows 948ea8fc595SSowjanya Komatineni */ 949ea8fc595SSowjanya Komatineni thdupper = (2 * worstcase + bestcase) / 2; 950ea8fc595SSowjanya Komatineni thdlower = worstcase / 4; 951ea8fc595SSowjanya Komatineni /* 952ea8fc595SSowjanya Komatineni * fixed tap is used when HW tuning result contains single edge 953ea8fc595SSowjanya Komatineni * and tap is set at fixed tap delay relative to the first edge 954ea8fc595SSowjanya Komatineni */ 955ea8fc595SSowjanya Komatineni avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 956ea8fc595SSowjanya Komatineni fixed_tap = avg_tap_dly / 2; 957ea8fc595SSowjanya Komatineni 958ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 959ea8fc595SSowjanya Komatineni start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 960ea8fc595SSowjanya Komatineni end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 961ea8fc595SSowjanya Komatineni SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 962ea8fc595SSowjanya Komatineni window_width = end_tap - start_tap; 963ea8fc595SSowjanya Komatineni num_iter = host->tuning_loop_count; 964ea8fc595SSowjanya Komatineni /* 965ea8fc595SSowjanya Komatineni * partial window includes edges of the tuning range. 966ea8fc595SSowjanya Komatineni * merged window includes more taps so window width is higher 967ea8fc595SSowjanya Komatineni * than upper threshold. 968ea8fc595SSowjanya Komatineni */ 969ea8fc595SSowjanya Komatineni if (start_tap == 0 || (end_tap == (num_iter - 1)) || 970ea8fc595SSowjanya Komatineni (end_tap == num_iter - 2) || window_width >= thdupper) { 971ea8fc595SSowjanya Komatineni pr_debug("%s: Apply tuning correction\n", 972ea8fc595SSowjanya Komatineni mmc_hostname(host->mmc)); 973ea8fc595SSowjanya Komatineni tegra_sdhci_tap_correction(host, thdupper, thdlower, 974ea8fc595SSowjanya Komatineni fixed_tap); 975ea8fc595SSowjanya Komatineni } 976ea8fc595SSowjanya Komatineni } 977ea8fc595SSowjanya Komatineni 978ea8fc595SSowjanya Komatineni tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 979ea8fc595SSowjanya Komatineni } 980ea8fc595SSowjanya Komatineni 981ea8fc595SSowjanya Komatineni static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 982ea8fc595SSowjanya Komatineni { 983ea8fc595SSowjanya Komatineni struct sdhci_host *host = mmc_priv(mmc); 984ea8fc595SSowjanya Komatineni int err; 985ea8fc595SSowjanya Komatineni 986ea8fc595SSowjanya Komatineni err = sdhci_execute_tuning(mmc, opcode); 987ea8fc595SSowjanya Komatineni if (!err && !host->tuning_err) 988ea8fc595SSowjanya Komatineni tegra_sdhci_post_tuning(host); 989ea8fc595SSowjanya Komatineni 990ea8fc595SSowjanya Komatineni return err; 991ea8fc595SSowjanya Komatineni } 992ea8fc595SSowjanya Komatineni 993c2c09678SAapo Vienamo static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 994c2c09678SAapo Vienamo unsigned timing) 995c3c2384cSLucas Stach { 996d4501d8eSAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 997d4501d8eSAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 998c2c09678SAapo Vienamo bool set_default_tap = false; 999f5313aaaSAapo Vienamo bool set_dqs_trim = false; 1000bc5568bfSAapo Vienamo bool do_hs400_dll_cal = false; 1001ea8fc595SSowjanya Komatineni u8 iter = TRIES_256; 1002ea8fc595SSowjanya Komatineni u32 val; 1003c3c2384cSLucas Stach 100492cd1667SSowjanya Komatineni tegra_host->ddr_signaling = false; 1005c2c09678SAapo Vienamo switch (timing) { 1006c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR50: 1007ea8fc595SSowjanya Komatineni break; 1008c2c09678SAapo Vienamo case MMC_TIMING_UHS_SDR104: 1009c2c09678SAapo Vienamo case MMC_TIMING_MMC_HS200: 1010c2c09678SAapo Vienamo /* Don't set default tap on tunable modes. */ 1011ea8fc595SSowjanya Komatineni iter = TRIES_128; 1012c2c09678SAapo Vienamo break; 1013f5313aaaSAapo Vienamo case MMC_TIMING_MMC_HS400: 1014f5313aaaSAapo Vienamo set_dqs_trim = true; 1015bc5568bfSAapo Vienamo do_hs400_dll_cal = true; 1016ea8fc595SSowjanya Komatineni iter = TRIES_128; 1017f5313aaaSAapo Vienamo break; 1018c2c09678SAapo Vienamo case MMC_TIMING_MMC_DDR52: 1019c2c09678SAapo Vienamo case MMC_TIMING_UHS_DDR50: 1020c2c09678SAapo Vienamo tegra_host->ddr_signaling = true; 1021c2c09678SAapo Vienamo set_default_tap = true; 1022c2c09678SAapo Vienamo break; 1023c2c09678SAapo Vienamo default: 1024c2c09678SAapo Vienamo set_default_tap = true; 1025c2c09678SAapo Vienamo break; 1026d4501d8eSAapo Vienamo } 1027c2c09678SAapo Vienamo 1028ea8fc595SSowjanya Komatineni val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 1029ea8fc595SSowjanya Komatineni val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 1030ea8fc595SSowjanya Komatineni SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 1031ea8fc595SSowjanya Komatineni SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 1032ea8fc595SSowjanya Komatineni val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 1033ea8fc595SSowjanya Komatineni 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 1034ea8fc595SSowjanya Komatineni 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 1035ea8fc595SSowjanya Komatineni sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 1036ea8fc595SSowjanya Komatineni sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 1037ea8fc595SSowjanya Komatineni 1038ea8fc595SSowjanya Komatineni host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 1039ea8fc595SSowjanya Komatineni 1040c2c09678SAapo Vienamo sdhci_set_uhs_signaling(host, timing); 1041c2c09678SAapo Vienamo 1042c2c09678SAapo Vienamo tegra_sdhci_pad_autocalib(host); 1043c2c09678SAapo Vienamo 1044ea8fc595SSowjanya Komatineni if (tegra_host->tuned_tap_delay && !set_default_tap) 1045ea8fc595SSowjanya Komatineni tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1046ea8fc595SSowjanya Komatineni else 1047c2c09678SAapo Vienamo tegra_sdhci_set_tap(host, tegra_host->default_tap); 1048f5313aaaSAapo Vienamo 1049f5313aaaSAapo Vienamo if (set_dqs_trim) 1050f5313aaaSAapo Vienamo tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1051bc5568bfSAapo Vienamo 1052bc5568bfSAapo Vienamo if (do_hs400_dll_cal) 1053bc5568bfSAapo Vienamo tegra_sdhci_hs400_dll_cal(host); 1054c3c2384cSLucas Stach } 1055c3c2384cSLucas Stach 1056c3c2384cSLucas Stach static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1057c3c2384cSLucas Stach { 1058c3c2384cSLucas Stach unsigned int min, max; 1059c3c2384cSLucas Stach 1060c3c2384cSLucas Stach /* 1061c3c2384cSLucas Stach * Start search for minimum tap value at 10, as smaller values are 1062c3c2384cSLucas Stach * may wrongly be reported as working but fail at higher speeds, 1063c3c2384cSLucas Stach * according to the TRM. 1064c3c2384cSLucas Stach */ 1065c3c2384cSLucas Stach min = 10; 1066c3c2384cSLucas Stach while (min < 255) { 1067c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min); 1068c3c2384cSLucas Stach if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1069c3c2384cSLucas Stach break; 1070c3c2384cSLucas Stach min++; 1071c3c2384cSLucas Stach } 1072c3c2384cSLucas Stach 1073c3c2384cSLucas Stach /* Find the maximum tap value that still passes. */ 1074c3c2384cSLucas Stach max = min + 1; 1075c3c2384cSLucas Stach while (max < 255) { 1076c3c2384cSLucas Stach tegra_sdhci_set_tap(host, max); 1077c3c2384cSLucas Stach if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1078c3c2384cSLucas Stach max--; 1079c3c2384cSLucas Stach break; 1080c3c2384cSLucas Stach } 1081c3c2384cSLucas Stach max++; 1082c3c2384cSLucas Stach } 1083c3c2384cSLucas Stach 1084c3c2384cSLucas Stach /* The TRM states the ideal tap value is at 75% in the passing range. */ 1085c3c2384cSLucas Stach tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1086c3c2384cSLucas Stach 1087c3c2384cSLucas Stach return mmc_send_tuning(host->mmc, opcode, NULL); 1088c3c2384cSLucas Stach } 1089c3c2384cSLucas Stach 109086ac2f8bSAapo Vienamo static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 109186ac2f8bSAapo Vienamo struct mmc_ios *ios) 109286ac2f8bSAapo Vienamo { 109386ac2f8bSAapo Vienamo struct sdhci_host *host = mmc_priv(mmc); 109444babea2SAapo Vienamo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109544babea2SAapo Vienamo struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 109686ac2f8bSAapo Vienamo int ret = 0; 109786ac2f8bSAapo Vienamo 109886ac2f8bSAapo Vienamo if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1099de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 110086ac2f8bSAapo Vienamo if (ret < 0) 110186ac2f8bSAapo Vienamo return ret; 110286ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 110386ac2f8bSAapo Vienamo } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 110486ac2f8bSAapo Vienamo ret = sdhci_start_signal_voltage_switch(mmc, ios); 110586ac2f8bSAapo Vienamo if (ret < 0) 110686ac2f8bSAapo Vienamo return ret; 1107de25fa5aSSowjanya Komatineni ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 110886ac2f8bSAapo Vienamo } 110986ac2f8bSAapo Vienamo 111044babea2SAapo Vienamo if (tegra_host->pad_calib_required) 111144babea2SAapo Vienamo tegra_sdhci_pad_autocalib(host); 111244babea2SAapo Vienamo 111386ac2f8bSAapo Vienamo return ret; 111486ac2f8bSAapo Vienamo } 111586ac2f8bSAapo Vienamo 111686ac2f8bSAapo Vienamo static int tegra_sdhci_init_pinctrl_info(struct device *dev, 111786ac2f8bSAapo Vienamo struct sdhci_tegra *tegra_host) 111886ac2f8bSAapo Vienamo { 111986ac2f8bSAapo Vienamo tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 112086ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 112186ac2f8bSAapo Vienamo dev_dbg(dev, "No pinctrl info, err: %ld\n", 112286ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_sdmmc)); 112386ac2f8bSAapo Vienamo return -1; 112486ac2f8bSAapo Vienamo } 112586ac2f8bSAapo Vienamo 1126de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1127de25fa5aSSowjanya Komatineni tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1128de25fa5aSSowjanya Komatineni if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1129de25fa5aSSowjanya Komatineni if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1130de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_1v8_drv = NULL; 1131de25fa5aSSowjanya Komatineni } 1132de25fa5aSSowjanya Komatineni 1133de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1134de25fa5aSSowjanya Komatineni tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1135de25fa5aSSowjanya Komatineni if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1136de25fa5aSSowjanya Komatineni if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1137de25fa5aSSowjanya Komatineni tegra_host->pinctrl_state_3v3_drv = NULL; 1138de25fa5aSSowjanya Komatineni } 1139de25fa5aSSowjanya Komatineni 114086ac2f8bSAapo Vienamo tegra_host->pinctrl_state_3v3 = 114186ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 114286ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 114386ac2f8bSAapo Vienamo dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 114486ac2f8bSAapo Vienamo PTR_ERR(tegra_host->pinctrl_state_3v3)); 114586ac2f8bSAapo Vienamo return -1; 114686ac2f8bSAapo Vienamo } 114786ac2f8bSAapo Vienamo 114886ac2f8bSAapo Vienamo tegra_host->pinctrl_state_1v8 = 114986ac2f8bSAapo Vienamo pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 115086ac2f8bSAapo Vienamo if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 115186ac2f8bSAapo Vienamo dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1152e5378247SYueHaibing PTR_ERR(tegra_host->pinctrl_state_1v8)); 115386ac2f8bSAapo Vienamo return -1; 115486ac2f8bSAapo Vienamo } 115586ac2f8bSAapo Vienamo 115686ac2f8bSAapo Vienamo tegra_host->pad_control_available = true; 115786ac2f8bSAapo Vienamo 115886ac2f8bSAapo Vienamo return 0; 115986ac2f8bSAapo Vienamo } 116086ac2f8bSAapo Vienamo 1161e5c63d91SLucas Stach static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1162e5c63d91SLucas Stach { 1163e5c63d91SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1164e5c63d91SLucas Stach struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1165e5c63d91SLucas Stach const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1166e5c63d91SLucas Stach 1167e5c63d91SLucas Stach if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1168e5c63d91SLucas Stach tegra_host->pad_calib_required = true; 1169e5c63d91SLucas Stach } 1170e5c63d91SLucas Stach 1171b7754428SSowjanya Komatineni static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1172b7754428SSowjanya Komatineni { 1173b7754428SSowjanya Komatineni struct mmc_host *mmc = cq_host->mmc; 11745ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 1175b7754428SSowjanya Komatineni u8 ctrl; 1176b7754428SSowjanya Komatineni ktime_t timeout; 1177b7754428SSowjanya Komatineni bool timed_out; 1178b7754428SSowjanya Komatineni 1179b7754428SSowjanya Komatineni /* 1180b7754428SSowjanya Komatineni * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1181b7754428SSowjanya Komatineni * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1182b7754428SSowjanya Komatineni * to be re-configured. 1183b7754428SSowjanya Komatineni * Tegra CQHCI/SDHCI prevents write access to block size register when 1184b7754428SSowjanya Komatineni * CQE is unhalted. So handling CQE resume sequence here to configure 1185b7754428SSowjanya Komatineni * SDHCI block registers prior to exiting CQE halt state. 1186b7754428SSowjanya Komatineni */ 1187b7754428SSowjanya Komatineni if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1188b7754428SSowjanya Komatineni cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 11895ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1190b7754428SSowjanya Komatineni sdhci_cqe_enable(mmc); 1191b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1192b7754428SSowjanya Komatineni timeout = ktime_add_us(ktime_get(), 50); 1193b7754428SSowjanya Komatineni while (1) { 1194b7754428SSowjanya Komatineni timed_out = ktime_compare(ktime_get(), timeout) > 0; 1195b7754428SSowjanya Komatineni ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1196b7754428SSowjanya Komatineni if (!(ctrl & CQHCI_HALT) || timed_out) 1197b7754428SSowjanya Komatineni break; 1198b7754428SSowjanya Komatineni } 1199b7754428SSowjanya Komatineni /* 1200b7754428SSowjanya Komatineni * CQE usually resumes very quick, but incase if Tegra CQE 1201b7754428SSowjanya Komatineni * doesn't resume retry unhalt. 1202b7754428SSowjanya Komatineni */ 1203b7754428SSowjanya Komatineni if (timed_out) 1204b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1205b7754428SSowjanya Komatineni } else { 1206b7754428SSowjanya Komatineni writel(val, cq_host->mmio + reg); 1207b7754428SSowjanya Komatineni } 1208b7754428SSowjanya Komatineni } 1209b7754428SSowjanya Komatineni 1210c6e7ab90SSowjanya Komatineni static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1211c6e7ab90SSowjanya Komatineni struct mmc_request *mrq, u64 *data) 1212c6e7ab90SSowjanya Komatineni { 1213c6e7ab90SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1214c6e7ab90SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1215c6e7ab90SSowjanya Komatineni const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1216c6e7ab90SSowjanya Komatineni 1217c6e7ab90SSowjanya Komatineni if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1218c6e7ab90SSowjanya Komatineni mrq->cmd->flags & MMC_RSP_R1B) 1219c6e7ab90SSowjanya Komatineni *data |= CQHCI_CMD_TIMING(1); 1220c6e7ab90SSowjanya Komatineni } 1221c6e7ab90SSowjanya Komatineni 12223c4019f9SSowjanya Komatineni static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 12233c4019f9SSowjanya Komatineni { 12243c4019f9SSowjanya Komatineni struct cqhci_host *cq_host = mmc->cqe_private; 12255ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 1226b7754428SSowjanya Komatineni u32 val; 12273c4019f9SSowjanya Komatineni 12283c4019f9SSowjanya Komatineni /* 1229b7754428SSowjanya Komatineni * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1230b7754428SSowjanya Komatineni * register when CQE is enabled and unhalted. 1231b7754428SSowjanya Komatineni * CQHCI driver enables CQE prior to activation, so disable CQE before 1232b7754428SSowjanya Komatineni * programming block size in sdhci controller and enable it back. 12333c4019f9SSowjanya Komatineni */ 1234b7754428SSowjanya Komatineni if (!cq_host->activated) { 1235b7754428SSowjanya Komatineni val = cqhci_readl(cq_host, CQHCI_CFG); 1236b7754428SSowjanya Komatineni if (val & CQHCI_ENABLE) 1237b7754428SSowjanya Komatineni cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1238b7754428SSowjanya Komatineni CQHCI_CFG); 12395ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 12403c4019f9SSowjanya Komatineni sdhci_cqe_enable(mmc); 1241b7754428SSowjanya Komatineni if (val & CQHCI_ENABLE) 1242b7754428SSowjanya Komatineni cqhci_writel(cq_host, val, CQHCI_CFG); 1243b7754428SSowjanya Komatineni } 12443c4019f9SSowjanya Komatineni 1245b7754428SSowjanya Komatineni /* 1246b7754428SSowjanya Komatineni * CMD CRC errors are seen sometimes with some eMMC devices when status 1247b7754428SSowjanya Komatineni * command is sent during transfer of last data block which is the 1248b7754428SSowjanya Komatineni * default case as send status command block counter (CBC) is 1. 1249b7754428SSowjanya Komatineni * Recommended fix to set CBC to 0 allowing send status command only 1250b7754428SSowjanya Komatineni * when data lines are idle. 1251b7754428SSowjanya Komatineni */ 1252b7754428SSowjanya Komatineni val = cqhci_readl(cq_host, CQHCI_SSC1); 1253b7754428SSowjanya Komatineni val &= ~CQHCI_SSC1_CBC_MASK; 1254b7754428SSowjanya Komatineni cqhci_writel(cq_host, val, CQHCI_SSC1); 12553c4019f9SSowjanya Komatineni } 12563c4019f9SSowjanya Komatineni 12573c4019f9SSowjanya Komatineni static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 12583c4019f9SSowjanya Komatineni { 12593c4019f9SSowjanya Komatineni sdhci_dumpregs(mmc_priv(mmc)); 12603c4019f9SSowjanya Komatineni } 12613c4019f9SSowjanya Komatineni 12623c4019f9SSowjanya Komatineni static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 12633c4019f9SSowjanya Komatineni { 12643c4019f9SSowjanya Komatineni int cmd_error = 0; 12653c4019f9SSowjanya Komatineni int data_error = 0; 12663c4019f9SSowjanya Komatineni 12673c4019f9SSowjanya Komatineni if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 12683c4019f9SSowjanya Komatineni return intmask; 12693c4019f9SSowjanya Komatineni 12703c4019f9SSowjanya Komatineni cqhci_irq(host->mmc, intmask, cmd_error, data_error); 12713c4019f9SSowjanya Komatineni 12723c4019f9SSowjanya Komatineni return 0; 12733c4019f9SSowjanya Komatineni } 12743c4019f9SSowjanya Komatineni 12755e958e4aSSowjanya Komatineni static void tegra_sdhci_set_timeout(struct sdhci_host *host, 12765e958e4aSSowjanya Komatineni struct mmc_command *cmd) 12775e958e4aSSowjanya Komatineni { 12785e958e4aSSowjanya Komatineni u32 val; 12795e958e4aSSowjanya Komatineni 12805e958e4aSSowjanya Komatineni /* 12815e958e4aSSowjanya Komatineni * HW busy detection timeout is based on programmed data timeout 12825e958e4aSSowjanya Komatineni * counter and maximum supported timeout is 11s which may not be 12835e958e4aSSowjanya Komatineni * enough for long operations like cache flush, sleep awake, erase. 12845e958e4aSSowjanya Komatineni * 12855e958e4aSSowjanya Komatineni * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 12865e958e4aSSowjanya Komatineni * host controller to wait for busy state until the card is busy 12875e958e4aSSowjanya Komatineni * without HW timeout. 12885e958e4aSSowjanya Komatineni * 12895e958e4aSSowjanya Komatineni * So, use infinite busy wait mode for operations that may take 12905e958e4aSSowjanya Komatineni * more than maximum HW busy timeout of 11s otherwise use finite 12915e958e4aSSowjanya Komatineni * busy wait mode. 12925e958e4aSSowjanya Komatineni */ 12935e958e4aSSowjanya Komatineni val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1294fcc541feSWolfram Sang if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) 12955e958e4aSSowjanya Komatineni val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 12965e958e4aSSowjanya Komatineni else 12975e958e4aSSowjanya Komatineni val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 12985e958e4aSSowjanya Komatineni sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 12995e958e4aSSowjanya Komatineni 13005e958e4aSSowjanya Komatineni __sdhci_set_timeout(host, cmd); 13015e958e4aSSowjanya Komatineni } 13025e958e4aSSowjanya Komatineni 13035ec6fa5aSAniruddha Tvs Rao static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc) 13045ec6fa5aSAniruddha Tvs Rao { 13055ec6fa5aSAniruddha Tvs Rao struct cqhci_host *cq_host = mmc->cqe_private; 13065ec6fa5aSAniruddha Tvs Rao u32 reg; 13075ec6fa5aSAniruddha Tvs Rao 13085ec6fa5aSAniruddha Tvs Rao reg = cqhci_readl(cq_host, CQHCI_CFG); 13095ec6fa5aSAniruddha Tvs Rao reg |= CQHCI_ENABLE; 13105ec6fa5aSAniruddha Tvs Rao cqhci_writel(cq_host, reg, CQHCI_CFG); 13115ec6fa5aSAniruddha Tvs Rao } 13125ec6fa5aSAniruddha Tvs Rao 13135ec6fa5aSAniruddha Tvs Rao static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc) 13145ec6fa5aSAniruddha Tvs Rao { 13155ec6fa5aSAniruddha Tvs Rao struct cqhci_host *cq_host = mmc->cqe_private; 13165ec6fa5aSAniruddha Tvs Rao struct sdhci_host *host = mmc_priv(mmc); 13175ec6fa5aSAniruddha Tvs Rao u32 reg; 13185ec6fa5aSAniruddha Tvs Rao 13195ec6fa5aSAniruddha Tvs Rao reg = cqhci_readl(cq_host, CQHCI_CFG); 13205ec6fa5aSAniruddha Tvs Rao reg &= ~CQHCI_ENABLE; 13215ec6fa5aSAniruddha Tvs Rao cqhci_writel(cq_host, reg, CQHCI_CFG); 13225ec6fa5aSAniruddha Tvs Rao sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 13235ec6fa5aSAniruddha Tvs Rao } 13245ec6fa5aSAniruddha Tvs Rao 13253c4019f9SSowjanya Komatineni static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1326b7754428SSowjanya Komatineni .write_l = tegra_cqhci_writel, 13273c4019f9SSowjanya Komatineni .enable = sdhci_tegra_cqe_enable, 13283c4019f9SSowjanya Komatineni .disable = sdhci_cqe_disable, 13293c4019f9SSowjanya Komatineni .dumpregs = sdhci_tegra_dumpregs, 1330c6e7ab90SSowjanya Komatineni .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 13315ec6fa5aSAniruddha Tvs Rao .pre_enable = sdhci_tegra_cqe_pre_enable, 13325ec6fa5aSAniruddha Tvs Rao .post_disable = sdhci_tegra_cqe_post_disable, 13333c4019f9SSowjanya Komatineni }; 13343c4019f9SSowjanya Komatineni 1335b960bc44SNicolin Chen static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1336b960bc44SNicolin Chen { 1337b960bc44SNicolin Chen struct sdhci_pltfm_host *platform = sdhci_priv(host); 1338b960bc44SNicolin Chen struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1339b960bc44SNicolin Chen const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1340b960bc44SNicolin Chen struct device *dev = mmc_dev(host->mmc); 1341b960bc44SNicolin Chen 1342b960bc44SNicolin Chen if (soc->dma_mask) 1343b960bc44SNicolin Chen return dma_set_mask_and_coherent(dev, soc->dma_mask); 1344b960bc44SNicolin Chen 1345b960bc44SNicolin Chen return 0; 1346b960bc44SNicolin Chen } 1347b960bc44SNicolin Chen 1348c915568dSLars-Peter Clausen static const struct sdhci_ops tegra_sdhci_ops = { 13490f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 135085d6509dSShawn Guo .read_w = tegra_sdhci_readw, 135185d6509dSShawn Guo .write_l = tegra_sdhci_writel, 1352a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 1353b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 135414b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 135503231f9bSRussell King .reset = tegra_sdhci_reset, 1356c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 1357a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1358e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 135944350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 136085d6509dSShawn Guo }; 136103d2bfc8SOlof Johansson 13621db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 136385d6509dSShawn Guo .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 136485d6509dSShawn Guo SDHCI_QUIRK_SINGLE_POWER_WRITE | 136585d6509dSShawn Guo SDHCI_QUIRK_NO_HISPD_BIT | 1366f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1367f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 136885d6509dSShawn Guo .ops = &tegra_sdhci_ops, 136985d6509dSShawn Guo }; 137085d6509dSShawn Guo 1371d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 13723e44a1a7SStephen Warren .pdata = &sdhci_tegra20_pdata, 1373b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 13743e44a1a7SStephen Warren .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 13751743fa54SDmitry Osipenko NVQUIRK_HAS_ANDROID_GPT_SECTOR | 13763e44a1a7SStephen Warren NVQUIRK_ENABLE_BLOCK_GAP_DET, 13773e44a1a7SStephen Warren }; 13783e44a1a7SStephen Warren 13791db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 13803e44a1a7SStephen Warren .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 13813e44a1a7SStephen Warren SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 13823e44a1a7SStephen Warren SDHCI_QUIRK_SINGLE_POWER_WRITE | 13833e44a1a7SStephen Warren SDHCI_QUIRK_NO_HISPD_BIT | 1384f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1385f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1386127407e3SStefan Agner .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1387726df1d5SStefan Agner SDHCI_QUIRK2_BROKEN_HS200 | 1388726df1d5SStefan Agner /* 1389726df1d5SStefan Agner * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1390726df1d5SStefan Agner * though no command operation was in progress." 1391726df1d5SStefan Agner * 1392726df1d5SStefan Agner * The exact reason is unknown, as the same hardware seems 1393726df1d5SStefan Agner * to support Auto CMD23 on a downstream 3.1 kernel. 1394726df1d5SStefan Agner */ 1395726df1d5SStefan Agner SDHCI_QUIRK2_ACMD23_BROKEN, 13963e44a1a7SStephen Warren .ops = &tegra_sdhci_ops, 13973e44a1a7SStephen Warren }; 13983e44a1a7SStephen Warren 1399d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 14003e44a1a7SStephen Warren .pdata = &sdhci_tegra30_pdata, 1401b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 14023145351aSAndrew Bresticker .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 14037ad2ed1dSLucas Stach NVQUIRK_ENABLE_SDR50 | 1404e5c63d91SLucas Stach NVQUIRK_ENABLE_SDR104 | 14051743fa54SDmitry Osipenko NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1406e5c63d91SLucas Stach NVQUIRK_HAS_PADCALIB, 14073e44a1a7SStephen Warren }; 14083e44a1a7SStephen Warren 140901df7ecdSRhyland Klein static const struct sdhci_ops tegra114_sdhci_ops = { 14100f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 141101df7ecdSRhyland Klein .read_w = tegra_sdhci_readw, 141201df7ecdSRhyland Klein .write_w = tegra_sdhci_writew, 141301df7ecdSRhyland Klein .write_l = tegra_sdhci_writel, 1414a8e326a9SLucas Stach .set_clock = tegra_sdhci_set_clock, 1415b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 141614b04c6aSMichał Mirosław .set_bus_width = sdhci_set_bus_width, 141701df7ecdSRhyland Klein .reset = tegra_sdhci_reset, 1418c3c2384cSLucas Stach .platform_execute_tuning = tegra_sdhci_execute_tuning, 1419a8e326a9SLucas Stach .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1420e5c63d91SLucas Stach .voltage_switch = tegra_sdhci_voltage_switch, 142144350993SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 142201df7ecdSRhyland Klein }; 142301df7ecdSRhyland Klein 14241db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 14255ebf2552SRhyland Klein .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 14265ebf2552SRhyland Klein SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 14275ebf2552SRhyland Klein SDHCI_QUIRK_SINGLE_POWER_WRITE | 14285ebf2552SRhyland Klein SDHCI_QUIRK_NO_HISPD_BIT | 1429f9260355SAndrew Bresticker SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1430f9260355SAndrew Bresticker SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1431a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 143201df7ecdSRhyland Klein .ops = &tegra114_sdhci_ops, 14335ebf2552SRhyland Klein }; 14345ebf2552SRhyland Klein 1435d49d19c2SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 14365ebf2552SRhyland Klein .pdata = &sdhci_tegra114_pdata, 1437b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(32), 14381743fa54SDmitry Osipenko .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 14397bf037d6SJon Hunter }; 14407bf037d6SJon Hunter 14414ae12588SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 14424ae12588SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 14434ae12588SThierry Reding SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 14444ae12588SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 14454ae12588SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 14464ae12588SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 14474ae12588SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1448b960bc44SNicolin Chen .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 14494ae12588SThierry Reding .ops = &tegra114_sdhci_ops, 14504ae12588SThierry Reding }; 14514ae12588SThierry Reding 14524ae12588SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 14534ae12588SThierry Reding .pdata = &sdhci_tegra124_pdata, 1454b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(34), 14551743fa54SDmitry Osipenko .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 14564ae12588SThierry Reding }; 14574ae12588SThierry Reding 14581070e83aSAapo Vienamo static const struct sdhci_ops tegra210_sdhci_ops = { 14590f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 14601070e83aSAapo Vienamo .read_w = tegra_sdhci_readw, 146138a284d9SAapo Vienamo .write_w = tegra210_sdhci_writew, 14621070e83aSAapo Vienamo .write_l = tegra_sdhci_writel, 14631070e83aSAapo Vienamo .set_clock = tegra_sdhci_set_clock, 1464b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 14651070e83aSAapo Vienamo .set_bus_width = sdhci_set_bus_width, 14661070e83aSAapo Vienamo .reset = tegra_sdhci_reset, 14671070e83aSAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 14681070e83aSAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 14691070e83aSAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 14705e958e4aSSowjanya Komatineni .set_timeout = tegra_sdhci_set_timeout, 14711070e83aSAapo Vienamo }; 14721070e83aSAapo Vienamo 1473b5a84ecfSThierry Reding static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1474b5a84ecfSThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1475b5a84ecfSThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 1476b5a84ecfSThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 1477a8e326a9SLucas Stach SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1478a8e326a9SLucas Stach SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1479a8e326a9SLucas Stach .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 14801070e83aSAapo Vienamo .ops = &tegra210_sdhci_ops, 1481b5a84ecfSThierry Reding }; 1482b5a84ecfSThierry Reding 1483b5a84ecfSThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1484b5a84ecfSThierry Reding .pdata = &sdhci_tegra210_pdata, 1485b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(34), 1486d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1487d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 14883559d4a6SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 14893559d4a6SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 14908048822bSSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 14918048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK, 1492ea8fc595SSowjanya Komatineni .min_tap_delay = 106, 1493ea8fc595SSowjanya Komatineni .max_tap_delay = 185, 1494b5a84ecfSThierry Reding }; 1495b5a84ecfSThierry Reding 149638a284d9SAapo Vienamo static const struct sdhci_ops tegra186_sdhci_ops = { 14970f686ca9SDmitry Osipenko .get_ro = tegra_sdhci_get_ro, 149838a284d9SAapo Vienamo .read_w = tegra_sdhci_readw, 149938a284d9SAapo Vienamo .write_l = tegra_sdhci_writel, 150038a284d9SAapo Vienamo .set_clock = tegra_sdhci_set_clock, 1501b960bc44SNicolin Chen .set_dma_mask = tegra_sdhci_set_dma_mask, 150238a284d9SAapo Vienamo .set_bus_width = sdhci_set_bus_width, 150338a284d9SAapo Vienamo .reset = tegra_sdhci_reset, 150438a284d9SAapo Vienamo .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 150538a284d9SAapo Vienamo .voltage_switch = tegra_sdhci_voltage_switch, 150638a284d9SAapo Vienamo .get_max_clock = tegra_sdhci_get_max_clock, 15073c4019f9SSowjanya Komatineni .irq = sdhci_tegra_cqhci_irq, 15085e958e4aSSowjanya Komatineni .set_timeout = tegra_sdhci_set_timeout, 150938a284d9SAapo Vienamo }; 151038a284d9SAapo Vienamo 15114346b7c7SThierry Reding static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 15124346b7c7SThierry Reding .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 15134346b7c7SThierry Reding SDHCI_QUIRK_SINGLE_POWER_WRITE | 15144346b7c7SThierry Reding SDHCI_QUIRK_NO_HISPD_BIT | 15154346b7c7SThierry Reding SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 15164346b7c7SThierry Reding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1517b960bc44SNicolin Chen .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 151838a284d9SAapo Vienamo .ops = &tegra186_sdhci_ops, 15194346b7c7SThierry Reding }; 15204346b7c7SThierry Reding 15214346b7c7SThierry Reding static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 15224346b7c7SThierry Reding .pdata = &sdhci_tegra186_pdata, 1523b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(40), 1524d943f6e9SAapo Vienamo .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1525d4501d8eSAapo Vienamo NVQUIRK_HAS_PADCALIB | 15262ad50051SAapo Vienamo NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 15272ad50051SAapo Vienamo NVQUIRK_ENABLE_SDR50 | 1528c6e7ab90SSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 15298048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK | 1530c6e7ab90SSowjanya Komatineni NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1531ea8fc595SSowjanya Komatineni .min_tap_delay = 84, 1532ea8fc595SSowjanya Komatineni .max_tap_delay = 136, 1533ea8fc595SSowjanya Komatineni }; 1534ea8fc595SSowjanya Komatineni 1535ea8fc595SSowjanya Komatineni static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1536ea8fc595SSowjanya Komatineni .pdata = &sdhci_tegra186_pdata, 1537b960bc44SNicolin Chen .dma_mask = DMA_BIT_MASK(39), 1538ea8fc595SSowjanya Komatineni .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1539ea8fc595SSowjanya Komatineni NVQUIRK_HAS_PADCALIB | 1540ea8fc595SSowjanya Komatineni NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1541ea8fc595SSowjanya Komatineni NVQUIRK_ENABLE_SDR50 | 15428048822bSSowjanya Komatineni NVQUIRK_ENABLE_SDR104 | 15438048822bSSowjanya Komatineni NVQUIRK_HAS_TMCLK, 1544ea8fc595SSowjanya Komatineni .min_tap_delay = 96, 1545ea8fc595SSowjanya Komatineni .max_tap_delay = 139, 15464346b7c7SThierry Reding }; 15474346b7c7SThierry Reding 1548498d83e7SBill Pemberton static const struct of_device_id sdhci_tegra_dt_match[] = { 1549ea8fc595SSowjanya Komatineni { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 15504346b7c7SThierry Reding { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1551b5a84ecfSThierry Reding { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 15524ae12588SThierry Reding { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 15535ebf2552SRhyland Klein { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 15543e44a1a7SStephen Warren { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 15553e44a1a7SStephen Warren { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1556275173b2SGrant Likely {} 1557275173b2SGrant Likely }; 1558e4404fabSArnd Bergmann MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1559275173b2SGrant Likely 15603c4019f9SSowjanya Komatineni static int sdhci_tegra_add_host(struct sdhci_host *host) 15613c4019f9SSowjanya Komatineni { 15623c4019f9SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 15633c4019f9SSowjanya Komatineni struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 15643c4019f9SSowjanya Komatineni struct cqhci_host *cq_host; 15653c4019f9SSowjanya Komatineni bool dma64; 15663c4019f9SSowjanya Komatineni int ret; 15673c4019f9SSowjanya Komatineni 15683c4019f9SSowjanya Komatineni if (!tegra_host->enable_hwcq) 15693c4019f9SSowjanya Komatineni return sdhci_add_host(host); 15703c4019f9SSowjanya Komatineni 15713c4019f9SSowjanya Komatineni sdhci_enable_v4_mode(host); 15723c4019f9SSowjanya Komatineni 15733c4019f9SSowjanya Komatineni ret = sdhci_setup_host(host); 15743c4019f9SSowjanya Komatineni if (ret) 15753c4019f9SSowjanya Komatineni return ret; 15763c4019f9SSowjanya Komatineni 15773c4019f9SSowjanya Komatineni host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 15783c4019f9SSowjanya Komatineni 1579bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), 15803c4019f9SSowjanya Komatineni sizeof(*cq_host), GFP_KERNEL); 15813c4019f9SSowjanya Komatineni if (!cq_host) { 15823c4019f9SSowjanya Komatineni ret = -ENOMEM; 15833c4019f9SSowjanya Komatineni goto cleanup; 15843c4019f9SSowjanya Komatineni } 15853c4019f9SSowjanya Komatineni 15863c4019f9SSowjanya Komatineni cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 15873c4019f9SSowjanya Komatineni cq_host->ops = &sdhci_tegra_cqhci_ops; 15883c4019f9SSowjanya Komatineni 15893c4019f9SSowjanya Komatineni dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 15903c4019f9SSowjanya Komatineni if (dma64) 15913c4019f9SSowjanya Komatineni cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 15923c4019f9SSowjanya Komatineni 15933c4019f9SSowjanya Komatineni ret = cqhci_init(cq_host, host->mmc, dma64); 15943c4019f9SSowjanya Komatineni if (ret) 15953c4019f9SSowjanya Komatineni goto cleanup; 15963c4019f9SSowjanya Komatineni 15973c4019f9SSowjanya Komatineni ret = __sdhci_add_host(host); 15983c4019f9SSowjanya Komatineni if (ret) 15993c4019f9SSowjanya Komatineni goto cleanup; 16003c4019f9SSowjanya Komatineni 16013c4019f9SSowjanya Komatineni return 0; 16023c4019f9SSowjanya Komatineni 16033c4019f9SSowjanya Komatineni cleanup: 16043c4019f9SSowjanya Komatineni sdhci_cleanup_host(host); 16053c4019f9SSowjanya Komatineni return ret; 16063c4019f9SSowjanya Komatineni } 16073c4019f9SSowjanya Komatineni 1608c3be1efdSBill Pemberton static int sdhci_tegra_probe(struct platform_device *pdev) 160903d2bfc8SOlof Johansson { 16103e44a1a7SStephen Warren const struct of_device_id *match; 16113e44a1a7SStephen Warren const struct sdhci_tegra_soc_data *soc_data; 16123e44a1a7SStephen Warren struct sdhci_host *host; 161385d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 16143e44a1a7SStephen Warren struct sdhci_tegra *tegra_host; 161503d2bfc8SOlof Johansson struct clk *clk; 161603d2bfc8SOlof Johansson int rc; 161703d2bfc8SOlof Johansson 16183e44a1a7SStephen Warren match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1619b37f9d98SJoseph Lo if (!match) 1620b37f9d98SJoseph Lo return -EINVAL; 16213e44a1a7SStephen Warren soc_data = match->data; 16223e44a1a7SStephen Warren 16230734e79cSJisheng Zhang host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 162485d6509dSShawn Guo if (IS_ERR(host)) 162585d6509dSShawn Guo return PTR_ERR(host); 162685d6509dSShawn Guo pltfm_host = sdhci_priv(host); 162785d6509dSShawn Guo 16280734e79cSJisheng Zhang tegra_host = sdhci_pltfm_priv(pltfm_host); 1629a8e326a9SLucas Stach tegra_host->ddr_signaling = false; 1630e5c63d91SLucas Stach tegra_host->pad_calib_required = false; 163186ac2f8bSAapo Vienamo tegra_host->pad_control_available = false; 16323e44a1a7SStephen Warren tegra_host->soc_data = soc_data; 1633275173b2SGrant Likely 16341743fa54SDmitry Osipenko if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) 16351743fa54SDmitry Osipenko host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; 16361743fa54SDmitry Osipenko 163786ac2f8bSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 163886ac2f8bSAapo Vienamo rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 163986ac2f8bSAapo Vienamo if (rc == 0) 164086ac2f8bSAapo Vienamo host->mmc_host_ops.start_signal_voltage_switch = 164186ac2f8bSAapo Vienamo sdhci_tegra_start_signal_voltage_switch; 164286ac2f8bSAapo Vienamo } 164386ac2f8bSAapo Vienamo 164461dad40eSAapo Vienamo /* Hook to periodically rerun pad calibration */ 164561dad40eSAapo Vienamo if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 164661dad40eSAapo Vienamo host->mmc_host_ops.request = tegra_sdhci_request; 164761dad40eSAapo Vienamo 1648dfc9700cSAapo Vienamo host->mmc_host_ops.hs400_enhanced_strobe = 1649dfc9700cSAapo Vienamo tegra_sdhci_hs400_enhanced_strobe; 1650dfc9700cSAapo Vienamo 1651ea8fc595SSowjanya Komatineni if (!host->ops->platform_execute_tuning) 1652ea8fc595SSowjanya Komatineni host->mmc_host_ops.execute_tuning = 1653ea8fc595SSowjanya Komatineni tegra_sdhci_execute_hw_tuning; 1654ea8fc595SSowjanya Komatineni 16552391b340SMylene JOSSERAND rc = mmc_of_parse(host->mmc); 165647caa84fSSimon Baatz if (rc) 165747caa84fSSimon Baatz goto err_parse_dt; 16580e786102SStephen Warren 16597ad2ed1dSLucas Stach if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1660c3c2384cSLucas Stach host->mmc->caps |= MMC_CAP_1_8V_DDR; 1661c3c2384cSLucas Stach 1662ff124c31SSowjanya Komatineni /* HW busy detection is supported, but R1B responses are required. */ 1663ff124c31SSowjanya Komatineni host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1664d2f8bfa4SUlf Hansson 16653c4019f9SSowjanya Komatineni tegra_sdhci_parse_dt(host); 166685c0da17SAapo Vienamo 16672391b340SMylene JOSSERAND tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 16682391b340SMylene JOSSERAND GPIOD_OUT_HIGH); 16692391b340SMylene JOSSERAND if (IS_ERR(tegra_host->power_gpio)) { 16702391b340SMylene JOSSERAND rc = PTR_ERR(tegra_host->power_gpio); 167185d6509dSShawn Guo goto err_power_req; 167203d2bfc8SOlof Johansson } 167303d2bfc8SOlof Johansson 16748048822bSSowjanya Komatineni /* 16758048822bSSowjanya Komatineni * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host 16768048822bSSowjanya Komatineni * timeout clock and SW can choose TMCLK or SDCLK for hardware 16778048822bSSowjanya Komatineni * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of 16788048822bSSowjanya Komatineni * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL. 16798048822bSSowjanya Komatineni * 16808048822bSSowjanya Komatineni * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses 16818048822bSSowjanya Komatineni * 12Mhz TMCLK which is advertised in host capability register. 16828048822bSSowjanya Komatineni * With TMCLK of 12Mhz provides maximum data timeout period that can 16838048822bSSowjanya Komatineni * be achieved is 11s better than using SDCLK for data timeout. 16848048822bSSowjanya Komatineni * 16858048822bSSowjanya Komatineni * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's 16868048822bSSowjanya Komatineni * supporting separate TMCLK. 16878048822bSSowjanya Komatineni */ 16888048822bSSowjanya Komatineni 16898048822bSSowjanya Komatineni if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { 16908048822bSSowjanya Komatineni clk = devm_clk_get(&pdev->dev, "tmclk"); 16918048822bSSowjanya Komatineni if (IS_ERR(clk)) { 16928048822bSSowjanya Komatineni rc = PTR_ERR(clk); 16938048822bSSowjanya Komatineni if (rc == -EPROBE_DEFER) 16948048822bSSowjanya Komatineni goto err_power_req; 16958048822bSSowjanya Komatineni 16968048822bSSowjanya Komatineni dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 16978048822bSSowjanya Komatineni clk = NULL; 16988048822bSSowjanya Komatineni } 16998048822bSSowjanya Komatineni 17008048822bSSowjanya Komatineni clk_set_rate(clk, 12000000); 17018048822bSSowjanya Komatineni rc = clk_prepare_enable(clk); 17028048822bSSowjanya Komatineni if (rc) { 17038048822bSSowjanya Komatineni dev_err(&pdev->dev, 17048048822bSSowjanya Komatineni "failed to enable tmclk: %d\n", rc); 17058048822bSSowjanya Komatineni goto err_power_req; 17068048822bSSowjanya Komatineni } 17078048822bSSowjanya Komatineni 17088048822bSSowjanya Komatineni tegra_host->tmclk = clk; 17098048822bSSowjanya Komatineni } 17108048822bSSowjanya Komatineni 1711e4f79d9cSKevin Hao clk = devm_clk_get(mmc_dev(host->mmc), NULL); 171203d2bfc8SOlof Johansson if (IS_ERR(clk)) { 1713180a4665SKrzysztof Kozlowski rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), 1714180a4665SKrzysztof Kozlowski "failed to get clock\n"); 171585d6509dSShawn Guo goto err_clk_get; 171603d2bfc8SOlof Johansson } 17171e674bc6SPrashant Gaikwad clk_prepare_enable(clk); 171803d2bfc8SOlof Johansson pltfm_host->clk = clk; 171903d2bfc8SOlof Johansson 17202cd6c49dSPhilipp Zabel tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 17212cd6c49dSPhilipp Zabel "sdhci"); 172220567be9SThierry Reding if (IS_ERR(tegra_host->rst)) { 172320567be9SThierry Reding rc = PTR_ERR(tegra_host->rst); 172420567be9SThierry Reding dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 172520567be9SThierry Reding goto err_rst_get; 172620567be9SThierry Reding } 172720567be9SThierry Reding 172820567be9SThierry Reding rc = reset_control_assert(tegra_host->rst); 172920567be9SThierry Reding if (rc) 173020567be9SThierry Reding goto err_rst_get; 173120567be9SThierry Reding 173220567be9SThierry Reding usleep_range(2000, 4000); 173320567be9SThierry Reding 173420567be9SThierry Reding rc = reset_control_deassert(tegra_host->rst); 173520567be9SThierry Reding if (rc) 173620567be9SThierry Reding goto err_rst_get; 173720567be9SThierry Reding 173820567be9SThierry Reding usleep_range(2000, 4000); 173920567be9SThierry Reding 17403c4019f9SSowjanya Komatineni rc = sdhci_tegra_add_host(host); 174185d6509dSShawn Guo if (rc) 174285d6509dSShawn Guo goto err_add_host; 174385d6509dSShawn Guo 174403d2bfc8SOlof Johansson return 0; 174503d2bfc8SOlof Johansson 174685d6509dSShawn Guo err_add_host: 174720567be9SThierry Reding reset_control_assert(tegra_host->rst); 174820567be9SThierry Reding err_rst_get: 17491e674bc6SPrashant Gaikwad clk_disable_unprepare(pltfm_host->clk); 175085d6509dSShawn Guo err_clk_get: 17518048822bSSowjanya Komatineni clk_disable_unprepare(tegra_host->tmclk); 175285d6509dSShawn Guo err_power_req: 175347caa84fSSimon Baatz err_parse_dt: 175485d6509dSShawn Guo sdhci_pltfm_free(pdev); 175503d2bfc8SOlof Johansson return rc; 175603d2bfc8SOlof Johansson } 175703d2bfc8SOlof Johansson 175820567be9SThierry Reding static int sdhci_tegra_remove(struct platform_device *pdev) 175920567be9SThierry Reding { 176020567be9SThierry Reding struct sdhci_host *host = platform_get_drvdata(pdev); 176120567be9SThierry Reding struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 176220567be9SThierry Reding struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 176320567be9SThierry Reding 176420567be9SThierry Reding sdhci_remove_host(host, 0); 176520567be9SThierry Reding 176620567be9SThierry Reding reset_control_assert(tegra_host->rst); 176720567be9SThierry Reding usleep_range(2000, 4000); 176820567be9SThierry Reding clk_disable_unprepare(pltfm_host->clk); 17698048822bSSowjanya Komatineni clk_disable_unprepare(tegra_host->tmclk); 177020567be9SThierry Reding 177120567be9SThierry Reding sdhci_pltfm_free(pdev); 177220567be9SThierry Reding 177320567be9SThierry Reding return 0; 177420567be9SThierry Reding } 177520567be9SThierry Reding 177671c733c4SSowjanya Komatineni #ifdef CONFIG_PM_SLEEP 177771c733c4SSowjanya Komatineni static int __maybe_unused sdhci_tegra_suspend(struct device *dev) 177871c733c4SSowjanya Komatineni { 177971c733c4SSowjanya Komatineni struct sdhci_host *host = dev_get_drvdata(dev); 178071c733c4SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 178171c733c4SSowjanya Komatineni int ret; 178271c733c4SSowjanya Komatineni 178371c733c4SSowjanya Komatineni if (host->mmc->caps2 & MMC_CAP2_CQE) { 178471c733c4SSowjanya Komatineni ret = cqhci_suspend(host->mmc); 178571c733c4SSowjanya Komatineni if (ret) 178671c733c4SSowjanya Komatineni return ret; 178771c733c4SSowjanya Komatineni } 178871c733c4SSowjanya Komatineni 178971c733c4SSowjanya Komatineni ret = sdhci_suspend_host(host); 179071c733c4SSowjanya Komatineni if (ret) { 179171c733c4SSowjanya Komatineni cqhci_resume(host->mmc); 179271c733c4SSowjanya Komatineni return ret; 179371c733c4SSowjanya Komatineni } 179471c733c4SSowjanya Komatineni 179571c733c4SSowjanya Komatineni clk_disable_unprepare(pltfm_host->clk); 179671c733c4SSowjanya Komatineni return 0; 179771c733c4SSowjanya Komatineni } 179871c733c4SSowjanya Komatineni 179971c733c4SSowjanya Komatineni static int __maybe_unused sdhci_tegra_resume(struct device *dev) 180071c733c4SSowjanya Komatineni { 180171c733c4SSowjanya Komatineni struct sdhci_host *host = dev_get_drvdata(dev); 180271c733c4SSowjanya Komatineni struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 180371c733c4SSowjanya Komatineni int ret; 180471c733c4SSowjanya Komatineni 180571c733c4SSowjanya Komatineni ret = clk_prepare_enable(pltfm_host->clk); 180671c733c4SSowjanya Komatineni if (ret) 180771c733c4SSowjanya Komatineni return ret; 180871c733c4SSowjanya Komatineni 180971c733c4SSowjanya Komatineni ret = sdhci_resume_host(host); 181071c733c4SSowjanya Komatineni if (ret) 181171c733c4SSowjanya Komatineni goto disable_clk; 181271c733c4SSowjanya Komatineni 181371c733c4SSowjanya Komatineni if (host->mmc->caps2 & MMC_CAP2_CQE) { 181471c733c4SSowjanya Komatineni ret = cqhci_resume(host->mmc); 181571c733c4SSowjanya Komatineni if (ret) 181671c733c4SSowjanya Komatineni goto suspend_host; 181771c733c4SSowjanya Komatineni } 181871c733c4SSowjanya Komatineni 181971c733c4SSowjanya Komatineni return 0; 182071c733c4SSowjanya Komatineni 182171c733c4SSowjanya Komatineni suspend_host: 182271c733c4SSowjanya Komatineni sdhci_suspend_host(host); 182371c733c4SSowjanya Komatineni disable_clk: 182471c733c4SSowjanya Komatineni clk_disable_unprepare(pltfm_host->clk); 182571c733c4SSowjanya Komatineni return ret; 182671c733c4SSowjanya Komatineni } 182771c733c4SSowjanya Komatineni #endif 182871c733c4SSowjanya Komatineni 182971c733c4SSowjanya Komatineni static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend, 183071c733c4SSowjanya Komatineni sdhci_tegra_resume); 183171c733c4SSowjanya Komatineni 183285d6509dSShawn Guo static struct platform_driver sdhci_tegra_driver = { 183385d6509dSShawn Guo .driver = { 183485d6509dSShawn Guo .name = "sdhci-tegra", 183521b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1836275173b2SGrant Likely .of_match_table = sdhci_tegra_dt_match, 183771c733c4SSowjanya Komatineni .pm = &sdhci_tegra_dev_pm_ops, 183885d6509dSShawn Guo }, 183985d6509dSShawn Guo .probe = sdhci_tegra_probe, 184020567be9SThierry Reding .remove = sdhci_tegra_remove, 184103d2bfc8SOlof Johansson }; 184203d2bfc8SOlof Johansson 1843d1f81a64SAxel Lin module_platform_driver(sdhci_tegra_driver); 184485d6509dSShawn Guo 184585d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Tegra"); 184685d6509dSShawn Guo MODULE_AUTHOR("Google, Inc."); 184785d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1848