1 /* linux/drivers/mmc/host/sdhci-s3c.c 2 * 3 * Copyright 2008 Openmoko Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * SDHCI (HSMMC) support for Samsung SoC 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/gpio.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_gpio.h> 25 #include <linux/pm.h> 26 #include <linux/pm_runtime.h> 27 28 #include <linux/mmc/host.h> 29 30 #include <plat/sdhci.h> 31 #include <plat/regs-sdhci.h> 32 33 #include "sdhci.h" 34 35 #define MAX_BUS_CLK (4) 36 37 /** 38 * struct sdhci_s3c - S3C SDHCI instance 39 * @host: The SDHCI host created 40 * @pdev: The platform device we where created from. 41 * @ioarea: The resource created when we claimed the IO area. 42 * @pdata: The platform data for this controller. 43 * @cur_clk: The index of the current bus clock. 44 * @clk_io: The clock for the internal bus interface. 45 * @clk_bus: The clocks that are available for the SD/MMC bus clock. 46 */ 47 struct sdhci_s3c { 48 struct sdhci_host *host; 49 struct platform_device *pdev; 50 struct resource *ioarea; 51 struct s3c_sdhci_platdata *pdata; 52 unsigned int cur_clk; 53 int ext_cd_irq; 54 int ext_cd_gpio; 55 56 struct clk *clk_io; 57 struct clk *clk_bus[MAX_BUS_CLK]; 58 }; 59 60 /** 61 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data 62 * @sdhci_quirks: sdhci host specific quirks. 63 * 64 * Specifies platform specific configuration of sdhci controller. 65 * Note: A structure for driver specific platform data is used for future 66 * expansion of its usage. 67 */ 68 struct sdhci_s3c_drv_data { 69 unsigned int sdhci_quirks; 70 }; 71 72 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) 73 { 74 return sdhci_priv(host); 75 } 76 77 /** 78 * get_curclk - convert ctrl2 register to clock source number 79 * @ctrl2: Control2 register value. 80 */ 81 static u32 get_curclk(u32 ctrl2) 82 { 83 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; 84 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 85 86 return ctrl2; 87 } 88 89 static void sdhci_s3c_check_sclk(struct sdhci_host *host) 90 { 91 struct sdhci_s3c *ourhost = to_s3c(host); 92 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 93 94 if (get_curclk(tmp) != ourhost->cur_clk) { 95 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n"); 96 97 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 98 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 99 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2); 100 } 101 } 102 103 /** 104 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. 105 * @host: The SDHCI host instance. 106 * 107 * Callback to return the maximum clock rate acheivable by the controller. 108 */ 109 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) 110 { 111 struct sdhci_s3c *ourhost = to_s3c(host); 112 struct clk *busclk; 113 unsigned int rate, max; 114 int clk; 115 116 /* note, a reset will reset the clock source */ 117 118 sdhci_s3c_check_sclk(host); 119 120 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) { 121 busclk = ourhost->clk_bus[clk]; 122 if (!busclk) 123 continue; 124 125 rate = clk_get_rate(busclk); 126 if (rate > max) 127 max = rate; 128 } 129 130 return max; 131 } 132 133 /** 134 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting 135 * @ourhost: Our SDHCI instance. 136 * @src: The source clock index. 137 * @wanted: The clock frequency wanted. 138 */ 139 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, 140 unsigned int src, 141 unsigned int wanted) 142 { 143 unsigned long rate; 144 struct clk *clksrc = ourhost->clk_bus[src]; 145 int div; 146 147 if (!clksrc) 148 return UINT_MAX; 149 150 /* 151 * If controller uses a non-standard clock division, find the best clock 152 * speed possible with selected clock source and skip the division. 153 */ 154 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 155 rate = clk_round_rate(clksrc, wanted); 156 return wanted - rate; 157 } 158 159 rate = clk_get_rate(clksrc); 160 161 for (div = 1; div < 256; div *= 2) { 162 if ((rate / div) <= wanted) 163 break; 164 } 165 166 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", 167 src, rate, wanted, rate / div); 168 169 return (wanted - (rate / div)); 170 } 171 172 /** 173 * sdhci_s3c_set_clock - callback on clock change 174 * @host: The SDHCI host being changed 175 * @clock: The clock rate being requested. 176 * 177 * When the card's clock is going to be changed, look at the new frequency 178 * and find the best clock source to go with it. 179 */ 180 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) 181 { 182 struct sdhci_s3c *ourhost = to_s3c(host); 183 unsigned int best = UINT_MAX; 184 unsigned int delta; 185 int best_src = 0; 186 int src; 187 u32 ctrl; 188 189 /* don't bother if the clock is going off. */ 190 if (clock == 0) 191 return; 192 193 for (src = 0; src < MAX_BUS_CLK; src++) { 194 delta = sdhci_s3c_consider_clock(ourhost, src, clock); 195 if (delta < best) { 196 best = delta; 197 best_src = src; 198 } 199 } 200 201 dev_dbg(&ourhost->pdev->dev, 202 "selected source %d, clock %d, delta %d\n", 203 best_src, clock, best); 204 205 /* select the new clock source */ 206 207 if (ourhost->cur_clk != best_src) { 208 struct clk *clk = ourhost->clk_bus[best_src]; 209 210 /* turn clock off to card before changing clock source */ 211 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 212 213 ourhost->cur_clk = best_src; 214 host->max_clk = clk_get_rate(clk); 215 216 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 217 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 218 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 219 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 220 } 221 222 /* reprogram default hardware configuration */ 223 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, 224 host->ioaddr + S3C64XX_SDHCI_CONTROL4); 225 226 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 227 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | 228 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | 229 S3C_SDHCI_CTRL2_ENFBCLKRX | 230 S3C_SDHCI_CTRL2_DFCNT_NONE | 231 S3C_SDHCI_CTRL2_ENCLKOUTHOLD); 232 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 233 234 /* reconfigure the controller for new clock rate */ 235 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); 236 if (clock < 25 * 1000000) 237 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); 238 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); 239 } 240 241 /** 242 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value 243 * @host: The SDHCI host being queried 244 * 245 * To init mmc host properly a minimal clock value is needed. For high system 246 * bus clock's values the standard formula gives values out of allowed range. 247 * The clock still can be set to lower values, if clock source other then 248 * system bus is selected. 249 */ 250 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) 251 { 252 struct sdhci_s3c *ourhost = to_s3c(host); 253 unsigned int delta, min = UINT_MAX; 254 int src; 255 256 for (src = 0; src < MAX_BUS_CLK; src++) { 257 delta = sdhci_s3c_consider_clock(ourhost, src, 0); 258 if (delta == UINT_MAX) 259 continue; 260 /* delta is a negative value in this case */ 261 if (-delta < min) 262 min = -delta; 263 } 264 return min; 265 } 266 267 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ 268 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) 269 { 270 struct sdhci_s3c *ourhost = to_s3c(host); 271 272 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX); 273 } 274 275 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ 276 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) 277 { 278 struct sdhci_s3c *ourhost = to_s3c(host); 279 280 /* 281 * initial clock can be in the frequency range of 282 * 100KHz-400KHz, so we set it as max value. 283 */ 284 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000); 285 } 286 287 /* sdhci_cmu_set_clock - callback on clock change.*/ 288 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) 289 { 290 struct sdhci_s3c *ourhost = to_s3c(host); 291 unsigned long timeout; 292 u16 clk = 0; 293 294 /* don't bother if the clock is going off */ 295 if (clock == 0) 296 return; 297 298 sdhci_s3c_set_clock(host, clock); 299 300 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); 301 302 host->clock = clock; 303 304 clk = SDHCI_CLOCK_INT_EN; 305 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 306 307 /* Wait max 20 ms */ 308 timeout = 20; 309 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 310 & SDHCI_CLOCK_INT_STABLE)) { 311 if (timeout == 0) { 312 printk(KERN_ERR "%s: Internal clock never " 313 "stabilised.\n", mmc_hostname(host->mmc)); 314 return; 315 } 316 timeout--; 317 mdelay(1); 318 } 319 320 clk |= SDHCI_CLOCK_CARD_EN; 321 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 322 } 323 324 /** 325 * sdhci_s3c_platform_8bit_width - support 8bit buswidth 326 * @host: The SDHCI host being queried 327 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested 328 * 329 * We have 8-bit width support but is not a v3 controller. 330 * So we add platform_8bit_width() and support 8bit width. 331 */ 332 static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width) 333 { 334 u8 ctrl; 335 336 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 337 338 switch (width) { 339 case MMC_BUS_WIDTH_8: 340 ctrl |= SDHCI_CTRL_8BITBUS; 341 ctrl &= ~SDHCI_CTRL_4BITBUS; 342 break; 343 case MMC_BUS_WIDTH_4: 344 ctrl |= SDHCI_CTRL_4BITBUS; 345 ctrl &= ~SDHCI_CTRL_8BITBUS; 346 break; 347 default: 348 ctrl &= ~SDHCI_CTRL_4BITBUS; 349 ctrl &= ~SDHCI_CTRL_8BITBUS; 350 break; 351 } 352 353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 354 355 return 0; 356 } 357 358 static struct sdhci_ops sdhci_s3c_ops = { 359 .get_max_clock = sdhci_s3c_get_max_clk, 360 .set_clock = sdhci_s3c_set_clock, 361 .get_min_clock = sdhci_s3c_get_min_clock, 362 .platform_8bit_width = sdhci_s3c_platform_8bit_width, 363 }; 364 365 static void sdhci_s3c_notify_change(struct platform_device *dev, int state) 366 { 367 struct sdhci_host *host = platform_get_drvdata(dev); 368 unsigned long flags; 369 370 if (host) { 371 spin_lock_irqsave(&host->lock, flags); 372 if (state) { 373 dev_dbg(&dev->dev, "card inserted.\n"); 374 host->flags &= ~SDHCI_DEVICE_DEAD; 375 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 376 } else { 377 dev_dbg(&dev->dev, "card removed.\n"); 378 host->flags |= SDHCI_DEVICE_DEAD; 379 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 380 } 381 tasklet_schedule(&host->card_tasklet); 382 spin_unlock_irqrestore(&host->lock, flags); 383 } 384 } 385 386 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) 387 { 388 struct sdhci_s3c *sc = dev_id; 389 int status = gpio_get_value(sc->ext_cd_gpio); 390 if (sc->pdata->ext_cd_gpio_invert) 391 status = !status; 392 sdhci_s3c_notify_change(sc->pdev, status); 393 return IRQ_HANDLED; 394 } 395 396 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) 397 { 398 struct s3c_sdhci_platdata *pdata = sc->pdata; 399 struct device *dev = &sc->pdev->dev; 400 401 if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { 402 sc->ext_cd_gpio = pdata->ext_cd_gpio; 403 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); 404 if (sc->ext_cd_irq && 405 request_threaded_irq(sc->ext_cd_irq, NULL, 406 sdhci_s3c_gpio_card_detect_thread, 407 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 408 dev_name(dev), sc) == 0) { 409 int status = gpio_get_value(sc->ext_cd_gpio); 410 if (pdata->ext_cd_gpio_invert) 411 status = !status; 412 sdhci_s3c_notify_change(sc->pdev, status); 413 } else { 414 dev_warn(dev, "cannot request irq for card detect\n"); 415 sc->ext_cd_irq = 0; 416 } 417 } else { 418 dev_err(dev, "cannot request gpio for card detect\n"); 419 } 420 } 421 422 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( 423 struct platform_device *pdev) 424 { 425 return (struct sdhci_s3c_drv_data *) 426 platform_get_device_id(pdev)->driver_data; 427 } 428 429 static int __devinit sdhci_s3c_probe(struct platform_device *pdev) 430 { 431 struct s3c_sdhci_platdata *pdata; 432 struct sdhci_s3c_drv_data *drv_data; 433 struct device *dev = &pdev->dev; 434 struct sdhci_host *host; 435 struct sdhci_s3c *sc; 436 struct resource *res; 437 int ret, irq, ptr, clks; 438 439 if (!pdev->dev.platform_data) { 440 dev_err(dev, "no device data specified\n"); 441 return -ENOENT; 442 } 443 444 irq = platform_get_irq(pdev, 0); 445 if (irq < 0) { 446 dev_err(dev, "no irq specified\n"); 447 return irq; 448 } 449 450 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 451 if (IS_ERR(host)) { 452 dev_err(dev, "sdhci_alloc_host() failed\n"); 453 return PTR_ERR(host); 454 } 455 456 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 457 if (!pdata) { 458 ret = -ENOMEM; 459 goto err_io_clk; 460 } 461 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 462 463 drv_data = sdhci_s3c_get_driver_data(pdev); 464 sc = sdhci_priv(host); 465 466 sc->host = host; 467 sc->pdev = pdev; 468 sc->pdata = pdata; 469 sc->ext_cd_gpio = -1; /* invalid gpio number */ 470 471 platform_set_drvdata(pdev, host); 472 473 sc->clk_io = clk_get(dev, "hsmmc"); 474 if (IS_ERR(sc->clk_io)) { 475 dev_err(dev, "failed to get io clock\n"); 476 ret = PTR_ERR(sc->clk_io); 477 goto err_io_clk; 478 } 479 480 /* enable the local io clock and keep it running for the moment. */ 481 clk_enable(sc->clk_io); 482 483 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 484 struct clk *clk; 485 char name[14]; 486 487 snprintf(name, 14, "mmc_busclk.%d", ptr); 488 clk = clk_get(dev, name); 489 if (IS_ERR(clk)) { 490 continue; 491 } 492 493 clks++; 494 sc->clk_bus[ptr] = clk; 495 496 /* 497 * save current clock index to know which clock bus 498 * is used later in overriding functions. 499 */ 500 sc->cur_clk = ptr; 501 502 clk_enable(clk); 503 504 dev_info(dev, "clock source %d: %s (%ld Hz)\n", 505 ptr, name, clk_get_rate(clk)); 506 } 507 508 if (clks == 0) { 509 dev_err(dev, "failed to find any bus clocks\n"); 510 ret = -ENOENT; 511 goto err_no_busclks; 512 } 513 514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 515 host->ioaddr = devm_request_and_ioremap(&pdev->dev, res); 516 if (!host->ioaddr) { 517 dev_err(dev, "failed to map registers\n"); 518 ret = -ENXIO; 519 goto err_req_regs; 520 } 521 522 /* Ensure we have minimal gpio selected CMD/CLK/Detect */ 523 if (pdata->cfg_gpio) 524 pdata->cfg_gpio(pdev, pdata->max_width); 525 526 host->hw_name = "samsung-hsmmc"; 527 host->ops = &sdhci_s3c_ops; 528 host->quirks = 0; 529 host->irq = irq; 530 531 /* Setup quirks for the controller */ 532 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; 533 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 534 if (drv_data) 535 host->quirks |= drv_data->sdhci_quirks; 536 537 #ifndef CONFIG_MMC_SDHCI_S3C_DMA 538 539 /* we currently see overruns on errors, so disable the SDMA 540 * support as well. */ 541 host->quirks |= SDHCI_QUIRK_BROKEN_DMA; 542 543 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ 544 545 /* It seems we do not get an DATA transfer complete on non-busy 546 * transfers, not sure if this is a problem with this specific 547 * SDHCI block, or a missing configuration that needs to be set. */ 548 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; 549 550 /* This host supports the Auto CMD12 */ 551 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 552 553 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ 554 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; 555 556 if (pdata->cd_type == S3C_SDHCI_CD_NONE || 557 pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 558 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 559 560 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 561 host->mmc->caps = MMC_CAP_NONREMOVABLE; 562 563 switch (pdata->max_width) { 564 case 8: 565 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 566 case 4: 567 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 568 break; 569 } 570 571 if (pdata->pm_caps) 572 host->mmc->pm_caps |= pdata->pm_caps; 573 574 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | 575 SDHCI_QUIRK_32BIT_DMA_SIZE); 576 577 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 578 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 579 580 /* 581 * If controller does not have internal clock divider, 582 * we can use overriding functions instead of default. 583 */ 584 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 585 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 586 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 587 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 588 } 589 590 /* It supports additional host capabilities if needed */ 591 if (pdata->host_caps) 592 host->mmc->caps |= pdata->host_caps; 593 594 if (pdata->host_caps2) 595 host->mmc->caps2 |= pdata->host_caps2; 596 597 pm_runtime_enable(&pdev->dev); 598 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 599 pm_runtime_use_autosuspend(&pdev->dev); 600 pm_suspend_ignore_children(&pdev->dev, 1); 601 602 ret = sdhci_add_host(host); 603 if (ret) { 604 dev_err(dev, "sdhci_add_host() failed\n"); 605 pm_runtime_forbid(&pdev->dev); 606 pm_runtime_get_noresume(&pdev->dev); 607 goto err_req_regs; 608 } 609 610 /* The following two methods of card detection might call 611 sdhci_s3c_notify_change() immediately, so they can be called 612 only after sdhci_add_host(). Setup errors are ignored. */ 613 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) 614 pdata->ext_cd_init(&sdhci_s3c_notify_change); 615 if (pdata->cd_type == S3C_SDHCI_CD_GPIO && 616 gpio_is_valid(pdata->ext_cd_gpio)) 617 sdhci_s3c_setup_card_detect_gpio(sc); 618 619 return 0; 620 621 err_req_regs: 622 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 623 if (sc->clk_bus[ptr]) { 624 clk_disable(sc->clk_bus[ptr]); 625 clk_put(sc->clk_bus[ptr]); 626 } 627 } 628 629 err_no_busclks: 630 clk_disable(sc->clk_io); 631 clk_put(sc->clk_io); 632 633 err_io_clk: 634 sdhci_free_host(host); 635 636 return ret; 637 } 638 639 static int __devexit sdhci_s3c_remove(struct platform_device *pdev) 640 { 641 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data; 642 struct sdhci_host *host = platform_get_drvdata(pdev); 643 struct sdhci_s3c *sc = sdhci_priv(host); 644 int ptr; 645 646 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) 647 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); 648 649 if (sc->ext_cd_irq) 650 free_irq(sc->ext_cd_irq, sc); 651 652 if (gpio_is_valid(sc->ext_cd_gpio)) 653 gpio_free(sc->ext_cd_gpio); 654 655 sdhci_remove_host(host, 1); 656 657 pm_runtime_disable(&pdev->dev); 658 659 for (ptr = 0; ptr < 3; ptr++) { 660 if (sc->clk_bus[ptr]) { 661 clk_disable(sc->clk_bus[ptr]); 662 clk_put(sc->clk_bus[ptr]); 663 } 664 } 665 clk_disable(sc->clk_io); 666 clk_put(sc->clk_io); 667 668 sdhci_free_host(host); 669 platform_set_drvdata(pdev, NULL); 670 671 return 0; 672 } 673 674 #ifdef CONFIG_PM_SLEEP 675 static int sdhci_s3c_suspend(struct device *dev) 676 { 677 struct sdhci_host *host = dev_get_drvdata(dev); 678 679 return sdhci_suspend_host(host); 680 } 681 682 static int sdhci_s3c_resume(struct device *dev) 683 { 684 struct sdhci_host *host = dev_get_drvdata(dev); 685 686 return sdhci_resume_host(host); 687 } 688 #endif 689 690 #ifdef CONFIG_PM_RUNTIME 691 static int sdhci_s3c_runtime_suspend(struct device *dev) 692 { 693 struct sdhci_host *host = dev_get_drvdata(dev); 694 695 return sdhci_runtime_suspend_host(host); 696 } 697 698 static int sdhci_s3c_runtime_resume(struct device *dev) 699 { 700 struct sdhci_host *host = dev_get_drvdata(dev); 701 702 return sdhci_runtime_resume_host(host); 703 } 704 #endif 705 706 #ifdef CONFIG_PM 707 static const struct dev_pm_ops sdhci_s3c_pmops = { 708 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 709 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 710 NULL) 711 }; 712 713 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) 714 715 #else 716 #define SDHCI_S3C_PMOPS NULL 717 #endif 718 719 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 720 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 721 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, 722 }; 723 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) 724 #else 725 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) 726 #endif 727 728 static struct platform_device_id sdhci_s3c_driver_ids[] = { 729 { 730 .name = "s3c-sdhci", 731 .driver_data = (kernel_ulong_t)NULL, 732 }, { 733 .name = "exynos4-sdhci", 734 .driver_data = EXYNOS4_SDHCI_DRV_DATA, 735 }, 736 { } 737 }; 738 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); 739 740 static struct platform_driver sdhci_s3c_driver = { 741 .probe = sdhci_s3c_probe, 742 .remove = __devexit_p(sdhci_s3c_remove), 743 .id_table = sdhci_s3c_driver_ids, 744 .driver = { 745 .owner = THIS_MODULE, 746 .name = "s3c-sdhci", 747 .pm = SDHCI_S3C_PMOPS, 748 }, 749 }; 750 751 module_platform_driver(sdhci_s3c_driver); 752 753 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); 754 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 755 MODULE_LICENSE("GPL v2"); 756 MODULE_ALIAS("platform:s3c-sdhci"); 757