xref: /openbmc/linux/drivers/mmc/host/sdhci-s3c.c (revision 0c6dfa75) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
3  *
4  * Copyright 2008 Openmoko Inc.
5  * Copyright 2008 Simtec Electronics
6  *      Ben Dooks <ben@simtec.co.uk>
7  *      http://armlinux.simtec.co.uk/
8  *
9  * SDHCI (HSMMC) support for Samsung SoC
10  */
11 
12 #include <linux/spinlock.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pm.h>
25 #include <linux/pm_runtime.h>
26 
27 #include <linux/mmc/host.h>
28 
29 #include "sdhci.h"
30 
31 #define MAX_BUS_CLK	(4)
32 
33 #define S3C_SDHCI_CONTROL2			(0x80)
34 #define S3C_SDHCI_CONTROL3			(0x84)
35 #define S3C64XX_SDHCI_CONTROL4			(0x8C)
36 
37 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR	BIT(31)
38 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK		BIT(30)
39 #define S3C_SDHCI_CTRL2_CDINVRXD3		BIT(29)
40 #define S3C_SDHCI_CTRL2_SLCARDOUT		BIT(28)
41 
42 #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK		(0xf << 24)
43 #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT		(24)
44 #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)		((_x) << 24)
45 
46 #define S3C_SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
47 #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT		(16)
48 #define S3C_SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
49 
50 #define S3C_SDHCI_CTRL2_ENFBCLKTX		BIT(15)
51 #define S3C_SDHCI_CTRL2_ENFBCLKRX		BIT(14)
52 #define S3C_SDHCI_CTRL2_SDCDSEL			BIT(13)
53 #define S3C_SDHCI_CTRL2_SDSIGPC			BIT(12)
54 #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART	BIT(11)
55 
56 #define S3C_SDHCI_CTRL2_DFCNT_MASK		(0x3 << 9)
57 #define S3C_SDHCI_CTRL2_DFCNT_SHIFT		(9)
58 #define S3C_SDHCI_CTRL2_DFCNT_NONE		(0x0 << 9)
59 #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK		(0x1 << 9)
60 #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK		(0x2 << 9)
61 #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK		(0x3 << 9)
62 
63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD		BIT(8)
64 #define S3C_SDHCI_CTRL2_RWAITMODE		BIT(7)
65 #define S3C_SDHCI_CTRL2_DISBUFRD		BIT(6)
66 
67 #define S3C_SDHCI_CTRL2_SELBASECLK_MASK		(0x3 << 4)
68 #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
69 #define S3C_SDHCI_CTRL2_PWRSYNC			BIT(3)
70 #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON		BIT(1)
71 #define S3C_SDHCI_CTRL2_HWINITFIN		BIT(0)
72 
73 #define S3C_SDHCI_CTRL3_FCSEL3			BIT(31)
74 #define S3C_SDHCI_CTRL3_FCSEL2			BIT(23)
75 #define S3C_SDHCI_CTRL3_FCSEL1			BIT(15)
76 #define S3C_SDHCI_CTRL3_FCSEL0			BIT(7)
77 
78 #define S3C_SDHCI_CTRL3_FIA3_MASK		(0x7f << 24)
79 #define S3C_SDHCI_CTRL3_FIA3_SHIFT		(24)
80 #define S3C_SDHCI_CTRL3_FIA3(_x)		((_x) << 24)
81 
82 #define S3C_SDHCI_CTRL3_FIA2_MASK		(0x7f << 16)
83 #define S3C_SDHCI_CTRL3_FIA2_SHIFT		(16)
84 #define S3C_SDHCI_CTRL3_FIA2(_x)		((_x) << 16)
85 
86 #define S3C_SDHCI_CTRL3_FIA1_MASK		(0x7f << 8)
87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT		(8)
88 #define S3C_SDHCI_CTRL3_FIA1(_x)		((_x) << 8)
89 
90 #define S3C_SDHCI_CTRL3_FIA0_MASK		(0x7f << 0)
91 #define S3C_SDHCI_CTRL3_FIA0_SHIFT		(0)
92 #define S3C_SDHCI_CTRL3_FIA0(_x)		((_x) << 0)
93 
94 #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK	(0x3 << 16)
95 #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT	(16)
96 #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA	(0x0 << 16)
97 #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA	(0x1 << 16)
98 #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA	(0x2 << 16)
99 #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA	(0x3 << 16)
100 
101 #define S3C64XX_SDHCI_CONTROL4_BUSY		(1)
102 
103 /**
104  * struct sdhci_s3c - S3C SDHCI instance
105  * @host: The SDHCI host created
106  * @pdev: The platform device we where created from.
107  * @ioarea: The resource created when we claimed the IO area.
108  * @pdata: The platform data for this controller.
109  * @cur_clk: The index of the current bus clock.
110  * @ext_cd_irq: External card detect interrupt.
111  * @clk_io: The clock for the internal bus interface.
112  * @clk_rates: Clock frequencies.
113  * @clk_bus: The clocks that are available for the SD/MMC bus clock.
114  * @no_divider: No or non-standard internal clock divider.
115  */
116 struct sdhci_s3c {
117 	struct sdhci_host	*host;
118 	struct platform_device	*pdev;
119 	struct resource		*ioarea;
120 	struct s3c_sdhci_platdata *pdata;
121 	int			cur_clk;
122 	int			ext_cd_irq;
123 
124 	struct clk		*clk_io;
125 	struct clk		*clk_bus[MAX_BUS_CLK];
126 	unsigned long		clk_rates[MAX_BUS_CLK];
127 
128 	bool			no_divider;
129 };
130 
131 /**
132  * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
133  * @sdhci_quirks: sdhci host specific quirks.
134  * @no_divider: no or non-standard internal clock divider.
135  *
136  * Specifies platform specific configuration of sdhci controller.
137  * Note: A structure for driver specific platform data is used for future
138  * expansion of its usage.
139  */
140 struct sdhci_s3c_drv_data {
141 	unsigned int	sdhci_quirks;
142 	bool		no_divider;
143 };
144 
145 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146 {
147 	return sdhci_priv(host);
148 }
149 
150 /**
151  * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
152  * @host: The SDHCI host instance.
153  *
154  * Callback to return the maximum clock rate acheivable by the controller.
155 */
156 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157 {
158 	struct sdhci_s3c *ourhost = to_s3c(host);
159 	unsigned long rate, max = 0;
160 	int src;
161 
162 	for (src = 0; src < MAX_BUS_CLK; src++) {
163 		rate = ourhost->clk_rates[src];
164 		if (rate > max)
165 			max = rate;
166 	}
167 
168 	return max;
169 }
170 
171 /**
172  * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
173  * @ourhost: Our SDHCI instance.
174  * @src: The source clock index.
175  * @wanted: The clock frequency wanted.
176  */
177 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
178 					     unsigned int src,
179 					     unsigned int wanted)
180 {
181 	unsigned long rate;
182 	struct clk *clksrc = ourhost->clk_bus[src];
183 	int shift;
184 
185 	if (IS_ERR(clksrc))
186 		return UINT_MAX;
187 
188 	/*
189 	 * If controller uses a non-standard clock division, find the best clock
190 	 * speed possible with selected clock source and skip the division.
191 	 */
192 	if (ourhost->no_divider) {
193 		rate = clk_round_rate(clksrc, wanted);
194 		return wanted - rate;
195 	}
196 
197 	rate = ourhost->clk_rates[src];
198 
199 	for (shift = 0; shift <= 8; ++shift) {
200 		if ((rate >> shift) <= wanted)
201 			break;
202 	}
203 
204 	if (shift > 8) {
205 		dev_dbg(&ourhost->pdev->dev,
206 			"clk %d: rate %ld, min rate %lu > wanted %u\n",
207 			src, rate, rate / 256, wanted);
208 		return UINT_MAX;
209 	}
210 
211 	dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
212 		src, rate, wanted, rate >> shift);
213 
214 	return wanted - (rate >> shift);
215 }
216 
217 /**
218  * sdhci_s3c_set_clock - callback on clock change
219  * @host: The SDHCI host being changed
220  * @clock: The clock rate being requested.
221  *
222  * When the card's clock is going to be changed, look at the new frequency
223  * and find the best clock source to go with it.
224 */
225 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
226 {
227 	struct sdhci_s3c *ourhost = to_s3c(host);
228 	unsigned int best = UINT_MAX;
229 	unsigned int delta;
230 	int best_src = 0;
231 	int src;
232 	u32 ctrl;
233 
234 	host->mmc->actual_clock = 0;
235 
236 	/* don't bother if the clock is going off. */
237 	if (clock == 0) {
238 		sdhci_set_clock(host, clock);
239 		return;
240 	}
241 
242 	for (src = 0; src < MAX_BUS_CLK; src++) {
243 		delta = sdhci_s3c_consider_clock(ourhost, src, clock);
244 		if (delta < best) {
245 			best = delta;
246 			best_src = src;
247 		}
248 	}
249 
250 	dev_dbg(&ourhost->pdev->dev,
251 		"selected source %d, clock %d, delta %d\n",
252 		 best_src, clock, best);
253 
254 	/* select the new clock source */
255 	if (ourhost->cur_clk != best_src) {
256 		struct clk *clk = ourhost->clk_bus[best_src];
257 
258 		clk_prepare_enable(clk);
259 		if (ourhost->cur_clk >= 0)
260 			clk_disable_unprepare(
261 					ourhost->clk_bus[ourhost->cur_clk]);
262 
263 		ourhost->cur_clk = best_src;
264 		host->max_clk = ourhost->clk_rates[best_src];
265 	}
266 
267 	/* turn clock off to card before changing clock source */
268 	writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
269 
270 	ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
271 	ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
272 	ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
273 	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
274 
275 	/* reprogram default hardware configuration */
276 	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
277 		host->ioaddr + S3C64XX_SDHCI_CONTROL4);
278 
279 	ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
280 	ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
281 		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
282 		  S3C_SDHCI_CTRL2_ENFBCLKRX |
283 		  S3C_SDHCI_CTRL2_DFCNT_NONE |
284 		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
285 	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
286 
287 	/* reconfigure the controller for new clock rate */
288 	ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
289 	if (clock < 25 * 1000000)
290 		ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
291 	writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
292 
293 	sdhci_set_clock(host, clock);
294 }
295 
296 /**
297  * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
298  * @host: The SDHCI host being queried
299  *
300  * To init mmc host properly a minimal clock value is needed. For high system
301  * bus clock's values the standard formula gives values out of allowed range.
302  * The clock still can be set to lower values, if clock source other then
303  * system bus is selected.
304 */
305 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306 {
307 	struct sdhci_s3c *ourhost = to_s3c(host);
308 	unsigned long rate, min = ULONG_MAX;
309 	int src;
310 
311 	for (src = 0; src < MAX_BUS_CLK; src++) {
312 		rate = ourhost->clk_rates[src] / 256;
313 		if (!rate)
314 			continue;
315 		if (rate < min)
316 			min = rate;
317 	}
318 
319 	return min;
320 }
321 
322 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
323 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324 {
325 	struct sdhci_s3c *ourhost = to_s3c(host);
326 	unsigned long rate, max = 0;
327 	int src;
328 
329 	for (src = 0; src < MAX_BUS_CLK; src++) {
330 		struct clk *clk;
331 
332 		clk = ourhost->clk_bus[src];
333 		if (IS_ERR(clk))
334 			continue;
335 
336 		rate = clk_round_rate(clk, ULONG_MAX);
337 		if (rate > max)
338 			max = rate;
339 	}
340 
341 	return max;
342 }
343 
344 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
345 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346 {
347 	struct sdhci_s3c *ourhost = to_s3c(host);
348 	unsigned long rate, min = ULONG_MAX;
349 	int src;
350 
351 	for (src = 0; src < MAX_BUS_CLK; src++) {
352 		struct clk *clk;
353 
354 		clk = ourhost->clk_bus[src];
355 		if (IS_ERR(clk))
356 			continue;
357 
358 		rate = clk_round_rate(clk, 0);
359 		if (rate < min)
360 			min = rate;
361 	}
362 
363 	return min;
364 }
365 
366 /* sdhci_cmu_set_clock - callback on clock change.*/
367 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368 {
369 	struct sdhci_s3c *ourhost = to_s3c(host);
370 	struct device *dev = &ourhost->pdev->dev;
371 	unsigned long timeout;
372 	u16 clk = 0;
373 	int ret;
374 
375 	host->mmc->actual_clock = 0;
376 
377 	/* If the clock is going off, set to 0 at clock control register */
378 	if (clock == 0) {
379 		sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380 		return;
381 	}
382 
383 	sdhci_s3c_set_clock(host, clock);
384 
385 	/* Reset SD Clock Enable */
386 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387 	clk &= ~SDHCI_CLOCK_CARD_EN;
388 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389 
390 	ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391 	if (ret != 0) {
392 		dev_err(dev, "%s: failed to set clock rate %uHz\n",
393 			mmc_hostname(host->mmc), clock);
394 		return;
395 	}
396 
397 	clk = SDHCI_CLOCK_INT_EN;
398 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
399 
400 	/* Wait max 20 ms */
401 	timeout = 20;
402 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
403 		& SDHCI_CLOCK_INT_STABLE)) {
404 		if (timeout == 0) {
405 			dev_err(dev, "%s: Internal clock never stabilised.\n",
406 				mmc_hostname(host->mmc));
407 			return;
408 		}
409 		timeout--;
410 		mdelay(1);
411 	}
412 
413 	clk |= SDHCI_CLOCK_CARD_EN;
414 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415 }
416 
417 static struct sdhci_ops sdhci_s3c_ops = {
418 	.get_max_clock		= sdhci_s3c_get_max_clk,
419 	.set_clock		= sdhci_s3c_set_clock,
420 	.get_min_clock		= sdhci_s3c_get_min_clock,
421 	.set_bus_width		= sdhci_set_bus_width,
422 	.reset			= sdhci_reset,
423 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
424 };
425 
426 #ifdef CONFIG_OF
427 static int sdhci_s3c_parse_dt(struct device *dev,
428 		struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
429 {
430 	struct device_node *node = dev->of_node;
431 	u32 max_width;
432 
433 	/* if the bus-width property is not specified, assume width as 1 */
434 	if (of_property_read_u32(node, "bus-width", &max_width))
435 		max_width = 1;
436 	pdata->max_width = max_width;
437 
438 	/* get the card detection method */
439 	if (of_property_read_bool(node, "broken-cd")) {
440 		pdata->cd_type = S3C_SDHCI_CD_NONE;
441 		return 0;
442 	}
443 
444 	if (of_property_read_bool(node, "non-removable")) {
445 		pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
446 		return 0;
447 	}
448 
449 	if (of_get_named_gpio(node, "cd-gpios", 0))
450 		return 0;
451 
452 	/* assuming internal card detect that will be configured by pinctrl */
453 	pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
454 	return 0;
455 }
456 #else
457 static int sdhci_s3c_parse_dt(struct device *dev,
458 		struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
459 {
460 	return -EINVAL;
461 }
462 #endif
463 
464 static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
465 			struct platform_device *pdev)
466 {
467 #ifdef CONFIG_OF
468 	if (pdev->dev.of_node)
469 		return of_device_get_match_data(&pdev->dev);
470 #endif
471 	return (const struct sdhci_s3c_drv_data *)
472 			platform_get_device_id(pdev)->driver_data;
473 }
474 
475 static int sdhci_s3c_probe(struct platform_device *pdev)
476 {
477 	struct s3c_sdhci_platdata *pdata;
478 	const struct sdhci_s3c_drv_data *drv_data;
479 	struct device *dev = &pdev->dev;
480 	struct sdhci_host *host;
481 	struct sdhci_s3c *sc;
482 	int ret, irq, ptr, clks;
483 
484 	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
485 		dev_err(dev, "no device data specified\n");
486 		return -ENOENT;
487 	}
488 
489 	irq = platform_get_irq(pdev, 0);
490 	if (irq < 0)
491 		return irq;
492 
493 	host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
494 	if (IS_ERR(host)) {
495 		dev_err(dev, "sdhci_alloc_host() failed\n");
496 		return PTR_ERR(host);
497 	}
498 	sc = sdhci_priv(host);
499 
500 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
501 	if (!pdata) {
502 		ret = -ENOMEM;
503 		goto err_pdata_io_clk;
504 	}
505 
506 	if (pdev->dev.of_node) {
507 		ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
508 		if (ret)
509 			goto err_pdata_io_clk;
510 	} else {
511 		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
512 	}
513 
514 	drv_data = sdhci_s3c_get_driver_data(pdev);
515 
516 	sc->host = host;
517 	sc->pdev = pdev;
518 	sc->pdata = pdata;
519 	sc->cur_clk = -1;
520 
521 	platform_set_drvdata(pdev, host);
522 
523 	sc->clk_io = devm_clk_get(dev, "hsmmc");
524 	if (IS_ERR(sc->clk_io)) {
525 		dev_err(dev, "failed to get io clock\n");
526 		ret = PTR_ERR(sc->clk_io);
527 		goto err_pdata_io_clk;
528 	}
529 
530 	/* enable the local io clock and keep it running for the moment. */
531 	clk_prepare_enable(sc->clk_io);
532 
533 	for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
534 		char name[14];
535 
536 		snprintf(name, 14, "mmc_busclk.%d", ptr);
537 		sc->clk_bus[ptr] = devm_clk_get(dev, name);
538 		if (IS_ERR(sc->clk_bus[ptr]))
539 			continue;
540 
541 		clks++;
542 		sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
543 
544 		dev_info(dev, "clock source %d: %s (%ld Hz)\n",
545 				ptr, name, sc->clk_rates[ptr]);
546 	}
547 
548 	if (clks == 0) {
549 		dev_err(dev, "failed to find any bus clocks\n");
550 		ret = -ENOENT;
551 		goto err_no_busclks;
552 	}
553 
554 	host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
555 	if (IS_ERR(host->ioaddr)) {
556 		ret = PTR_ERR(host->ioaddr);
557 		goto err_req_regs;
558 	}
559 
560 	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
561 	if (pdata->cfg_gpio)
562 		pdata->cfg_gpio(pdev, pdata->max_width);
563 
564 	host->hw_name = "samsung-hsmmc";
565 	host->ops = &sdhci_s3c_ops;
566 	host->quirks = 0;
567 	host->quirks2 = 0;
568 	host->irq = irq;
569 
570 	/* Setup quirks for the controller */
571 	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
572 	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
573 	if (drv_data) {
574 		host->quirks |= drv_data->sdhci_quirks;
575 		sc->no_divider = drv_data->no_divider;
576 	}
577 
578 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
579 
580 	/* we currently see overruns on errors, so disable the SDMA
581 	 * support as well. */
582 	host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
583 
584 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
585 
586 	/* It seems we do not get an DATA transfer complete on non-busy
587 	 * transfers, not sure if this is a problem with this specific
588 	 * SDHCI block, or a missing configuration that needs to be set. */
589 	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
590 
591 	/* This host supports the Auto CMD12 */
592 	host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
593 
594 	/* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
595 	host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
596 
597 	if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
598 	    pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
599 		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
600 
601 	if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
602 		host->mmc->caps = MMC_CAP_NONREMOVABLE;
603 
604 	switch (pdata->max_width) {
605 	case 8:
606 		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
607 		fallthrough;
608 	case 4:
609 		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
610 		break;
611 	}
612 
613 	if (pdata->pm_caps)
614 		host->mmc->pm_caps |= pdata->pm_caps;
615 
616 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
617 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
618 
619 	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
620 	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
621 
622 	/*
623 	 * If controller does not have internal clock divider,
624 	 * we can use overriding functions instead of default.
625 	 */
626 	if (sc->no_divider) {
627 		sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
628 		sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
629 		sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
630 	}
631 
632 	/* It supports additional host capabilities if needed */
633 	if (pdata->host_caps)
634 		host->mmc->caps |= pdata->host_caps;
635 
636 	if (pdata->host_caps2)
637 		host->mmc->caps2 |= pdata->host_caps2;
638 
639 	pm_runtime_enable(&pdev->dev);
640 	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
641 	pm_runtime_use_autosuspend(&pdev->dev);
642 	pm_suspend_ignore_children(&pdev->dev, 1);
643 
644 	ret = mmc_of_parse(host->mmc);
645 	if (ret)
646 		goto err_req_regs;
647 
648 	ret = sdhci_add_host(host);
649 	if (ret)
650 		goto err_req_regs;
651 
652 #ifdef CONFIG_PM
653 	if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
654 		clk_disable_unprepare(sc->clk_io);
655 #endif
656 	return 0;
657 
658  err_req_regs:
659 	pm_runtime_disable(&pdev->dev);
660 
661  err_no_busclks:
662 	clk_disable_unprepare(sc->clk_io);
663 
664  err_pdata_io_clk:
665 	sdhci_free_host(host);
666 
667 	return ret;
668 }
669 
670 static void sdhci_s3c_remove(struct platform_device *pdev)
671 {
672 	struct sdhci_host *host =  platform_get_drvdata(pdev);
673 	struct sdhci_s3c *sc = sdhci_priv(host);
674 
675 	if (sc->ext_cd_irq)
676 		free_irq(sc->ext_cd_irq, sc);
677 
678 #ifdef CONFIG_PM
679 	if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
680 		clk_prepare_enable(sc->clk_io);
681 #endif
682 	sdhci_remove_host(host, 1);
683 
684 	pm_runtime_dont_use_autosuspend(&pdev->dev);
685 	pm_runtime_disable(&pdev->dev);
686 
687 	clk_disable_unprepare(sc->clk_io);
688 
689 	sdhci_free_host(host);
690 }
691 
692 #ifdef CONFIG_PM_SLEEP
693 static int sdhci_s3c_suspend(struct device *dev)
694 {
695 	struct sdhci_host *host = dev_get_drvdata(dev);
696 
697 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
698 		mmc_retune_needed(host->mmc);
699 
700 	return sdhci_suspend_host(host);
701 }
702 
703 static int sdhci_s3c_resume(struct device *dev)
704 {
705 	struct sdhci_host *host = dev_get_drvdata(dev);
706 
707 	return sdhci_resume_host(host);
708 }
709 #endif
710 
711 #ifdef CONFIG_PM
712 static int sdhci_s3c_runtime_suspend(struct device *dev)
713 {
714 	struct sdhci_host *host = dev_get_drvdata(dev);
715 	struct sdhci_s3c *ourhost = to_s3c(host);
716 	struct clk *busclk = ourhost->clk_io;
717 	int ret;
718 
719 	ret = sdhci_runtime_suspend_host(host);
720 
721 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
722 		mmc_retune_needed(host->mmc);
723 
724 	if (ourhost->cur_clk >= 0)
725 		clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
726 	clk_disable_unprepare(busclk);
727 	return ret;
728 }
729 
730 static int sdhci_s3c_runtime_resume(struct device *dev)
731 {
732 	struct sdhci_host *host = dev_get_drvdata(dev);
733 	struct sdhci_s3c *ourhost = to_s3c(host);
734 	struct clk *busclk = ourhost->clk_io;
735 	int ret;
736 
737 	clk_prepare_enable(busclk);
738 	if (ourhost->cur_clk >= 0)
739 		clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
740 	ret = sdhci_runtime_resume_host(host, 0);
741 	return ret;
742 }
743 #endif
744 
745 static const struct dev_pm_ops sdhci_s3c_pmops = {
746 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
747 	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
748 			   NULL)
749 };
750 
751 static const struct platform_device_id sdhci_s3c_driver_ids[] = {
752 	{
753 		.name		= "s3c-sdhci",
754 		.driver_data	= (kernel_ulong_t)NULL,
755 	},
756 	{ }
757 };
758 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
759 
760 #ifdef CONFIG_OF
761 static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
762 	.no_divider = true,
763 };
764 
765 static const struct of_device_id sdhci_s3c_dt_match[] = {
766 	{ .compatible = "samsung,s3c6410-sdhci", },
767 	{ .compatible = "samsung,exynos4210-sdhci",
768 		.data = &exynos4_sdhci_drv_data },
769 	{},
770 };
771 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
772 #endif
773 
774 static struct platform_driver sdhci_s3c_driver = {
775 	.probe		= sdhci_s3c_probe,
776 	.remove_new	= sdhci_s3c_remove,
777 	.id_table	= sdhci_s3c_driver_ids,
778 	.driver		= {
779 		.name	= "s3c-sdhci",
780 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
781 		.of_match_table = of_match_ptr(sdhci_s3c_dt_match),
782 		.pm	= &sdhci_s3c_pmops,
783 	},
784 };
785 
786 module_platform_driver(sdhci_s3c_driver);
787 
788 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
789 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
790 MODULE_LICENSE("GPL v2");
791