10d1bb41aSBen Dooks /* linux/drivers/mmc/host/sdhci-s3c.c 20d1bb41aSBen Dooks * 30d1bb41aSBen Dooks * Copyright 2008 Openmoko Inc. 40d1bb41aSBen Dooks * Copyright 2008 Simtec Electronics 50d1bb41aSBen Dooks * Ben Dooks <ben@simtec.co.uk> 60d1bb41aSBen Dooks * http://armlinux.simtec.co.uk/ 70d1bb41aSBen Dooks * 80d1bb41aSBen Dooks * SDHCI (HSMMC) support for Samsung SoC 90d1bb41aSBen Dooks * 100d1bb41aSBen Dooks * This program is free software; you can redistribute it and/or modify 110d1bb41aSBen Dooks * it under the terms of the GNU General Public License version 2 as 120d1bb41aSBen Dooks * published by the Free Software Foundation. 130d1bb41aSBen Dooks */ 140d1bb41aSBen Dooks 150d1bb41aSBen Dooks #include <linux/delay.h> 160d1bb41aSBen Dooks #include <linux/dma-mapping.h> 170d1bb41aSBen Dooks #include <linux/platform_device.h> 18cc014f3eSArnd Bergmann #include <linux/platform_data/mmc-sdhci-s3c.h> 195a0e3ad6STejun Heo #include <linux/slab.h> 200d1bb41aSBen Dooks #include <linux/clk.h> 210d1bb41aSBen Dooks #include <linux/io.h> 2217866e14SMarek Szyprowski #include <linux/gpio.h> 2355156d24SMark Brown #include <linux/module.h> 24d5e9c02cSMark Brown #include <linux/of.h> 25d5e9c02cSMark Brown #include <linux/of_gpio.h> 26d5e9c02cSMark Brown #include <linux/pm.h> 279f4e8151SMark Brown #include <linux/pm_runtime.h> 280d1bb41aSBen Dooks 290d1bb41aSBen Dooks #include <linux/mmc/host.h> 300d1bb41aSBen Dooks 31cc014f3eSArnd Bergmann #include "sdhci-s3c-regs.h" 320d1bb41aSBen Dooks #include "sdhci.h" 330d1bb41aSBen Dooks 340d1bb41aSBen Dooks #define MAX_BUS_CLK (4) 350d1bb41aSBen Dooks 360d1bb41aSBen Dooks /** 370d1bb41aSBen Dooks * struct sdhci_s3c - S3C SDHCI instance 380d1bb41aSBen Dooks * @host: The SDHCI host created 390d1bb41aSBen Dooks * @pdev: The platform device we where created from. 400d1bb41aSBen Dooks * @ioarea: The resource created when we claimed the IO area. 410d1bb41aSBen Dooks * @pdata: The platform data for this controller. 420d1bb41aSBen Dooks * @cur_clk: The index of the current bus clock. 430d1bb41aSBen Dooks * @clk_io: The clock for the internal bus interface. 440d1bb41aSBen Dooks * @clk_bus: The clocks that are available for the SD/MMC bus clock. 450d1bb41aSBen Dooks */ 460d1bb41aSBen Dooks struct sdhci_s3c { 470d1bb41aSBen Dooks struct sdhci_host *host; 480d1bb41aSBen Dooks struct platform_device *pdev; 490d1bb41aSBen Dooks struct resource *ioarea; 500d1bb41aSBen Dooks struct s3c_sdhci_platdata *pdata; 513ac147faSTomasz Figa int cur_clk; 5217866e14SMarek Szyprowski int ext_cd_irq; 5317866e14SMarek Szyprowski int ext_cd_gpio; 540d1bb41aSBen Dooks 550d1bb41aSBen Dooks struct clk *clk_io; 560d1bb41aSBen Dooks struct clk *clk_bus[MAX_BUS_CLK]; 576eb28bdcSTomasz Figa unsigned long clk_rates[MAX_BUS_CLK]; 581771059cSRussell King 591771059cSRussell King bool no_divider; 600d1bb41aSBen Dooks }; 610d1bb41aSBen Dooks 623119936aSThomas Abraham /** 633119936aSThomas Abraham * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data 643119936aSThomas Abraham * @sdhci_quirks: sdhci host specific quirks. 653119936aSThomas Abraham * 663119936aSThomas Abraham * Specifies platform specific configuration of sdhci controller. 673119936aSThomas Abraham * Note: A structure for driver specific platform data is used for future 683119936aSThomas Abraham * expansion of its usage. 693119936aSThomas Abraham */ 703119936aSThomas Abraham struct sdhci_s3c_drv_data { 713119936aSThomas Abraham unsigned int sdhci_quirks; 721771059cSRussell King bool no_divider; 733119936aSThomas Abraham }; 743119936aSThomas Abraham 750d1bb41aSBen Dooks static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) 760d1bb41aSBen Dooks { 770d1bb41aSBen Dooks return sdhci_priv(host); 780d1bb41aSBen Dooks } 790d1bb41aSBen Dooks 800d1bb41aSBen Dooks /** 810d1bb41aSBen Dooks * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. 820d1bb41aSBen Dooks * @host: The SDHCI host instance. 830d1bb41aSBen Dooks * 840d1bb41aSBen Dooks * Callback to return the maximum clock rate acheivable by the controller. 850d1bb41aSBen Dooks */ 860d1bb41aSBen Dooks static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) 870d1bb41aSBen Dooks { 880d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host); 89222a13c5STomasz Figa unsigned long rate, max = 0; 90222a13c5STomasz Figa int src; 910d1bb41aSBen Dooks 92222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 93222a13c5STomasz Figa rate = ourhost->clk_rates[src]; 940d1bb41aSBen Dooks if (rate > max) 950d1bb41aSBen Dooks max = rate; 960d1bb41aSBen Dooks } 970d1bb41aSBen Dooks 980d1bb41aSBen Dooks return max; 990d1bb41aSBen Dooks } 1000d1bb41aSBen Dooks 1010d1bb41aSBen Dooks /** 1020d1bb41aSBen Dooks * sdhci_s3c_consider_clock - consider one the bus clocks for current setting 1030d1bb41aSBen Dooks * @ourhost: Our SDHCI instance. 1040d1bb41aSBen Dooks * @src: The source clock index. 1050d1bb41aSBen Dooks * @wanted: The clock frequency wanted. 1060d1bb41aSBen Dooks */ 1070d1bb41aSBen Dooks static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, 1080d1bb41aSBen Dooks unsigned int src, 1090d1bb41aSBen Dooks unsigned int wanted) 1100d1bb41aSBen Dooks { 1110d1bb41aSBen Dooks unsigned long rate; 1120d1bb41aSBen Dooks struct clk *clksrc = ourhost->clk_bus[src]; 1138880a4a5STomasz Figa int shift; 1140d1bb41aSBen Dooks 1158f4b78d9STomasz Figa if (IS_ERR(clksrc)) 1160d1bb41aSBen Dooks return UINT_MAX; 1170d1bb41aSBen Dooks 118253e0a7cSJeongbae Seo /* 1193119936aSThomas Abraham * If controller uses a non-standard clock division, find the best clock 1203119936aSThomas Abraham * speed possible with selected clock source and skip the division. 121253e0a7cSJeongbae Seo */ 1221771059cSRussell King if (ourhost->no_divider) { 123253e0a7cSJeongbae Seo rate = clk_round_rate(clksrc, wanted); 124253e0a7cSJeongbae Seo return wanted - rate; 125253e0a7cSJeongbae Seo } 126253e0a7cSJeongbae Seo 1276eb28bdcSTomasz Figa rate = ourhost->clk_rates[src]; 1280d1bb41aSBen Dooks 12922003000STomasz Figa for (shift = 0; shift <= 8; ++shift) { 1308880a4a5STomasz Figa if ((rate >> shift) <= wanted) 1310d1bb41aSBen Dooks break; 1320d1bb41aSBen Dooks } 1330d1bb41aSBen Dooks 13422003000STomasz Figa if (shift > 8) { 13522003000STomasz Figa dev_dbg(&ourhost->pdev->dev, 13622003000STomasz Figa "clk %d: rate %ld, min rate %lu > wanted %u\n", 13722003000STomasz Figa src, rate, rate / 256, wanted); 13822003000STomasz Figa return UINT_MAX; 13922003000STomasz Figa } 14022003000STomasz Figa 1410d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", 1428880a4a5STomasz Figa src, rate, wanted, rate >> shift); 1430d1bb41aSBen Dooks 1448880a4a5STomasz Figa return wanted - (rate >> shift); 1450d1bb41aSBen Dooks } 1460d1bb41aSBen Dooks 1470d1bb41aSBen Dooks /** 1480d1bb41aSBen Dooks * sdhci_s3c_set_clock - callback on clock change 1490d1bb41aSBen Dooks * @host: The SDHCI host being changed 1500d1bb41aSBen Dooks * @clock: The clock rate being requested. 1510d1bb41aSBen Dooks * 1520d1bb41aSBen Dooks * When the card's clock is going to be changed, look at the new frequency 1530d1bb41aSBen Dooks * and find the best clock source to go with it. 1540d1bb41aSBen Dooks */ 1550d1bb41aSBen Dooks static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) 1560d1bb41aSBen Dooks { 1570d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host); 1580d1bb41aSBen Dooks unsigned int best = UINT_MAX; 1590d1bb41aSBen Dooks unsigned int delta; 1600d1bb41aSBen Dooks int best_src = 0; 1610d1bb41aSBen Dooks int src; 1620d1bb41aSBen Dooks u32 ctrl; 1630d1bb41aSBen Dooks 1641650d0c7SRussell King host->mmc->actual_clock = 0; 1651650d0c7SRussell King 1660d1bb41aSBen Dooks /* don't bother if the clock is going off. */ 1671771059cSRussell King if (clock == 0) { 1681771059cSRussell King sdhci_set_clock(host, clock); 1690d1bb41aSBen Dooks return; 1701771059cSRussell King } 1710d1bb41aSBen Dooks 1720d1bb41aSBen Dooks for (src = 0; src < MAX_BUS_CLK; src++) { 1730d1bb41aSBen Dooks delta = sdhci_s3c_consider_clock(ourhost, src, clock); 1740d1bb41aSBen Dooks if (delta < best) { 1750d1bb41aSBen Dooks best = delta; 1760d1bb41aSBen Dooks best_src = src; 1770d1bb41aSBen Dooks } 1780d1bb41aSBen Dooks } 1790d1bb41aSBen Dooks 1800d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev, 1810d1bb41aSBen Dooks "selected source %d, clock %d, delta %d\n", 1820d1bb41aSBen Dooks best_src, clock, best); 1830d1bb41aSBen Dooks 1840d1bb41aSBen Dooks /* select the new clock source */ 1850d1bb41aSBen Dooks if (ourhost->cur_clk != best_src) { 1860d1bb41aSBen Dooks struct clk *clk = ourhost->clk_bus[best_src]; 1870d1bb41aSBen Dooks 1880f310a05SThomas Abraham clk_prepare_enable(clk); 1893ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 1903ac147faSTomasz Figa clk_disable_unprepare( 1913ac147faSTomasz Figa ourhost->clk_bus[ourhost->cur_clk]); 1920d1bb41aSBen Dooks 1930d1bb41aSBen Dooks ourhost->cur_clk = best_src; 1946eb28bdcSTomasz Figa host->max_clk = ourhost->clk_rates[best_src]; 1953ac147faSTomasz Figa } 1963ac147faSTomasz Figa 1973ac147faSTomasz Figa /* turn clock off to card before changing clock source */ 1983ac147faSTomasz Figa writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 1990d1bb41aSBen Dooks 2000d1bb41aSBen Dooks ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 2010d1bb41aSBen Dooks ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 2020d1bb41aSBen Dooks ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 2030d1bb41aSBen Dooks writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 2040d1bb41aSBen Dooks 2056fe47179SThomas Abraham /* reprogram default hardware configuration */ 2066fe47179SThomas Abraham writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, 2076fe47179SThomas Abraham host->ioaddr + S3C64XX_SDHCI_CONTROL4); 2080d1bb41aSBen Dooks 2096fe47179SThomas Abraham ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 2106fe47179SThomas Abraham ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | 2116fe47179SThomas Abraham S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | 2126fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENFBCLKRX | 2136fe47179SThomas Abraham S3C_SDHCI_CTRL2_DFCNT_NONE | 2146fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENCLKOUTHOLD); 2156fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 2160d1bb41aSBen Dooks 2176fe47179SThomas Abraham /* reconfigure the controller for new clock rate */ 2186fe47179SThomas Abraham ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); 2196fe47179SThomas Abraham if (clock < 25 * 1000000) 2206fe47179SThomas Abraham ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); 2216fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); 2221771059cSRussell King 2231771059cSRussell King sdhci_set_clock(host, clock); 2240d1bb41aSBen Dooks } 2250d1bb41aSBen Dooks 226ce5f036bSMarek Szyprowski /** 227ce5f036bSMarek Szyprowski * sdhci_s3c_get_min_clock - callback to get minimal supported clock value 228ce5f036bSMarek Szyprowski * @host: The SDHCI host being queried 229ce5f036bSMarek Szyprowski * 230ce5f036bSMarek Szyprowski * To init mmc host properly a minimal clock value is needed. For high system 231ce5f036bSMarek Szyprowski * bus clock's values the standard formula gives values out of allowed range. 232ce5f036bSMarek Szyprowski * The clock still can be set to lower values, if clock source other then 233ce5f036bSMarek Szyprowski * system bus is selected. 234ce5f036bSMarek Szyprowski */ 235ce5f036bSMarek Szyprowski static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) 236ce5f036bSMarek Szyprowski { 237ce5f036bSMarek Szyprowski struct sdhci_s3c *ourhost = to_s3c(host); 238222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX; 239ce5f036bSMarek Szyprowski int src; 240ce5f036bSMarek Szyprowski 241ce5f036bSMarek Szyprowski for (src = 0; src < MAX_BUS_CLK; src++) { 242222a13c5STomasz Figa rate = ourhost->clk_rates[src] / 256; 243222a13c5STomasz Figa if (!rate) 244ce5f036bSMarek Szyprowski continue; 245222a13c5STomasz Figa if (rate < min) 246222a13c5STomasz Figa min = rate; 247ce5f036bSMarek Szyprowski } 248222a13c5STomasz Figa 249ce5f036bSMarek Szyprowski return min; 250ce5f036bSMarek Szyprowski } 251ce5f036bSMarek Szyprowski 252253e0a7cSJeongbae Seo /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ 253253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) 254253e0a7cSJeongbae Seo { 255253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 256222a13c5STomasz Figa unsigned long rate, max = 0; 257222a13c5STomasz Figa int src; 258253e0a7cSJeongbae Seo 259222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 260222a13c5STomasz Figa struct clk *clk; 261222a13c5STomasz Figa 262222a13c5STomasz Figa clk = ourhost->clk_bus[src]; 263222a13c5STomasz Figa if (IS_ERR(clk)) 264222a13c5STomasz Figa continue; 265222a13c5STomasz Figa 266222a13c5STomasz Figa rate = clk_round_rate(clk, ULONG_MAX); 267222a13c5STomasz Figa if (rate > max) 268222a13c5STomasz Figa max = rate; 269222a13c5STomasz Figa } 270222a13c5STomasz Figa 271222a13c5STomasz Figa return max; 272253e0a7cSJeongbae Seo } 273253e0a7cSJeongbae Seo 274253e0a7cSJeongbae Seo /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ 275253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) 276253e0a7cSJeongbae Seo { 277253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 278222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX; 279222a13c5STomasz Figa int src; 280253e0a7cSJeongbae Seo 281222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 282222a13c5STomasz Figa struct clk *clk; 283222a13c5STomasz Figa 284222a13c5STomasz Figa clk = ourhost->clk_bus[src]; 285222a13c5STomasz Figa if (IS_ERR(clk)) 286222a13c5STomasz Figa continue; 287222a13c5STomasz Figa 288222a13c5STomasz Figa rate = clk_round_rate(clk, 0); 289222a13c5STomasz Figa if (rate < min) 290222a13c5STomasz Figa min = rate; 291222a13c5STomasz Figa } 292222a13c5STomasz Figa 293222a13c5STomasz Figa return min; 294253e0a7cSJeongbae Seo } 295253e0a7cSJeongbae Seo 296253e0a7cSJeongbae Seo /* sdhci_cmu_set_clock - callback on clock change.*/ 297253e0a7cSJeongbae Seo static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) 298253e0a7cSJeongbae Seo { 299253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 3002ad0b249SJingoo Han struct device *dev = &ourhost->pdev->dev; 3013119936aSThomas Abraham unsigned long timeout; 3023119936aSThomas Abraham u16 clk = 0; 303cd0cfdd2SMark Brown int ret; 304253e0a7cSJeongbae Seo 3051650d0c7SRussell King host->mmc->actual_clock = 0; 3061650d0c7SRussell King 3077ef2a5e2SJaehoon Chung /* If the clock is going off, set to 0 at clock control register */ 3087ef2a5e2SJaehoon Chung if (clock == 0) { 3097ef2a5e2SJaehoon Chung sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 310253e0a7cSJeongbae Seo return; 3117ef2a5e2SJaehoon Chung } 312253e0a7cSJeongbae Seo 313253e0a7cSJeongbae Seo sdhci_s3c_set_clock(host, clock); 314253e0a7cSJeongbae Seo 315cd0cfdd2SMark Brown ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); 316cd0cfdd2SMark Brown if (ret != 0) { 317cd0cfdd2SMark Brown dev_err(dev, "%s: failed to set clock rate %uHz\n", 318cd0cfdd2SMark Brown mmc_hostname(host->mmc), clock); 319cd0cfdd2SMark Brown return; 320cd0cfdd2SMark Brown } 321253e0a7cSJeongbae Seo 3223119936aSThomas Abraham clk = SDHCI_CLOCK_INT_EN; 3233119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 3243119936aSThomas Abraham 3253119936aSThomas Abraham /* Wait max 20 ms */ 3263119936aSThomas Abraham timeout = 20; 3273119936aSThomas Abraham while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 3283119936aSThomas Abraham & SDHCI_CLOCK_INT_STABLE)) { 3293119936aSThomas Abraham if (timeout == 0) { 3302ad0b249SJingoo Han dev_err(dev, "%s: Internal clock never stabilised.\n", 3312ad0b249SJingoo Han mmc_hostname(host->mmc)); 3323119936aSThomas Abraham return; 3333119936aSThomas Abraham } 3343119936aSThomas Abraham timeout--; 3353119936aSThomas Abraham mdelay(1); 3363119936aSThomas Abraham } 3373119936aSThomas Abraham 3383119936aSThomas Abraham clk |= SDHCI_CLOCK_CARD_EN; 3393119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 340253e0a7cSJeongbae Seo } 341253e0a7cSJeongbae Seo 342548f07d2SJaehoon Chung /** 3432317f56cSRussell King * sdhci_s3c_set_bus_width - support 8bit buswidth 344548f07d2SJaehoon Chung * @host: The SDHCI host being queried 345548f07d2SJaehoon Chung * @width: MMC_BUS_WIDTH_ macro for the bus width being requested 346548f07d2SJaehoon Chung * 347548f07d2SJaehoon Chung * We have 8-bit width support but is not a v3 controller. 3487bc088d3SSascha Hauer * So we add platform_bus_width() and support 8bit width. 349548f07d2SJaehoon Chung */ 3502317f56cSRussell King static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) 351548f07d2SJaehoon Chung { 352548f07d2SJaehoon Chung u8 ctrl; 353548f07d2SJaehoon Chung 354548f07d2SJaehoon Chung ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 355548f07d2SJaehoon Chung 356548f07d2SJaehoon Chung switch (width) { 357548f07d2SJaehoon Chung case MMC_BUS_WIDTH_8: 358548f07d2SJaehoon Chung ctrl |= SDHCI_CTRL_8BITBUS; 359548f07d2SJaehoon Chung ctrl &= ~SDHCI_CTRL_4BITBUS; 360548f07d2SJaehoon Chung break; 361548f07d2SJaehoon Chung case MMC_BUS_WIDTH_4: 362548f07d2SJaehoon Chung ctrl |= SDHCI_CTRL_4BITBUS; 363548f07d2SJaehoon Chung ctrl &= ~SDHCI_CTRL_8BITBUS; 364548f07d2SJaehoon Chung break; 365548f07d2SJaehoon Chung default: 36649bb1e61SGirish K S ctrl &= ~SDHCI_CTRL_4BITBUS; 36749bb1e61SGirish K S ctrl &= ~SDHCI_CTRL_8BITBUS; 368548f07d2SJaehoon Chung break; 369548f07d2SJaehoon Chung } 370548f07d2SJaehoon Chung 371548f07d2SJaehoon Chung sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 372548f07d2SJaehoon Chung } 373548f07d2SJaehoon Chung 3740d1bb41aSBen Dooks static struct sdhci_ops sdhci_s3c_ops = { 3750d1bb41aSBen Dooks .get_max_clock = sdhci_s3c_get_max_clk, 3760d1bb41aSBen Dooks .set_clock = sdhci_s3c_set_clock, 377ce5f036bSMarek Szyprowski .get_min_clock = sdhci_s3c_get_min_clock, 3782317f56cSRussell King .set_bus_width = sdhci_s3c_set_bus_width, 37903231f9bSRussell King .reset = sdhci_reset, 38096d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 3810d1bb41aSBen Dooks }; 3820d1bb41aSBen Dooks 383cd1b00ebSThomas Abraham #ifdef CONFIG_OF 384c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev, 385cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 386cd1b00ebSThomas Abraham { 387cd1b00ebSThomas Abraham struct device_node *node = dev->of_node; 388cd1b00ebSThomas Abraham u32 max_width; 389cd1b00ebSThomas Abraham 390cd1b00ebSThomas Abraham /* if the bus-width property is not specified, assume width as 1 */ 391cd1b00ebSThomas Abraham if (of_property_read_u32(node, "bus-width", &max_width)) 392cd1b00ebSThomas Abraham max_width = 1; 393cd1b00ebSThomas Abraham pdata->max_width = max_width; 394cd1b00ebSThomas Abraham 395cd1b00ebSThomas Abraham /* get the card detection method */ 396ab5023efSTushar Behera if (of_get_property(node, "broken-cd", NULL)) { 397cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_NONE; 398e19499aeSThomas Abraham return 0; 399cd1b00ebSThomas Abraham } 400cd1b00ebSThomas Abraham 401ab5023efSTushar Behera if (of_get_property(node, "non-removable", NULL)) { 402cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_PERMANENT; 403e19499aeSThomas Abraham return 0; 404cd1b00ebSThomas Abraham } 405cd1b00ebSThomas Abraham 40611bc9381SJaehoon Chung if (of_get_named_gpio(node, "cd-gpios", 0)) 407e19499aeSThomas Abraham return 0; 408cd1b00ebSThomas Abraham 409b96efccbSTomasz Figa /* assuming internal card detect that will be configured by pinctrl */ 410b96efccbSTomasz Figa pdata->cd_type = S3C_SDHCI_CD_INTERNAL; 411cd1b00ebSThomas Abraham return 0; 412cd1b00ebSThomas Abraham } 413cd1b00ebSThomas Abraham #else 414c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev, 415cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 416cd1b00ebSThomas Abraham { 417cd1b00ebSThomas Abraham return -EINVAL; 418cd1b00ebSThomas Abraham } 419cd1b00ebSThomas Abraham #endif 420cd1b00ebSThomas Abraham 421cd1b00ebSThomas Abraham static const struct of_device_id sdhci_s3c_dt_match[]; 422cd1b00ebSThomas Abraham 4233119936aSThomas Abraham static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( 4243119936aSThomas Abraham struct platform_device *pdev) 4253119936aSThomas Abraham { 426cd1b00ebSThomas Abraham #ifdef CONFIG_OF 427cd1b00ebSThomas Abraham if (pdev->dev.of_node) { 428cd1b00ebSThomas Abraham const struct of_device_id *match; 429cd1b00ebSThomas Abraham match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); 430cd1b00ebSThomas Abraham return (struct sdhci_s3c_drv_data *)match->data; 431cd1b00ebSThomas Abraham } 432cd1b00ebSThomas Abraham #endif 4333119936aSThomas Abraham return (struct sdhci_s3c_drv_data *) 4343119936aSThomas Abraham platform_get_device_id(pdev)->driver_data; 4353119936aSThomas Abraham } 4363119936aSThomas Abraham 437c3be1efdSBill Pemberton static int sdhci_s3c_probe(struct platform_device *pdev) 4380d1bb41aSBen Dooks { 4391d4dc338SThomas Abraham struct s3c_sdhci_platdata *pdata; 4403119936aSThomas Abraham struct sdhci_s3c_drv_data *drv_data; 4410d1bb41aSBen Dooks struct device *dev = &pdev->dev; 4420d1bb41aSBen Dooks struct sdhci_host *host; 4430d1bb41aSBen Dooks struct sdhci_s3c *sc; 4440d1bb41aSBen Dooks struct resource *res; 4450d1bb41aSBen Dooks int ret, irq, ptr, clks; 4460d1bb41aSBen Dooks 447cd1b00ebSThomas Abraham if (!pdev->dev.platform_data && !pdev->dev.of_node) { 4480d1bb41aSBen Dooks dev_err(dev, "no device data specified\n"); 4490d1bb41aSBen Dooks return -ENOENT; 4500d1bb41aSBen Dooks } 4510d1bb41aSBen Dooks 4520d1bb41aSBen Dooks irq = platform_get_irq(pdev, 0); 4530d1bb41aSBen Dooks if (irq < 0) { 4540d1bb41aSBen Dooks dev_err(dev, "no irq specified\n"); 4550d1bb41aSBen Dooks return irq; 4560d1bb41aSBen Dooks } 4570d1bb41aSBen Dooks 4580d1bb41aSBen Dooks host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 4590d1bb41aSBen Dooks if (IS_ERR(host)) { 4600d1bb41aSBen Dooks dev_err(dev, "sdhci_alloc_host() failed\n"); 4610d1bb41aSBen Dooks return PTR_ERR(host); 4620d1bb41aSBen Dooks } 463cd1b00ebSThomas Abraham sc = sdhci_priv(host); 4640d1bb41aSBen Dooks 4651d4dc338SThomas Abraham pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 4661d4dc338SThomas Abraham if (!pdata) { 4671d4dc338SThomas Abraham ret = -ENOMEM; 468b1b8fea9STomasz Figa goto err_pdata_io_clk; 4691d4dc338SThomas Abraham } 470cd1b00ebSThomas Abraham 471cd1b00ebSThomas Abraham if (pdev->dev.of_node) { 472cd1b00ebSThomas Abraham ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); 473cd1b00ebSThomas Abraham if (ret) 474b1b8fea9STomasz Figa goto err_pdata_io_clk; 475cd1b00ebSThomas Abraham } else { 4761d4dc338SThomas Abraham memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 477cd1b00ebSThomas Abraham sc->ext_cd_gpio = -1; /* invalid gpio number */ 478cd1b00ebSThomas Abraham } 4791d4dc338SThomas Abraham 4803119936aSThomas Abraham drv_data = sdhci_s3c_get_driver_data(pdev); 4810d1bb41aSBen Dooks 4820d1bb41aSBen Dooks sc->host = host; 4830d1bb41aSBen Dooks sc->pdev = pdev; 4840d1bb41aSBen Dooks sc->pdata = pdata; 4853ac147faSTomasz Figa sc->cur_clk = -1; 4860d1bb41aSBen Dooks 4870d1bb41aSBen Dooks platform_set_drvdata(pdev, host); 4880d1bb41aSBen Dooks 4893aaf7ba7SJingoo Han sc->clk_io = devm_clk_get(dev, "hsmmc"); 4900d1bb41aSBen Dooks if (IS_ERR(sc->clk_io)) { 4910d1bb41aSBen Dooks dev_err(dev, "failed to get io clock\n"); 4920d1bb41aSBen Dooks ret = PTR_ERR(sc->clk_io); 493b1b8fea9STomasz Figa goto err_pdata_io_clk; 4940d1bb41aSBen Dooks } 4950d1bb41aSBen Dooks 4960d1bb41aSBen Dooks /* enable the local io clock and keep it running for the moment. */ 4970f310a05SThomas Abraham clk_prepare_enable(sc->clk_io); 4980d1bb41aSBen Dooks 4990d1bb41aSBen Dooks for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 5004346b6d9SRajeshwari Shinde char name[14]; 5010d1bb41aSBen Dooks 5024346b6d9SRajeshwari Shinde snprintf(name, 14, "mmc_busclk.%d", ptr); 5038f4b78d9STomasz Figa sc->clk_bus[ptr] = devm_clk_get(dev, name); 5048f4b78d9STomasz Figa if (IS_ERR(sc->clk_bus[ptr])) 5050d1bb41aSBen Dooks continue; 5060d1bb41aSBen Dooks 5070d1bb41aSBen Dooks clks++; 5086eb28bdcSTomasz Figa sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); 5096eb28bdcSTomasz Figa 5100d1bb41aSBen Dooks dev_info(dev, "clock source %d: %s (%ld Hz)\n", 5116eb28bdcSTomasz Figa ptr, name, sc->clk_rates[ptr]); 5120d1bb41aSBen Dooks } 5130d1bb41aSBen Dooks 5140d1bb41aSBen Dooks if (clks == 0) { 5150d1bb41aSBen Dooks dev_err(dev, "failed to find any bus clocks\n"); 5160d1bb41aSBen Dooks ret = -ENOENT; 5170d1bb41aSBen Dooks goto err_no_busclks; 5180d1bb41aSBen Dooks } 5190d1bb41aSBen Dooks 5209bda6da7SJulia Lawall res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 521a3e2cd7fSThierry Reding host->ioaddr = devm_ioremap_resource(&pdev->dev, res); 522a3e2cd7fSThierry Reding if (IS_ERR(host->ioaddr)) { 523a3e2cd7fSThierry Reding ret = PTR_ERR(host->ioaddr); 5240d1bb41aSBen Dooks goto err_req_regs; 5250d1bb41aSBen Dooks } 5260d1bb41aSBen Dooks 5270d1bb41aSBen Dooks /* Ensure we have minimal gpio selected CMD/CLK/Detect */ 5280d1bb41aSBen Dooks if (pdata->cfg_gpio) 5290d1bb41aSBen Dooks pdata->cfg_gpio(pdev, pdata->max_width); 5300d1bb41aSBen Dooks 5310d1bb41aSBen Dooks host->hw_name = "samsung-hsmmc"; 5320d1bb41aSBen Dooks host->ops = &sdhci_s3c_ops; 5330d1bb41aSBen Dooks host->quirks = 0; 534285e244fSJaehoon Chung host->quirks2 = 0; 5350d1bb41aSBen Dooks host->irq = irq; 5360d1bb41aSBen Dooks 5370d1bb41aSBen Dooks /* Setup quirks for the controller */ 538b2e75effSThomas Abraham host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; 539a1d56460SMarek Szyprowski host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 5401771059cSRussell King if (drv_data) { 5413119936aSThomas Abraham host->quirks |= drv_data->sdhci_quirks; 5421771059cSRussell King sc->no_divider = drv_data->no_divider; 5431771059cSRussell King } 5440d1bb41aSBen Dooks 5450d1bb41aSBen Dooks #ifndef CONFIG_MMC_SDHCI_S3C_DMA 5460d1bb41aSBen Dooks 5470d1bb41aSBen Dooks /* we currently see overruns on errors, so disable the SDMA 5480d1bb41aSBen Dooks * support as well. */ 5490d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_BROKEN_DMA; 5500d1bb41aSBen Dooks 5510d1bb41aSBen Dooks #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ 5520d1bb41aSBen Dooks 5530d1bb41aSBen Dooks /* It seems we do not get an DATA transfer complete on non-busy 5540d1bb41aSBen Dooks * transfers, not sure if this is a problem with this specific 5550d1bb41aSBen Dooks * SDHCI block, or a missing configuration that needs to be set. */ 5560d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; 5570d1bb41aSBen Dooks 558732f0e31SKyungmin Park /* This host supports the Auto CMD12 */ 559732f0e31SKyungmin Park host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 560732f0e31SKyungmin Park 5617199e2b6SJaehoon Chung /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ 5627199e2b6SJaehoon Chung host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; 5637199e2b6SJaehoon Chung 56417866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_NONE || 56517866e14SMarek Szyprowski pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 56617866e14SMarek Szyprowski host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 56717866e14SMarek Szyprowski 56817866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 56917866e14SMarek Szyprowski host->mmc->caps = MMC_CAP_NONREMOVABLE; 57017866e14SMarek Szyprowski 5710d22c770SThomas Abraham switch (pdata->max_width) { 5720d22c770SThomas Abraham case 8: 5730d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_8_BIT_DATA; 5740d22c770SThomas Abraham case 4: 5750d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_4_BIT_DATA; 5760d22c770SThomas Abraham break; 5770d22c770SThomas Abraham } 5780d22c770SThomas Abraham 579fa1773ccSSangwook Lee if (pdata->pm_caps) 580fa1773ccSSangwook Lee host->mmc->pm_caps |= pdata->pm_caps; 581fa1773ccSSangwook Lee 5820d1bb41aSBen Dooks host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | 5830d1bb41aSBen Dooks SDHCI_QUIRK_32BIT_DMA_SIZE); 5840d1bb41aSBen Dooks 5853fe42e07SHyuk Lee /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 5863fe42e07SHyuk Lee host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 5873fe42e07SHyuk Lee 588253e0a7cSJeongbae Seo /* 589253e0a7cSJeongbae Seo * If controller does not have internal clock divider, 590253e0a7cSJeongbae Seo * we can use overriding functions instead of default. 591253e0a7cSJeongbae Seo */ 5921771059cSRussell King if (sc->no_divider) { 593253e0a7cSJeongbae Seo sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 594253e0a7cSJeongbae Seo sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 595253e0a7cSJeongbae Seo sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 596253e0a7cSJeongbae Seo } 597253e0a7cSJeongbae Seo 598b3824f2cSJeongbae Seo /* It supports additional host capabilities if needed */ 599b3824f2cSJeongbae Seo if (pdata->host_caps) 600b3824f2cSJeongbae Seo host->mmc->caps |= pdata->host_caps; 601b3824f2cSJeongbae Seo 602c1c4b66dSJaehoon Chung if (pdata->host_caps2) 603c1c4b66dSJaehoon Chung host->mmc->caps2 |= pdata->host_caps2; 604c1c4b66dSJaehoon Chung 6059f4e8151SMark Brown pm_runtime_enable(&pdev->dev); 6069f4e8151SMark Brown pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 6079f4e8151SMark Brown pm_runtime_use_autosuspend(&pdev->dev); 6089f4e8151SMark Brown pm_suspend_ignore_children(&pdev->dev, 1); 6099f4e8151SMark Brown 610f8e3260cSUlf Hansson ret = mmc_of_parse(host->mmc); 611f8e3260cSUlf Hansson if (ret) 612f8e3260cSUlf Hansson goto err_req_regs; 61311bc9381SJaehoon Chung 6140d1bb41aSBen Dooks ret = sdhci_add_host(host); 6150d1bb41aSBen Dooks if (ret) { 6160d1bb41aSBen Dooks dev_err(dev, "sdhci_add_host() failed\n"); 6179bda6da7SJulia Lawall goto err_req_regs; 6180d1bb41aSBen Dooks } 6190d1bb41aSBen Dooks 620162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 6210aa55c23SSeungwon Jeon if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 6220f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6232abeb5c5SChander Kashyap #endif 6240d1bb41aSBen Dooks return 0; 6250d1bb41aSBen Dooks 6260d1bb41aSBen Dooks err_req_regs: 627221414dbSBartlomiej Zolnierkiewicz pm_runtime_disable(&pdev->dev); 628221414dbSBartlomiej Zolnierkiewicz 6290d1bb41aSBen Dooks err_no_busclks: 6300f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6310d1bb41aSBen Dooks 632b1b8fea9STomasz Figa err_pdata_io_clk: 6330d1bb41aSBen Dooks sdhci_free_host(host); 6340d1bb41aSBen Dooks 6350d1bb41aSBen Dooks return ret; 6360d1bb41aSBen Dooks } 6370d1bb41aSBen Dooks 6386e0ee714SBill Pemberton static int sdhci_s3c_remove(struct platform_device *pdev) 6390d1bb41aSBen Dooks { 6409d51a6b2SMarek Szyprowski struct sdhci_host *host = platform_get_drvdata(pdev); 6419d51a6b2SMarek Szyprowski struct sdhci_s3c *sc = sdhci_priv(host); 64217866e14SMarek Szyprowski 64317866e14SMarek Szyprowski if (sc->ext_cd_irq) 64417866e14SMarek Szyprowski free_irq(sc->ext_cd_irq, sc); 64517866e14SMarek Szyprowski 646162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 64711bc9381SJaehoon Chung if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 6480f310a05SThomas Abraham clk_prepare_enable(sc->clk_io); 6492abeb5c5SChander Kashyap #endif 6509d51a6b2SMarek Szyprowski sdhci_remove_host(host, 1); 6519d51a6b2SMarek Szyprowski 652387a8cbdSChander Kashyap pm_runtime_dont_use_autosuspend(&pdev->dev); 6539f4e8151SMark Brown pm_runtime_disable(&pdev->dev); 6549f4e8151SMark Brown 6550f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6569d51a6b2SMarek Szyprowski 6579d51a6b2SMarek Szyprowski sdhci_free_host(host); 6589d51a6b2SMarek Szyprowski 6590d1bb41aSBen Dooks return 0; 6600d1bb41aSBen Dooks } 6610d1bb41aSBen Dooks 662d5e9c02cSMark Brown #ifdef CONFIG_PM_SLEEP 66329495aa0SManuel Lauss static int sdhci_s3c_suspend(struct device *dev) 6640d1bb41aSBen Dooks { 66529495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev); 6660d1bb41aSBen Dooks 66729495aa0SManuel Lauss return sdhci_suspend_host(host); 6680d1bb41aSBen Dooks } 6690d1bb41aSBen Dooks 67029495aa0SManuel Lauss static int sdhci_s3c_resume(struct device *dev) 6710d1bb41aSBen Dooks { 67229495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev); 6730d1bb41aSBen Dooks 67465d13516SWonil Choi return sdhci_resume_host(host); 6750d1bb41aSBen Dooks } 676d5e9c02cSMark Brown #endif 6770d1bb41aSBen Dooks 678162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 6799f4e8151SMark Brown static int sdhci_s3c_runtime_suspend(struct device *dev) 6809f4e8151SMark Brown { 6819f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev); 6822abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host); 6832abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io; 6842abeb5c5SChander Kashyap int ret; 6859f4e8151SMark Brown 6862abeb5c5SChander Kashyap ret = sdhci_runtime_suspend_host(host); 6872abeb5c5SChander Kashyap 6883ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 6890f310a05SThomas Abraham clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 6900f310a05SThomas Abraham clk_disable_unprepare(busclk); 6912abeb5c5SChander Kashyap return ret; 6929f4e8151SMark Brown } 6939f4e8151SMark Brown 6949f4e8151SMark Brown static int sdhci_s3c_runtime_resume(struct device *dev) 6959f4e8151SMark Brown { 6969f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev); 6972abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host); 6982abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io; 6992abeb5c5SChander Kashyap int ret; 7009f4e8151SMark Brown 7010f310a05SThomas Abraham clk_prepare_enable(busclk); 7023ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 7030f310a05SThomas Abraham clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); 7042abeb5c5SChander Kashyap ret = sdhci_runtime_resume_host(host); 7052abeb5c5SChander Kashyap return ret; 7069f4e8151SMark Brown } 7079f4e8151SMark Brown #endif 7089f4e8151SMark Brown 709d5e9c02cSMark Brown #ifdef CONFIG_PM 71029495aa0SManuel Lauss static const struct dev_pm_ops sdhci_s3c_pmops = { 711d5e9c02cSMark Brown SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 7129f4e8151SMark Brown SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 7139f4e8151SMark Brown NULL) 71429495aa0SManuel Lauss }; 71529495aa0SManuel Lauss 71629495aa0SManuel Lauss #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) 71729495aa0SManuel Lauss 7180d1bb41aSBen Dooks #else 71929495aa0SManuel Lauss #define SDHCI_S3C_PMOPS NULL 7200d1bb41aSBen Dooks #endif 7210d1bb41aSBen Dooks 7223119936aSThomas Abraham #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 7233119936aSThomas Abraham static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 7241771059cSRussell King .no_divider = true, 7253119936aSThomas Abraham }; 7263119936aSThomas Abraham #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) 7273119936aSThomas Abraham #else 7283119936aSThomas Abraham #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) 7293119936aSThomas Abraham #endif 7303119936aSThomas Abraham 7313119936aSThomas Abraham static struct platform_device_id sdhci_s3c_driver_ids[] = { 7323119936aSThomas Abraham { 7333119936aSThomas Abraham .name = "s3c-sdhci", 7343119936aSThomas Abraham .driver_data = (kernel_ulong_t)NULL, 7353119936aSThomas Abraham }, { 7363119936aSThomas Abraham .name = "exynos4-sdhci", 7373119936aSThomas Abraham .driver_data = EXYNOS4_SDHCI_DRV_DATA, 7383119936aSThomas Abraham }, 7393119936aSThomas Abraham { } 7403119936aSThomas Abraham }; 7413119936aSThomas Abraham MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); 7423119936aSThomas Abraham 743cd1b00ebSThomas Abraham #ifdef CONFIG_OF 744cd1b00ebSThomas Abraham static const struct of_device_id sdhci_s3c_dt_match[] = { 745cd1b00ebSThomas Abraham { .compatible = "samsung,s3c6410-sdhci", }, 746cd1b00ebSThomas Abraham { .compatible = "samsung,exynos4210-sdhci", 747cd1b00ebSThomas Abraham .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, 748cd1b00ebSThomas Abraham {}, 749cd1b00ebSThomas Abraham }; 750cd1b00ebSThomas Abraham MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); 751cd1b00ebSThomas Abraham #endif 752cd1b00ebSThomas Abraham 7530d1bb41aSBen Dooks static struct platform_driver sdhci_s3c_driver = { 7540d1bb41aSBen Dooks .probe = sdhci_s3c_probe, 7550433c143SBill Pemberton .remove = sdhci_s3c_remove, 7563119936aSThomas Abraham .id_table = sdhci_s3c_driver_ids, 7570d1bb41aSBen Dooks .driver = { 7580d1bb41aSBen Dooks .name = "s3c-sdhci", 759cd1b00ebSThomas Abraham .of_match_table = of_match_ptr(sdhci_s3c_dt_match), 76029495aa0SManuel Lauss .pm = SDHCI_S3C_PMOPS, 7610d1bb41aSBen Dooks }, 7620d1bb41aSBen Dooks }; 7630d1bb41aSBen Dooks 764d1f81a64SAxel Lin module_platform_driver(sdhci_s3c_driver); 7650d1bb41aSBen Dooks 7660d1bb41aSBen Dooks MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); 7670d1bb41aSBen Dooks MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 7680d1bb41aSBen Dooks MODULE_LICENSE("GPL v2"); 7690d1bb41aSBen Dooks MODULE_ALIAS("platform:s3c-sdhci"); 770