10d1bb41aSBen Dooks /* linux/drivers/mmc/host/sdhci-s3c.c 20d1bb41aSBen Dooks * 30d1bb41aSBen Dooks * Copyright 2008 Openmoko Inc. 40d1bb41aSBen Dooks * Copyright 2008 Simtec Electronics 50d1bb41aSBen Dooks * Ben Dooks <ben@simtec.co.uk> 60d1bb41aSBen Dooks * http://armlinux.simtec.co.uk/ 70d1bb41aSBen Dooks * 80d1bb41aSBen Dooks * SDHCI (HSMMC) support for Samsung SoC 90d1bb41aSBen Dooks * 100d1bb41aSBen Dooks * This program is free software; you can redistribute it and/or modify 110d1bb41aSBen Dooks * it under the terms of the GNU General Public License version 2 as 120d1bb41aSBen Dooks * published by the Free Software Foundation. 130d1bb41aSBen Dooks */ 140d1bb41aSBen Dooks 15017210d1SPaul Osmialowski #include <linux/spinlock.h> 160d1bb41aSBen Dooks #include <linux/delay.h> 170d1bb41aSBen Dooks #include <linux/dma-mapping.h> 180d1bb41aSBen Dooks #include <linux/platform_device.h> 19cc014f3eSArnd Bergmann #include <linux/platform_data/mmc-sdhci-s3c.h> 205a0e3ad6STejun Heo #include <linux/slab.h> 210d1bb41aSBen Dooks #include <linux/clk.h> 220d1bb41aSBen Dooks #include <linux/io.h> 2317866e14SMarek Szyprowski #include <linux/gpio.h> 2455156d24SMark Brown #include <linux/module.h> 25d5e9c02cSMark Brown #include <linux/of.h> 26d5e9c02cSMark Brown #include <linux/of_gpio.h> 27d5e9c02cSMark Brown #include <linux/pm.h> 289f4e8151SMark Brown #include <linux/pm_runtime.h> 290d1bb41aSBen Dooks 300d1bb41aSBen Dooks #include <linux/mmc/host.h> 310d1bb41aSBen Dooks 32cc014f3eSArnd Bergmann #include "sdhci-s3c-regs.h" 330d1bb41aSBen Dooks #include "sdhci.h" 340d1bb41aSBen Dooks 350d1bb41aSBen Dooks #define MAX_BUS_CLK (4) 360d1bb41aSBen Dooks 370d1bb41aSBen Dooks /** 380d1bb41aSBen Dooks * struct sdhci_s3c - S3C SDHCI instance 390d1bb41aSBen Dooks * @host: The SDHCI host created 400d1bb41aSBen Dooks * @pdev: The platform device we where created from. 410d1bb41aSBen Dooks * @ioarea: The resource created when we claimed the IO area. 420d1bb41aSBen Dooks * @pdata: The platform data for this controller. 430d1bb41aSBen Dooks * @cur_clk: The index of the current bus clock. 440d1bb41aSBen Dooks * @clk_io: The clock for the internal bus interface. 450d1bb41aSBen Dooks * @clk_bus: The clocks that are available for the SD/MMC bus clock. 460d1bb41aSBen Dooks */ 470d1bb41aSBen Dooks struct sdhci_s3c { 480d1bb41aSBen Dooks struct sdhci_host *host; 490d1bb41aSBen Dooks struct platform_device *pdev; 500d1bb41aSBen Dooks struct resource *ioarea; 510d1bb41aSBen Dooks struct s3c_sdhci_platdata *pdata; 523ac147faSTomasz Figa int cur_clk; 5317866e14SMarek Szyprowski int ext_cd_irq; 5417866e14SMarek Szyprowski int ext_cd_gpio; 550d1bb41aSBen Dooks 560d1bb41aSBen Dooks struct clk *clk_io; 570d1bb41aSBen Dooks struct clk *clk_bus[MAX_BUS_CLK]; 586eb28bdcSTomasz Figa unsigned long clk_rates[MAX_BUS_CLK]; 591771059cSRussell King 601771059cSRussell King bool no_divider; 610d1bb41aSBen Dooks }; 620d1bb41aSBen Dooks 633119936aSThomas Abraham /** 643119936aSThomas Abraham * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data 653119936aSThomas Abraham * @sdhci_quirks: sdhci host specific quirks. 663119936aSThomas Abraham * 673119936aSThomas Abraham * Specifies platform specific configuration of sdhci controller. 683119936aSThomas Abraham * Note: A structure for driver specific platform data is used for future 693119936aSThomas Abraham * expansion of its usage. 703119936aSThomas Abraham */ 713119936aSThomas Abraham struct sdhci_s3c_drv_data { 723119936aSThomas Abraham unsigned int sdhci_quirks; 731771059cSRussell King bool no_divider; 743119936aSThomas Abraham }; 753119936aSThomas Abraham 760d1bb41aSBen Dooks static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) 770d1bb41aSBen Dooks { 780d1bb41aSBen Dooks return sdhci_priv(host); 790d1bb41aSBen Dooks } 800d1bb41aSBen Dooks 810d1bb41aSBen Dooks /** 820d1bb41aSBen Dooks * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. 830d1bb41aSBen Dooks * @host: The SDHCI host instance. 840d1bb41aSBen Dooks * 850d1bb41aSBen Dooks * Callback to return the maximum clock rate acheivable by the controller. 860d1bb41aSBen Dooks */ 870d1bb41aSBen Dooks static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) 880d1bb41aSBen Dooks { 890d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host); 90222a13c5STomasz Figa unsigned long rate, max = 0; 91222a13c5STomasz Figa int src; 920d1bb41aSBen Dooks 93222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 94222a13c5STomasz Figa rate = ourhost->clk_rates[src]; 950d1bb41aSBen Dooks if (rate > max) 960d1bb41aSBen Dooks max = rate; 970d1bb41aSBen Dooks } 980d1bb41aSBen Dooks 990d1bb41aSBen Dooks return max; 1000d1bb41aSBen Dooks } 1010d1bb41aSBen Dooks 1020d1bb41aSBen Dooks /** 1030d1bb41aSBen Dooks * sdhci_s3c_consider_clock - consider one the bus clocks for current setting 1040d1bb41aSBen Dooks * @ourhost: Our SDHCI instance. 1050d1bb41aSBen Dooks * @src: The source clock index. 1060d1bb41aSBen Dooks * @wanted: The clock frequency wanted. 1070d1bb41aSBen Dooks */ 1080d1bb41aSBen Dooks static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, 1090d1bb41aSBen Dooks unsigned int src, 1100d1bb41aSBen Dooks unsigned int wanted) 1110d1bb41aSBen Dooks { 1120d1bb41aSBen Dooks unsigned long rate; 1130d1bb41aSBen Dooks struct clk *clksrc = ourhost->clk_bus[src]; 1148880a4a5STomasz Figa int shift; 1150d1bb41aSBen Dooks 1168f4b78d9STomasz Figa if (IS_ERR(clksrc)) 1170d1bb41aSBen Dooks return UINT_MAX; 1180d1bb41aSBen Dooks 119253e0a7cSJeongbae Seo /* 1203119936aSThomas Abraham * If controller uses a non-standard clock division, find the best clock 1213119936aSThomas Abraham * speed possible with selected clock source and skip the division. 122253e0a7cSJeongbae Seo */ 1231771059cSRussell King if (ourhost->no_divider) { 124253e0a7cSJeongbae Seo rate = clk_round_rate(clksrc, wanted); 125253e0a7cSJeongbae Seo return wanted - rate; 126253e0a7cSJeongbae Seo } 127253e0a7cSJeongbae Seo 1286eb28bdcSTomasz Figa rate = ourhost->clk_rates[src]; 1290d1bb41aSBen Dooks 13022003000STomasz Figa for (shift = 0; shift <= 8; ++shift) { 1318880a4a5STomasz Figa if ((rate >> shift) <= wanted) 1320d1bb41aSBen Dooks break; 1330d1bb41aSBen Dooks } 1340d1bb41aSBen Dooks 13522003000STomasz Figa if (shift > 8) { 13622003000STomasz Figa dev_dbg(&ourhost->pdev->dev, 13722003000STomasz Figa "clk %d: rate %ld, min rate %lu > wanted %u\n", 13822003000STomasz Figa src, rate, rate / 256, wanted); 13922003000STomasz Figa return UINT_MAX; 14022003000STomasz Figa } 14122003000STomasz Figa 1420d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", 1438880a4a5STomasz Figa src, rate, wanted, rate >> shift); 1440d1bb41aSBen Dooks 1458880a4a5STomasz Figa return wanted - (rate >> shift); 1460d1bb41aSBen Dooks } 1470d1bb41aSBen Dooks 1480d1bb41aSBen Dooks /** 1490d1bb41aSBen Dooks * sdhci_s3c_set_clock - callback on clock change 1500d1bb41aSBen Dooks * @host: The SDHCI host being changed 1510d1bb41aSBen Dooks * @clock: The clock rate being requested. 1520d1bb41aSBen Dooks * 1530d1bb41aSBen Dooks * When the card's clock is going to be changed, look at the new frequency 1540d1bb41aSBen Dooks * and find the best clock source to go with it. 1550d1bb41aSBen Dooks */ 1560d1bb41aSBen Dooks static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) 1570d1bb41aSBen Dooks { 1580d1bb41aSBen Dooks struct sdhci_s3c *ourhost = to_s3c(host); 1590d1bb41aSBen Dooks unsigned int best = UINT_MAX; 1600d1bb41aSBen Dooks unsigned int delta; 1610d1bb41aSBen Dooks int best_src = 0; 1620d1bb41aSBen Dooks int src; 1630d1bb41aSBen Dooks u32 ctrl; 1640d1bb41aSBen Dooks 1651650d0c7SRussell King host->mmc->actual_clock = 0; 1661650d0c7SRussell King 1670d1bb41aSBen Dooks /* don't bother if the clock is going off. */ 1681771059cSRussell King if (clock == 0) { 1691771059cSRussell King sdhci_set_clock(host, clock); 1700d1bb41aSBen Dooks return; 1711771059cSRussell King } 1720d1bb41aSBen Dooks 1730d1bb41aSBen Dooks for (src = 0; src < MAX_BUS_CLK; src++) { 1740d1bb41aSBen Dooks delta = sdhci_s3c_consider_clock(ourhost, src, clock); 1750d1bb41aSBen Dooks if (delta < best) { 1760d1bb41aSBen Dooks best = delta; 1770d1bb41aSBen Dooks best_src = src; 1780d1bb41aSBen Dooks } 1790d1bb41aSBen Dooks } 1800d1bb41aSBen Dooks 1810d1bb41aSBen Dooks dev_dbg(&ourhost->pdev->dev, 1820d1bb41aSBen Dooks "selected source %d, clock %d, delta %d\n", 1830d1bb41aSBen Dooks best_src, clock, best); 1840d1bb41aSBen Dooks 1850d1bb41aSBen Dooks /* select the new clock source */ 1860d1bb41aSBen Dooks if (ourhost->cur_clk != best_src) { 1870d1bb41aSBen Dooks struct clk *clk = ourhost->clk_bus[best_src]; 1880d1bb41aSBen Dooks 1890f310a05SThomas Abraham clk_prepare_enable(clk); 1903ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 1913ac147faSTomasz Figa clk_disable_unprepare( 1923ac147faSTomasz Figa ourhost->clk_bus[ourhost->cur_clk]); 1930d1bb41aSBen Dooks 1940d1bb41aSBen Dooks ourhost->cur_clk = best_src; 1956eb28bdcSTomasz Figa host->max_clk = ourhost->clk_rates[best_src]; 1963ac147faSTomasz Figa } 1973ac147faSTomasz Figa 1983ac147faSTomasz Figa /* turn clock off to card before changing clock source */ 1993ac147faSTomasz Figa writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 2000d1bb41aSBen Dooks 2010d1bb41aSBen Dooks ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 2020d1bb41aSBen Dooks ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 2030d1bb41aSBen Dooks ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 2040d1bb41aSBen Dooks writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 2050d1bb41aSBen Dooks 2066fe47179SThomas Abraham /* reprogram default hardware configuration */ 2076fe47179SThomas Abraham writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, 2086fe47179SThomas Abraham host->ioaddr + S3C64XX_SDHCI_CONTROL4); 2090d1bb41aSBen Dooks 2106fe47179SThomas Abraham ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 2116fe47179SThomas Abraham ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | 2126fe47179SThomas Abraham S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | 2136fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENFBCLKRX | 2146fe47179SThomas Abraham S3C_SDHCI_CTRL2_DFCNT_NONE | 2156fe47179SThomas Abraham S3C_SDHCI_CTRL2_ENCLKOUTHOLD); 2166fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 2170d1bb41aSBen Dooks 2186fe47179SThomas Abraham /* reconfigure the controller for new clock rate */ 2196fe47179SThomas Abraham ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); 2206fe47179SThomas Abraham if (clock < 25 * 1000000) 2216fe47179SThomas Abraham ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); 2226fe47179SThomas Abraham writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); 2231771059cSRussell King 2241771059cSRussell King sdhci_set_clock(host, clock); 2250d1bb41aSBen Dooks } 2260d1bb41aSBen Dooks 227ce5f036bSMarek Szyprowski /** 228ce5f036bSMarek Szyprowski * sdhci_s3c_get_min_clock - callback to get minimal supported clock value 229ce5f036bSMarek Szyprowski * @host: The SDHCI host being queried 230ce5f036bSMarek Szyprowski * 231ce5f036bSMarek Szyprowski * To init mmc host properly a minimal clock value is needed. For high system 232ce5f036bSMarek Szyprowski * bus clock's values the standard formula gives values out of allowed range. 233ce5f036bSMarek Szyprowski * The clock still can be set to lower values, if clock source other then 234ce5f036bSMarek Szyprowski * system bus is selected. 235ce5f036bSMarek Szyprowski */ 236ce5f036bSMarek Szyprowski static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) 237ce5f036bSMarek Szyprowski { 238ce5f036bSMarek Szyprowski struct sdhci_s3c *ourhost = to_s3c(host); 239222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX; 240ce5f036bSMarek Szyprowski int src; 241ce5f036bSMarek Szyprowski 242ce5f036bSMarek Szyprowski for (src = 0; src < MAX_BUS_CLK; src++) { 243222a13c5STomasz Figa rate = ourhost->clk_rates[src] / 256; 244222a13c5STomasz Figa if (!rate) 245ce5f036bSMarek Szyprowski continue; 246222a13c5STomasz Figa if (rate < min) 247222a13c5STomasz Figa min = rate; 248ce5f036bSMarek Szyprowski } 249222a13c5STomasz Figa 250ce5f036bSMarek Szyprowski return min; 251ce5f036bSMarek Szyprowski } 252ce5f036bSMarek Szyprowski 253253e0a7cSJeongbae Seo /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ 254253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) 255253e0a7cSJeongbae Seo { 256253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 257222a13c5STomasz Figa unsigned long rate, max = 0; 258222a13c5STomasz Figa int src; 259253e0a7cSJeongbae Seo 260222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 261222a13c5STomasz Figa struct clk *clk; 262222a13c5STomasz Figa 263222a13c5STomasz Figa clk = ourhost->clk_bus[src]; 264222a13c5STomasz Figa if (IS_ERR(clk)) 265222a13c5STomasz Figa continue; 266222a13c5STomasz Figa 267222a13c5STomasz Figa rate = clk_round_rate(clk, ULONG_MAX); 268222a13c5STomasz Figa if (rate > max) 269222a13c5STomasz Figa max = rate; 270222a13c5STomasz Figa } 271222a13c5STomasz Figa 272222a13c5STomasz Figa return max; 273253e0a7cSJeongbae Seo } 274253e0a7cSJeongbae Seo 275253e0a7cSJeongbae Seo /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ 276253e0a7cSJeongbae Seo static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) 277253e0a7cSJeongbae Seo { 278253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 279222a13c5STomasz Figa unsigned long rate, min = ULONG_MAX; 280222a13c5STomasz Figa int src; 281253e0a7cSJeongbae Seo 282222a13c5STomasz Figa for (src = 0; src < MAX_BUS_CLK; src++) { 283222a13c5STomasz Figa struct clk *clk; 284222a13c5STomasz Figa 285222a13c5STomasz Figa clk = ourhost->clk_bus[src]; 286222a13c5STomasz Figa if (IS_ERR(clk)) 287222a13c5STomasz Figa continue; 288222a13c5STomasz Figa 289222a13c5STomasz Figa rate = clk_round_rate(clk, 0); 290222a13c5STomasz Figa if (rate < min) 291222a13c5STomasz Figa min = rate; 292222a13c5STomasz Figa } 293222a13c5STomasz Figa 294222a13c5STomasz Figa return min; 295253e0a7cSJeongbae Seo } 296253e0a7cSJeongbae Seo 297253e0a7cSJeongbae Seo /* sdhci_cmu_set_clock - callback on clock change.*/ 298253e0a7cSJeongbae Seo static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) 299253e0a7cSJeongbae Seo { 300253e0a7cSJeongbae Seo struct sdhci_s3c *ourhost = to_s3c(host); 3012ad0b249SJingoo Han struct device *dev = &ourhost->pdev->dev; 3023119936aSThomas Abraham unsigned long timeout; 3033119936aSThomas Abraham u16 clk = 0; 304cd0cfdd2SMark Brown int ret; 305253e0a7cSJeongbae Seo 3061650d0c7SRussell King host->mmc->actual_clock = 0; 3071650d0c7SRussell King 3087ef2a5e2SJaehoon Chung /* If the clock is going off, set to 0 at clock control register */ 3097ef2a5e2SJaehoon Chung if (clock == 0) { 3107ef2a5e2SJaehoon Chung sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 311253e0a7cSJeongbae Seo return; 3127ef2a5e2SJaehoon Chung } 313253e0a7cSJeongbae Seo 314253e0a7cSJeongbae Seo sdhci_s3c_set_clock(host, clock); 315253e0a7cSJeongbae Seo 316017210d1SPaul Osmialowski /* Reset SD Clock Enable */ 317017210d1SPaul Osmialowski clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 318017210d1SPaul Osmialowski clk &= ~SDHCI_CLOCK_CARD_EN; 319017210d1SPaul Osmialowski sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 320017210d1SPaul Osmialowski 321017210d1SPaul Osmialowski spin_unlock_irq(&host->lock); 322cd0cfdd2SMark Brown ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); 323017210d1SPaul Osmialowski spin_lock_irq(&host->lock); 324cd0cfdd2SMark Brown if (ret != 0) { 325cd0cfdd2SMark Brown dev_err(dev, "%s: failed to set clock rate %uHz\n", 326cd0cfdd2SMark Brown mmc_hostname(host->mmc), clock); 327cd0cfdd2SMark Brown return; 328cd0cfdd2SMark Brown } 329253e0a7cSJeongbae Seo 3303119936aSThomas Abraham clk = SDHCI_CLOCK_INT_EN; 3313119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 3323119936aSThomas Abraham 3333119936aSThomas Abraham /* Wait max 20 ms */ 3343119936aSThomas Abraham timeout = 20; 3353119936aSThomas Abraham while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 3363119936aSThomas Abraham & SDHCI_CLOCK_INT_STABLE)) { 3373119936aSThomas Abraham if (timeout == 0) { 3382ad0b249SJingoo Han dev_err(dev, "%s: Internal clock never stabilised.\n", 3392ad0b249SJingoo Han mmc_hostname(host->mmc)); 3403119936aSThomas Abraham return; 3413119936aSThomas Abraham } 3423119936aSThomas Abraham timeout--; 3433119936aSThomas Abraham mdelay(1); 3443119936aSThomas Abraham } 3453119936aSThomas Abraham 3463119936aSThomas Abraham clk |= SDHCI_CLOCK_CARD_EN; 3473119936aSThomas Abraham sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 348253e0a7cSJeongbae Seo } 349253e0a7cSJeongbae Seo 350548f07d2SJaehoon Chung /** 3512317f56cSRussell King * sdhci_s3c_set_bus_width - support 8bit buswidth 352548f07d2SJaehoon Chung * @host: The SDHCI host being queried 353548f07d2SJaehoon Chung * @width: MMC_BUS_WIDTH_ macro for the bus width being requested 354548f07d2SJaehoon Chung * 355548f07d2SJaehoon Chung * We have 8-bit width support but is not a v3 controller. 3567bc088d3SSascha Hauer * So we add platform_bus_width() and support 8bit width. 357548f07d2SJaehoon Chung */ 3582317f56cSRussell King static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) 359548f07d2SJaehoon Chung { 360548f07d2SJaehoon Chung u8 ctrl; 361548f07d2SJaehoon Chung 362548f07d2SJaehoon Chung ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 363548f07d2SJaehoon Chung 364548f07d2SJaehoon Chung switch (width) { 365548f07d2SJaehoon Chung case MMC_BUS_WIDTH_8: 366548f07d2SJaehoon Chung ctrl |= SDHCI_CTRL_8BITBUS; 367548f07d2SJaehoon Chung ctrl &= ~SDHCI_CTRL_4BITBUS; 368548f07d2SJaehoon Chung break; 369548f07d2SJaehoon Chung case MMC_BUS_WIDTH_4: 370548f07d2SJaehoon Chung ctrl |= SDHCI_CTRL_4BITBUS; 371548f07d2SJaehoon Chung ctrl &= ~SDHCI_CTRL_8BITBUS; 372548f07d2SJaehoon Chung break; 373548f07d2SJaehoon Chung default: 37449bb1e61SGirish K S ctrl &= ~SDHCI_CTRL_4BITBUS; 37549bb1e61SGirish K S ctrl &= ~SDHCI_CTRL_8BITBUS; 376548f07d2SJaehoon Chung break; 377548f07d2SJaehoon Chung } 378548f07d2SJaehoon Chung 379548f07d2SJaehoon Chung sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 380548f07d2SJaehoon Chung } 381548f07d2SJaehoon Chung 3820d1bb41aSBen Dooks static struct sdhci_ops sdhci_s3c_ops = { 3830d1bb41aSBen Dooks .get_max_clock = sdhci_s3c_get_max_clk, 3840d1bb41aSBen Dooks .set_clock = sdhci_s3c_set_clock, 385ce5f036bSMarek Szyprowski .get_min_clock = sdhci_s3c_get_min_clock, 3862317f56cSRussell King .set_bus_width = sdhci_s3c_set_bus_width, 38703231f9bSRussell King .reset = sdhci_reset, 38896d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 3890d1bb41aSBen Dooks }; 3900d1bb41aSBen Dooks 391cd1b00ebSThomas Abraham #ifdef CONFIG_OF 392c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev, 393cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 394cd1b00ebSThomas Abraham { 395cd1b00ebSThomas Abraham struct device_node *node = dev->of_node; 396cd1b00ebSThomas Abraham u32 max_width; 397cd1b00ebSThomas Abraham 398cd1b00ebSThomas Abraham /* if the bus-width property is not specified, assume width as 1 */ 399cd1b00ebSThomas Abraham if (of_property_read_u32(node, "bus-width", &max_width)) 400cd1b00ebSThomas Abraham max_width = 1; 401cd1b00ebSThomas Abraham pdata->max_width = max_width; 402cd1b00ebSThomas Abraham 403cd1b00ebSThomas Abraham /* get the card detection method */ 404ab5023efSTushar Behera if (of_get_property(node, "broken-cd", NULL)) { 405cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_NONE; 406e19499aeSThomas Abraham return 0; 407cd1b00ebSThomas Abraham } 408cd1b00ebSThomas Abraham 409ab5023efSTushar Behera if (of_get_property(node, "non-removable", NULL)) { 410cd1b00ebSThomas Abraham pdata->cd_type = S3C_SDHCI_CD_PERMANENT; 411e19499aeSThomas Abraham return 0; 412cd1b00ebSThomas Abraham } 413cd1b00ebSThomas Abraham 41411bc9381SJaehoon Chung if (of_get_named_gpio(node, "cd-gpios", 0)) 415e19499aeSThomas Abraham return 0; 416cd1b00ebSThomas Abraham 417b96efccbSTomasz Figa /* assuming internal card detect that will be configured by pinctrl */ 418b96efccbSTomasz Figa pdata->cd_type = S3C_SDHCI_CD_INTERNAL; 419cd1b00ebSThomas Abraham return 0; 420cd1b00ebSThomas Abraham } 421cd1b00ebSThomas Abraham #else 422c3be1efdSBill Pemberton static int sdhci_s3c_parse_dt(struct device *dev, 423cd1b00ebSThomas Abraham struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 424cd1b00ebSThomas Abraham { 425cd1b00ebSThomas Abraham return -EINVAL; 426cd1b00ebSThomas Abraham } 427cd1b00ebSThomas Abraham #endif 428cd1b00ebSThomas Abraham 429cd1b00ebSThomas Abraham static const struct of_device_id sdhci_s3c_dt_match[]; 430cd1b00ebSThomas Abraham 4313119936aSThomas Abraham static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( 4323119936aSThomas Abraham struct platform_device *pdev) 4333119936aSThomas Abraham { 434cd1b00ebSThomas Abraham #ifdef CONFIG_OF 435cd1b00ebSThomas Abraham if (pdev->dev.of_node) { 436cd1b00ebSThomas Abraham const struct of_device_id *match; 437cd1b00ebSThomas Abraham match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); 438cd1b00ebSThomas Abraham return (struct sdhci_s3c_drv_data *)match->data; 439cd1b00ebSThomas Abraham } 440cd1b00ebSThomas Abraham #endif 4413119936aSThomas Abraham return (struct sdhci_s3c_drv_data *) 4423119936aSThomas Abraham platform_get_device_id(pdev)->driver_data; 4433119936aSThomas Abraham } 4443119936aSThomas Abraham 445c3be1efdSBill Pemberton static int sdhci_s3c_probe(struct platform_device *pdev) 4460d1bb41aSBen Dooks { 4471d4dc338SThomas Abraham struct s3c_sdhci_platdata *pdata; 4483119936aSThomas Abraham struct sdhci_s3c_drv_data *drv_data; 4490d1bb41aSBen Dooks struct device *dev = &pdev->dev; 4500d1bb41aSBen Dooks struct sdhci_host *host; 4510d1bb41aSBen Dooks struct sdhci_s3c *sc; 4520d1bb41aSBen Dooks struct resource *res; 4530d1bb41aSBen Dooks int ret, irq, ptr, clks; 4540d1bb41aSBen Dooks 455cd1b00ebSThomas Abraham if (!pdev->dev.platform_data && !pdev->dev.of_node) { 4560d1bb41aSBen Dooks dev_err(dev, "no device data specified\n"); 4570d1bb41aSBen Dooks return -ENOENT; 4580d1bb41aSBen Dooks } 4590d1bb41aSBen Dooks 4600d1bb41aSBen Dooks irq = platform_get_irq(pdev, 0); 4610d1bb41aSBen Dooks if (irq < 0) { 4620d1bb41aSBen Dooks dev_err(dev, "no irq specified\n"); 4630d1bb41aSBen Dooks return irq; 4640d1bb41aSBen Dooks } 4650d1bb41aSBen Dooks 4660d1bb41aSBen Dooks host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 4670d1bb41aSBen Dooks if (IS_ERR(host)) { 4680d1bb41aSBen Dooks dev_err(dev, "sdhci_alloc_host() failed\n"); 4690d1bb41aSBen Dooks return PTR_ERR(host); 4700d1bb41aSBen Dooks } 471cd1b00ebSThomas Abraham sc = sdhci_priv(host); 4720d1bb41aSBen Dooks 4731d4dc338SThomas Abraham pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 4741d4dc338SThomas Abraham if (!pdata) { 4751d4dc338SThomas Abraham ret = -ENOMEM; 476b1b8fea9STomasz Figa goto err_pdata_io_clk; 4771d4dc338SThomas Abraham } 478cd1b00ebSThomas Abraham 479cd1b00ebSThomas Abraham if (pdev->dev.of_node) { 480cd1b00ebSThomas Abraham ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); 481cd1b00ebSThomas Abraham if (ret) 482b1b8fea9STomasz Figa goto err_pdata_io_clk; 483cd1b00ebSThomas Abraham } else { 4841d4dc338SThomas Abraham memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 485cd1b00ebSThomas Abraham sc->ext_cd_gpio = -1; /* invalid gpio number */ 486cd1b00ebSThomas Abraham } 4871d4dc338SThomas Abraham 4883119936aSThomas Abraham drv_data = sdhci_s3c_get_driver_data(pdev); 4890d1bb41aSBen Dooks 4900d1bb41aSBen Dooks sc->host = host; 4910d1bb41aSBen Dooks sc->pdev = pdev; 4920d1bb41aSBen Dooks sc->pdata = pdata; 4933ac147faSTomasz Figa sc->cur_clk = -1; 4940d1bb41aSBen Dooks 4950d1bb41aSBen Dooks platform_set_drvdata(pdev, host); 4960d1bb41aSBen Dooks 4973aaf7ba7SJingoo Han sc->clk_io = devm_clk_get(dev, "hsmmc"); 4980d1bb41aSBen Dooks if (IS_ERR(sc->clk_io)) { 4990d1bb41aSBen Dooks dev_err(dev, "failed to get io clock\n"); 5000d1bb41aSBen Dooks ret = PTR_ERR(sc->clk_io); 501b1b8fea9STomasz Figa goto err_pdata_io_clk; 5020d1bb41aSBen Dooks } 5030d1bb41aSBen Dooks 5040d1bb41aSBen Dooks /* enable the local io clock and keep it running for the moment. */ 5050f310a05SThomas Abraham clk_prepare_enable(sc->clk_io); 5060d1bb41aSBen Dooks 5070d1bb41aSBen Dooks for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 5084346b6d9SRajeshwari Shinde char name[14]; 5090d1bb41aSBen Dooks 5104346b6d9SRajeshwari Shinde snprintf(name, 14, "mmc_busclk.%d", ptr); 5118f4b78d9STomasz Figa sc->clk_bus[ptr] = devm_clk_get(dev, name); 5128f4b78d9STomasz Figa if (IS_ERR(sc->clk_bus[ptr])) 5130d1bb41aSBen Dooks continue; 5140d1bb41aSBen Dooks 5150d1bb41aSBen Dooks clks++; 5166eb28bdcSTomasz Figa sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); 5176eb28bdcSTomasz Figa 5180d1bb41aSBen Dooks dev_info(dev, "clock source %d: %s (%ld Hz)\n", 5196eb28bdcSTomasz Figa ptr, name, sc->clk_rates[ptr]); 5200d1bb41aSBen Dooks } 5210d1bb41aSBen Dooks 5220d1bb41aSBen Dooks if (clks == 0) { 5230d1bb41aSBen Dooks dev_err(dev, "failed to find any bus clocks\n"); 5240d1bb41aSBen Dooks ret = -ENOENT; 5250d1bb41aSBen Dooks goto err_no_busclks; 5260d1bb41aSBen Dooks } 5270d1bb41aSBen Dooks 5289bda6da7SJulia Lawall res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 529a3e2cd7fSThierry Reding host->ioaddr = devm_ioremap_resource(&pdev->dev, res); 530a3e2cd7fSThierry Reding if (IS_ERR(host->ioaddr)) { 531a3e2cd7fSThierry Reding ret = PTR_ERR(host->ioaddr); 5320d1bb41aSBen Dooks goto err_req_regs; 5330d1bb41aSBen Dooks } 5340d1bb41aSBen Dooks 5350d1bb41aSBen Dooks /* Ensure we have minimal gpio selected CMD/CLK/Detect */ 5360d1bb41aSBen Dooks if (pdata->cfg_gpio) 5370d1bb41aSBen Dooks pdata->cfg_gpio(pdev, pdata->max_width); 5380d1bb41aSBen Dooks 5390d1bb41aSBen Dooks host->hw_name = "samsung-hsmmc"; 5400d1bb41aSBen Dooks host->ops = &sdhci_s3c_ops; 5410d1bb41aSBen Dooks host->quirks = 0; 542285e244fSJaehoon Chung host->quirks2 = 0; 5430d1bb41aSBen Dooks host->irq = irq; 5440d1bb41aSBen Dooks 5450d1bb41aSBen Dooks /* Setup quirks for the controller */ 546b2e75effSThomas Abraham host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; 547a1d56460SMarek Szyprowski host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 5481771059cSRussell King if (drv_data) { 5493119936aSThomas Abraham host->quirks |= drv_data->sdhci_quirks; 5501771059cSRussell King sc->no_divider = drv_data->no_divider; 5511771059cSRussell King } 5520d1bb41aSBen Dooks 5530d1bb41aSBen Dooks #ifndef CONFIG_MMC_SDHCI_S3C_DMA 5540d1bb41aSBen Dooks 5550d1bb41aSBen Dooks /* we currently see overruns on errors, so disable the SDMA 5560d1bb41aSBen Dooks * support as well. */ 5570d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_BROKEN_DMA; 5580d1bb41aSBen Dooks 5590d1bb41aSBen Dooks #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ 5600d1bb41aSBen Dooks 5610d1bb41aSBen Dooks /* It seems we do not get an DATA transfer complete on non-busy 5620d1bb41aSBen Dooks * transfers, not sure if this is a problem with this specific 5630d1bb41aSBen Dooks * SDHCI block, or a missing configuration that needs to be set. */ 5640d1bb41aSBen Dooks host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; 5650d1bb41aSBen Dooks 566732f0e31SKyungmin Park /* This host supports the Auto CMD12 */ 567732f0e31SKyungmin Park host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 568732f0e31SKyungmin Park 5697199e2b6SJaehoon Chung /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ 5707199e2b6SJaehoon Chung host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; 5717199e2b6SJaehoon Chung 57217866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_NONE || 57317866e14SMarek Szyprowski pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 57417866e14SMarek Szyprowski host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 57517866e14SMarek Szyprowski 57617866e14SMarek Szyprowski if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 57717866e14SMarek Szyprowski host->mmc->caps = MMC_CAP_NONREMOVABLE; 57817866e14SMarek Szyprowski 5790d22c770SThomas Abraham switch (pdata->max_width) { 5800d22c770SThomas Abraham case 8: 5810d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_8_BIT_DATA; 5820d22c770SThomas Abraham case 4: 5830d22c770SThomas Abraham host->mmc->caps |= MMC_CAP_4_BIT_DATA; 5840d22c770SThomas Abraham break; 5850d22c770SThomas Abraham } 5860d22c770SThomas Abraham 587fa1773ccSSangwook Lee if (pdata->pm_caps) 588fa1773ccSSangwook Lee host->mmc->pm_caps |= pdata->pm_caps; 589fa1773ccSSangwook Lee 5900d1bb41aSBen Dooks host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | 5910d1bb41aSBen Dooks SDHCI_QUIRK_32BIT_DMA_SIZE); 5920d1bb41aSBen Dooks 5933fe42e07SHyuk Lee /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 5943fe42e07SHyuk Lee host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 5953fe42e07SHyuk Lee 596253e0a7cSJeongbae Seo /* 597253e0a7cSJeongbae Seo * If controller does not have internal clock divider, 598253e0a7cSJeongbae Seo * we can use overriding functions instead of default. 599253e0a7cSJeongbae Seo */ 6001771059cSRussell King if (sc->no_divider) { 601253e0a7cSJeongbae Seo sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 602253e0a7cSJeongbae Seo sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 603253e0a7cSJeongbae Seo sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 604253e0a7cSJeongbae Seo } 605253e0a7cSJeongbae Seo 606b3824f2cSJeongbae Seo /* It supports additional host capabilities if needed */ 607b3824f2cSJeongbae Seo if (pdata->host_caps) 608b3824f2cSJeongbae Seo host->mmc->caps |= pdata->host_caps; 609b3824f2cSJeongbae Seo 610c1c4b66dSJaehoon Chung if (pdata->host_caps2) 611c1c4b66dSJaehoon Chung host->mmc->caps2 |= pdata->host_caps2; 612c1c4b66dSJaehoon Chung 6139f4e8151SMark Brown pm_runtime_enable(&pdev->dev); 6149f4e8151SMark Brown pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 6159f4e8151SMark Brown pm_runtime_use_autosuspend(&pdev->dev); 6169f4e8151SMark Brown pm_suspend_ignore_children(&pdev->dev, 1); 6179f4e8151SMark Brown 618f8e3260cSUlf Hansson ret = mmc_of_parse(host->mmc); 619f8e3260cSUlf Hansson if (ret) 620f8e3260cSUlf Hansson goto err_req_regs; 62111bc9381SJaehoon Chung 6220d1bb41aSBen Dooks ret = sdhci_add_host(host); 6230d1bb41aSBen Dooks if (ret) { 6240d1bb41aSBen Dooks dev_err(dev, "sdhci_add_host() failed\n"); 6259bda6da7SJulia Lawall goto err_req_regs; 6260d1bb41aSBen Dooks } 6270d1bb41aSBen Dooks 628162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 6290aa55c23SSeungwon Jeon if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 6300f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6312abeb5c5SChander Kashyap #endif 6320d1bb41aSBen Dooks return 0; 6330d1bb41aSBen Dooks 6340d1bb41aSBen Dooks err_req_regs: 635221414dbSBartlomiej Zolnierkiewicz pm_runtime_disable(&pdev->dev); 636221414dbSBartlomiej Zolnierkiewicz 6370d1bb41aSBen Dooks err_no_busclks: 6380f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6390d1bb41aSBen Dooks 640b1b8fea9STomasz Figa err_pdata_io_clk: 6410d1bb41aSBen Dooks sdhci_free_host(host); 6420d1bb41aSBen Dooks 6430d1bb41aSBen Dooks return ret; 6440d1bb41aSBen Dooks } 6450d1bb41aSBen Dooks 6466e0ee714SBill Pemberton static int sdhci_s3c_remove(struct platform_device *pdev) 6470d1bb41aSBen Dooks { 6489d51a6b2SMarek Szyprowski struct sdhci_host *host = platform_get_drvdata(pdev); 6499d51a6b2SMarek Szyprowski struct sdhci_s3c *sc = sdhci_priv(host); 65017866e14SMarek Szyprowski 65117866e14SMarek Szyprowski if (sc->ext_cd_irq) 65217866e14SMarek Szyprowski free_irq(sc->ext_cd_irq, sc); 65317866e14SMarek Szyprowski 654162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 65511bc9381SJaehoon Chung if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 6560f310a05SThomas Abraham clk_prepare_enable(sc->clk_io); 6572abeb5c5SChander Kashyap #endif 6589d51a6b2SMarek Szyprowski sdhci_remove_host(host, 1); 6599d51a6b2SMarek Szyprowski 660387a8cbdSChander Kashyap pm_runtime_dont_use_autosuspend(&pdev->dev); 6619f4e8151SMark Brown pm_runtime_disable(&pdev->dev); 6629f4e8151SMark Brown 6630f310a05SThomas Abraham clk_disable_unprepare(sc->clk_io); 6649d51a6b2SMarek Szyprowski 6659d51a6b2SMarek Szyprowski sdhci_free_host(host); 6669d51a6b2SMarek Szyprowski 6670d1bb41aSBen Dooks return 0; 6680d1bb41aSBen Dooks } 6690d1bb41aSBen Dooks 670d5e9c02cSMark Brown #ifdef CONFIG_PM_SLEEP 67129495aa0SManuel Lauss static int sdhci_s3c_suspend(struct device *dev) 6720d1bb41aSBen Dooks { 67329495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev); 6740d1bb41aSBen Dooks 67529495aa0SManuel Lauss return sdhci_suspend_host(host); 6760d1bb41aSBen Dooks } 6770d1bb41aSBen Dooks 67829495aa0SManuel Lauss static int sdhci_s3c_resume(struct device *dev) 6790d1bb41aSBen Dooks { 68029495aa0SManuel Lauss struct sdhci_host *host = dev_get_drvdata(dev); 6810d1bb41aSBen Dooks 68265d13516SWonil Choi return sdhci_resume_host(host); 6830d1bb41aSBen Dooks } 684d5e9c02cSMark Brown #endif 6850d1bb41aSBen Dooks 686162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 6879f4e8151SMark Brown static int sdhci_s3c_runtime_suspend(struct device *dev) 6889f4e8151SMark Brown { 6899f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev); 6902abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host); 6912abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io; 6922abeb5c5SChander Kashyap int ret; 6939f4e8151SMark Brown 6942abeb5c5SChander Kashyap ret = sdhci_runtime_suspend_host(host); 6952abeb5c5SChander Kashyap 6963ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 6970f310a05SThomas Abraham clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 6980f310a05SThomas Abraham clk_disable_unprepare(busclk); 6992abeb5c5SChander Kashyap return ret; 7009f4e8151SMark Brown } 7019f4e8151SMark Brown 7029f4e8151SMark Brown static int sdhci_s3c_runtime_resume(struct device *dev) 7039f4e8151SMark Brown { 7049f4e8151SMark Brown struct sdhci_host *host = dev_get_drvdata(dev); 7052abeb5c5SChander Kashyap struct sdhci_s3c *ourhost = to_s3c(host); 7062abeb5c5SChander Kashyap struct clk *busclk = ourhost->clk_io; 7072abeb5c5SChander Kashyap int ret; 7089f4e8151SMark Brown 7090f310a05SThomas Abraham clk_prepare_enable(busclk); 7103ac147faSTomasz Figa if (ourhost->cur_clk >= 0) 7110f310a05SThomas Abraham clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); 7122abeb5c5SChander Kashyap ret = sdhci_runtime_resume_host(host); 7132abeb5c5SChander Kashyap return ret; 7149f4e8151SMark Brown } 7159f4e8151SMark Brown #endif 7169f4e8151SMark Brown 71729495aa0SManuel Lauss static const struct dev_pm_ops sdhci_s3c_pmops = { 718d5e9c02cSMark Brown SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 7199f4e8151SMark Brown SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 7209f4e8151SMark Brown NULL) 72129495aa0SManuel Lauss }; 72229495aa0SManuel Lauss 7233119936aSThomas Abraham #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 7243119936aSThomas Abraham static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 7251771059cSRussell King .no_divider = true, 7263119936aSThomas Abraham }; 7273119936aSThomas Abraham #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) 7283119936aSThomas Abraham #else 7293119936aSThomas Abraham #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) 7303119936aSThomas Abraham #endif 7313119936aSThomas Abraham 7324d0aa491SKrzysztof Kozlowski static const struct platform_device_id sdhci_s3c_driver_ids[] = { 7333119936aSThomas Abraham { 7343119936aSThomas Abraham .name = "s3c-sdhci", 7353119936aSThomas Abraham .driver_data = (kernel_ulong_t)NULL, 7363119936aSThomas Abraham }, { 7373119936aSThomas Abraham .name = "exynos4-sdhci", 7383119936aSThomas Abraham .driver_data = EXYNOS4_SDHCI_DRV_DATA, 7393119936aSThomas Abraham }, 7403119936aSThomas Abraham { } 7413119936aSThomas Abraham }; 7423119936aSThomas Abraham MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); 7433119936aSThomas Abraham 744cd1b00ebSThomas Abraham #ifdef CONFIG_OF 745cd1b00ebSThomas Abraham static const struct of_device_id sdhci_s3c_dt_match[] = { 746cd1b00ebSThomas Abraham { .compatible = "samsung,s3c6410-sdhci", }, 747cd1b00ebSThomas Abraham { .compatible = "samsung,exynos4210-sdhci", 748cd1b00ebSThomas Abraham .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, 749cd1b00ebSThomas Abraham {}, 750cd1b00ebSThomas Abraham }; 751cd1b00ebSThomas Abraham MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); 752cd1b00ebSThomas Abraham #endif 753cd1b00ebSThomas Abraham 7540d1bb41aSBen Dooks static struct platform_driver sdhci_s3c_driver = { 7550d1bb41aSBen Dooks .probe = sdhci_s3c_probe, 7560433c143SBill Pemberton .remove = sdhci_s3c_remove, 7573119936aSThomas Abraham .id_table = sdhci_s3c_driver_ids, 7580d1bb41aSBen Dooks .driver = { 7590d1bb41aSBen Dooks .name = "s3c-sdhci", 760cd1b00ebSThomas Abraham .of_match_table = of_match_ptr(sdhci_s3c_dt_match), 7616b3a194bSUlf Hansson .pm = &sdhci_s3c_pmops, 7620d1bb41aSBen Dooks }, 7630d1bb41aSBen Dooks }; 7640d1bb41aSBen Dooks 765d1f81a64SAxel Lin module_platform_driver(sdhci_s3c_driver); 7660d1bb41aSBen Dooks 7670d1bb41aSBen Dooks MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); 7680d1bb41aSBen Dooks MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 7690d1bb41aSBen Dooks MODULE_LICENSE("GPL v2"); 7700d1bb41aSBen Dooks MODULE_ALIAS("platform:s3c-sdhci"); 771