1 /* 2 * Copyright (C) 2010 Marvell International Ltd. 3 * Zhangfei Gao <zhangfei.gao@marvell.com> 4 * Kevin Wang <dwang4@marvell.com> 5 * Mingwei Wang <mwwang@marvell.com> 6 * Philip Rakity <prakity@marvell.com> 7 * Mark Brown <markb@marvell.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/platform_data/pxa_sdhci.h> 29 #include <linux/slab.h> 30 #include <linux/delay.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_gpio.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/mbus.h> 38 39 #include "sdhci.h" 40 #include "sdhci-pltfm.h" 41 42 #define PXAV3_RPM_DELAY_MS 50 43 44 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A 45 #define SDCLK_SEL 0x100 46 #define SDCLK_DELAY_SHIFT 9 47 #define SDCLK_DELAY_MASK 0x1f 48 49 #define SD_CFG_FIFO_PARAM 0x100 50 #define SDCFG_GEN_PAD_CLK_ON (1<<6) 51 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF 52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 53 54 #define SD_SPI_MODE 0x108 55 #define SD_CE_ATA_1 0x10C 56 57 #define SD_CE_ATA_2 0x10E 58 #define SDCE_MISC_INT (1<<2) 59 #define SDCE_MISC_INT_EN (1<<1) 60 61 struct sdhci_pxa { 62 struct clk *clk_core; 63 struct clk *clk_io; 64 u8 power_mode; 65 }; 66 67 /* 68 * These registers are relative to the second register region, for the 69 * MBus bridge. 70 */ 71 #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3)) 72 #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3)) 73 #define SDHCI_MAX_WIN_NUM 8 74 75 static int mv_conf_mbus_windows(struct platform_device *pdev, 76 const struct mbus_dram_target_info *dram) 77 { 78 int i; 79 void __iomem *regs; 80 struct resource *res; 81 82 if (!dram) { 83 dev_err(&pdev->dev, "no mbus dram info\n"); 84 return -EINVAL; 85 } 86 87 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 88 if (!res) { 89 dev_err(&pdev->dev, "cannot get mbus registers\n"); 90 return -EINVAL; 91 } 92 93 regs = ioremap(res->start, resource_size(res)); 94 if (!regs) { 95 dev_err(&pdev->dev, "cannot map mbus registers\n"); 96 return -ENOMEM; 97 } 98 99 for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) { 100 writel(0, regs + SDHCI_WINDOW_CTRL(i)); 101 writel(0, regs + SDHCI_WINDOW_BASE(i)); 102 } 103 104 for (i = 0; i < dram->num_cs; i++) { 105 const struct mbus_dram_window *cs = dram->cs + i; 106 107 /* Write size, attributes and target id to control register */ 108 writel(((cs->size - 1) & 0xffff0000) | 109 (cs->mbus_attr << 8) | 110 (dram->mbus_dram_target_id << 4) | 1, 111 regs + SDHCI_WINDOW_CTRL(i)); 112 /* Write base address to base register */ 113 writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); 114 } 115 116 iounmap(regs); 117 118 return 0; 119 } 120 121 static int armada_38x_quirks(struct platform_device *pdev, 122 struct sdhci_host *host) 123 { 124 struct device_node *np = pdev->dev.of_node; 125 126 host->quirks |= SDHCI_QUIRK_MISSING_CAPS; 127 /* 128 * According to erratum 'FE-2946959' both SDR50 and DDR50 129 * modes require specific clock adjustments in SDIO3 130 * Configuration register, if the adjustment is not done, 131 * remove them from the capabilities. 132 */ 133 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 134 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 135 136 /* 137 * According to erratum 'ERR-7878951' Armada 38x SDHCI 138 * controller has different capabilities than the ones shown 139 * in its registers 140 */ 141 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 142 if (of_property_read_bool(np, "no-1-8-v")) { 143 host->caps &= ~SDHCI_CAN_VDD_180; 144 host->mmc->caps &= ~MMC_CAP_1_8V_DDR; 145 } else { 146 host->caps &= ~SDHCI_CAN_VDD_330; 147 } 148 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING); 149 150 return 0; 151 } 152 153 static void pxav3_reset(struct sdhci_host *host, u8 mask) 154 { 155 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 156 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 157 158 sdhci_reset(host, mask); 159 160 if (mask == SDHCI_RESET_ALL) { 161 /* 162 * tune timing of read data/command when crc error happen 163 * no performance impact 164 */ 165 if (pdata && 0 != pdata->clk_delay_cycles) { 166 u16 tmp; 167 168 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 169 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 170 << SDCLK_DELAY_SHIFT; 171 tmp |= SDCLK_SEL; 172 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 173 } 174 } 175 } 176 177 #define MAX_WAIT_COUNT 5 178 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) 179 { 180 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 181 struct sdhci_pxa *pxa = pltfm_host->priv; 182 u16 tmp; 183 int count; 184 185 if (pxa->power_mode == MMC_POWER_UP 186 && power_mode == MMC_POWER_ON) { 187 188 dev_dbg(mmc_dev(host->mmc), 189 "%s: slot->power_mode = %d," 190 "ios->power_mode = %d\n", 191 __func__, 192 pxa->power_mode, 193 power_mode); 194 195 /* set we want notice of when 74 clocks are sent */ 196 tmp = readw(host->ioaddr + SD_CE_ATA_2); 197 tmp |= SDCE_MISC_INT_EN; 198 writew(tmp, host->ioaddr + SD_CE_ATA_2); 199 200 /* start sending the 74 clocks */ 201 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); 202 tmp |= SDCFG_GEN_PAD_CLK_ON; 203 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); 204 205 /* slowest speed is about 100KHz or 10usec per clock */ 206 udelay(740); 207 count = 0; 208 209 while (count++ < MAX_WAIT_COUNT) { 210 if ((readw(host->ioaddr + SD_CE_ATA_2) 211 & SDCE_MISC_INT) == 0) 212 break; 213 udelay(10); 214 } 215 216 if (count == MAX_WAIT_COUNT) 217 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); 218 219 /* clear the interrupt bit if posted */ 220 tmp = readw(host->ioaddr + SD_CE_ATA_2); 221 tmp |= SDCE_MISC_INT; 222 writew(tmp, host->ioaddr + SD_CE_ATA_2); 223 } 224 pxa->power_mode = power_mode; 225 } 226 227 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 228 { 229 u16 ctrl_2; 230 231 /* 232 * Set V18_EN -- UHS modes do not work without this. 233 * does not change signaling voltage 234 */ 235 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 236 237 /* Select Bus Speed Mode for host */ 238 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 239 switch (uhs) { 240 case MMC_TIMING_UHS_SDR12: 241 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 242 break; 243 case MMC_TIMING_UHS_SDR25: 244 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 245 break; 246 case MMC_TIMING_UHS_SDR50: 247 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; 248 break; 249 case MMC_TIMING_UHS_SDR104: 250 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; 251 break; 252 case MMC_TIMING_MMC_DDR52: 253 case MMC_TIMING_UHS_DDR50: 254 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; 255 break; 256 } 257 258 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 259 dev_dbg(mmc_dev(host->mmc), 260 "%s uhs = %d, ctrl_2 = %04X\n", 261 __func__, uhs, ctrl_2); 262 } 263 264 static const struct sdhci_ops pxav3_sdhci_ops = { 265 .set_clock = sdhci_set_clock, 266 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, 267 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 268 .set_bus_width = sdhci_set_bus_width, 269 .reset = pxav3_reset, 270 .set_uhs_signaling = pxav3_set_uhs_signaling, 271 }; 272 273 static struct sdhci_pltfm_data sdhci_pxav3_pdata = { 274 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 275 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 276 | SDHCI_QUIRK_32BIT_ADMA_SIZE 277 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 278 .ops = &pxav3_sdhci_ops, 279 }; 280 281 #ifdef CONFIG_OF 282 static const struct of_device_id sdhci_pxav3_of_match[] = { 283 { 284 .compatible = "mrvl,pxav3-mmc", 285 }, 286 { 287 .compatible = "marvell,armada-380-sdhci", 288 }, 289 {}, 290 }; 291 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); 292 293 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 294 { 295 struct sdhci_pxa_platdata *pdata; 296 struct device_node *np = dev->of_node; 297 u32 clk_delay_cycles; 298 299 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 300 if (!pdata) 301 return NULL; 302 303 if (!of_property_read_u32(np, "mrvl,clk-delay-cycles", 304 &clk_delay_cycles)) 305 pdata->clk_delay_cycles = clk_delay_cycles; 306 307 return pdata; 308 } 309 #else 310 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 311 { 312 return NULL; 313 } 314 #endif 315 316 static int sdhci_pxav3_probe(struct platform_device *pdev) 317 { 318 struct sdhci_pltfm_host *pltfm_host; 319 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 320 struct device *dev = &pdev->dev; 321 struct device_node *np = pdev->dev.of_node; 322 struct sdhci_host *host = NULL; 323 struct sdhci_pxa *pxa = NULL; 324 const struct of_device_id *match; 325 int ret; 326 327 pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL); 328 if (!pxa) 329 return -ENOMEM; 330 331 host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0); 332 if (IS_ERR(host)) 333 return PTR_ERR(host); 334 335 pltfm_host = sdhci_priv(host); 336 pltfm_host->priv = pxa; 337 338 pxa->clk_io = devm_clk_get(dev, "io"); 339 if (IS_ERR(pxa->clk_io)) 340 pxa->clk_io = devm_clk_get(dev, NULL); 341 if (IS_ERR(pxa->clk_io)) { 342 dev_err(dev, "failed to get io clock\n"); 343 ret = PTR_ERR(pxa->clk_io); 344 goto err_clk_get; 345 } 346 pltfm_host->clk = pxa->clk_io; 347 clk_prepare_enable(pxa->clk_io); 348 349 pxa->clk_core = devm_clk_get(dev, "core"); 350 if (!IS_ERR(pxa->clk_core)) 351 clk_prepare_enable(pxa->clk_core); 352 353 /* enable 1/8V DDR capable */ 354 host->mmc->caps |= MMC_CAP_1_8V_DDR; 355 356 if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { 357 ret = armada_38x_quirks(pdev, host); 358 if (ret < 0) 359 goto err_clk_get; 360 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); 361 if (ret < 0) 362 goto err_mbus_win; 363 } 364 365 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); 366 if (match) { 367 ret = mmc_of_parse(host->mmc); 368 if (ret) 369 goto err_of_parse; 370 sdhci_get_of_property(pdev); 371 pdata = pxav3_get_mmc_pdata(dev); 372 } else if (pdata) { 373 /* on-chip device */ 374 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) 375 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 376 377 /* If slot design supports 8 bit data, indicate this to MMC. */ 378 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 379 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 380 381 if (pdata->quirks) 382 host->quirks |= pdata->quirks; 383 if (pdata->quirks2) 384 host->quirks2 |= pdata->quirks2; 385 if (pdata->host_caps) 386 host->mmc->caps |= pdata->host_caps; 387 if (pdata->host_caps2) 388 host->mmc->caps2 |= pdata->host_caps2; 389 if (pdata->pm_caps) 390 host->mmc->pm_caps |= pdata->pm_caps; 391 392 if (gpio_is_valid(pdata->ext_cd_gpio)) { 393 ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, 394 0); 395 if (ret) { 396 dev_err(mmc_dev(host->mmc), 397 "failed to allocate card detect gpio\n"); 398 goto err_cd_req; 399 } 400 } 401 } 402 403 pm_runtime_get_noresume(&pdev->dev); 404 pm_runtime_set_active(&pdev->dev); 405 pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); 406 pm_runtime_use_autosuspend(&pdev->dev); 407 pm_runtime_enable(&pdev->dev); 408 pm_suspend_ignore_children(&pdev->dev, 1); 409 410 ret = sdhci_add_host(host); 411 if (ret) { 412 dev_err(&pdev->dev, "failed to add host\n"); 413 goto err_add_host; 414 } 415 416 platform_set_drvdata(pdev, host); 417 418 if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) { 419 device_init_wakeup(&pdev->dev, 1); 420 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ; 421 } else { 422 device_init_wakeup(&pdev->dev, 0); 423 } 424 425 pm_runtime_put_autosuspend(&pdev->dev); 426 427 return 0; 428 429 err_add_host: 430 pm_runtime_disable(&pdev->dev); 431 pm_runtime_put_noidle(&pdev->dev); 432 err_of_parse: 433 err_cd_req: 434 err_mbus_win: 435 clk_disable_unprepare(pxa->clk_io); 436 clk_disable_unprepare(pxa->clk_core); 437 err_clk_get: 438 sdhci_pltfm_free(pdev); 439 return ret; 440 } 441 442 static int sdhci_pxav3_remove(struct platform_device *pdev) 443 { 444 struct sdhci_host *host = platform_get_drvdata(pdev); 445 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 446 struct sdhci_pxa *pxa = pltfm_host->priv; 447 448 pm_runtime_get_sync(&pdev->dev); 449 pm_runtime_disable(&pdev->dev); 450 pm_runtime_put_noidle(&pdev->dev); 451 452 sdhci_remove_host(host, 1); 453 454 clk_disable_unprepare(pxa->clk_io); 455 clk_disable_unprepare(pxa->clk_core); 456 457 sdhci_pltfm_free(pdev); 458 459 return 0; 460 } 461 462 #ifdef CONFIG_PM_SLEEP 463 static int sdhci_pxav3_suspend(struct device *dev) 464 { 465 int ret; 466 struct sdhci_host *host = dev_get_drvdata(dev); 467 468 pm_runtime_get_sync(dev); 469 ret = sdhci_suspend_host(host); 470 pm_runtime_mark_last_busy(dev); 471 pm_runtime_put_autosuspend(dev); 472 473 return ret; 474 } 475 476 static int sdhci_pxav3_resume(struct device *dev) 477 { 478 int ret; 479 struct sdhci_host *host = dev_get_drvdata(dev); 480 481 pm_runtime_get_sync(dev); 482 ret = sdhci_resume_host(host); 483 pm_runtime_mark_last_busy(dev); 484 pm_runtime_put_autosuspend(dev); 485 486 return ret; 487 } 488 #endif 489 490 #ifdef CONFIG_PM 491 static int sdhci_pxav3_runtime_suspend(struct device *dev) 492 { 493 struct sdhci_host *host = dev_get_drvdata(dev); 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct sdhci_pxa *pxa = pltfm_host->priv; 496 int ret; 497 498 ret = sdhci_runtime_suspend_host(host); 499 if (ret) 500 return ret; 501 502 clk_disable_unprepare(pxa->clk_io); 503 if (!IS_ERR(pxa->clk_core)) 504 clk_disable_unprepare(pxa->clk_core); 505 506 return 0; 507 } 508 509 static int sdhci_pxav3_runtime_resume(struct device *dev) 510 { 511 struct sdhci_host *host = dev_get_drvdata(dev); 512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 513 struct sdhci_pxa *pxa = pltfm_host->priv; 514 515 clk_prepare_enable(pxa->clk_io); 516 if (!IS_ERR(pxa->clk_core)) 517 clk_prepare_enable(pxa->clk_core); 518 519 return sdhci_runtime_resume_host(host); 520 } 521 #endif 522 523 #ifdef CONFIG_PM 524 static const struct dev_pm_ops sdhci_pxav3_pmops = { 525 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) 526 SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, 527 sdhci_pxav3_runtime_resume, NULL) 528 }; 529 530 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) 531 532 #else 533 #define SDHCI_PXAV3_PMOPS NULL 534 #endif 535 536 static struct platform_driver sdhci_pxav3_driver = { 537 .driver = { 538 .name = "sdhci-pxav3", 539 #ifdef CONFIG_OF 540 .of_match_table = sdhci_pxav3_of_match, 541 #endif 542 .pm = SDHCI_PXAV3_PMOPS, 543 }, 544 .probe = sdhci_pxav3_probe, 545 .remove = sdhci_pxav3_remove, 546 }; 547 548 module_platform_driver(sdhci_pxav3_driver); 549 550 MODULE_DESCRIPTION("SDHCI driver for pxav3"); 551 MODULE_AUTHOR("Marvell International Ltd."); 552 MODULE_LICENSE("GPL v2"); 553 554