1 /* 2 * Copyright (C) 2010 Marvell International Ltd. 3 * Zhangfei Gao <zhangfei.gao@marvell.com> 4 * Kevin Wang <dwang4@marvell.com> 5 * Mingwei Wang <mwwang@marvell.com> 6 * Philip Rakity <prakity@marvell.com> 7 * Mark Brown <markb@marvell.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/platform_data/pxa_sdhci.h> 29 #include <linux/slab.h> 30 #include <linux/delay.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_gpio.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 38 #include "sdhci.h" 39 #include "sdhci-pltfm.h" 40 41 #define PXAV3_RPM_DELAY_MS 50 42 43 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A 44 #define SDCLK_SEL 0x100 45 #define SDCLK_DELAY_SHIFT 9 46 #define SDCLK_DELAY_MASK 0x1f 47 48 #define SD_CFG_FIFO_PARAM 0x100 49 #define SDCFG_GEN_PAD_CLK_ON (1<<6) 50 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF 51 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 52 53 #define SD_SPI_MODE 0x108 54 #define SD_CE_ATA_1 0x10C 55 56 #define SD_CE_ATA_2 0x10E 57 #define SDCE_MISC_INT (1<<2) 58 #define SDCE_MISC_INT_EN (1<<1) 59 60 static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask) 61 { 62 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 63 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 64 65 if (mask == SDHCI_RESET_ALL) { 66 /* 67 * tune timing of read data/command when crc error happen 68 * no performance impact 69 */ 70 if (pdata && 0 != pdata->clk_delay_cycles) { 71 u16 tmp; 72 73 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 74 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 75 << SDCLK_DELAY_SHIFT; 76 tmp |= SDCLK_SEL; 77 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 78 } 79 } 80 } 81 82 #define MAX_WAIT_COUNT 5 83 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) 84 { 85 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 86 struct sdhci_pxa *pxa = pltfm_host->priv; 87 u16 tmp; 88 int count; 89 90 if (pxa->power_mode == MMC_POWER_UP 91 && power_mode == MMC_POWER_ON) { 92 93 dev_dbg(mmc_dev(host->mmc), 94 "%s: slot->power_mode = %d," 95 "ios->power_mode = %d\n", 96 __func__, 97 pxa->power_mode, 98 power_mode); 99 100 /* set we want notice of when 74 clocks are sent */ 101 tmp = readw(host->ioaddr + SD_CE_ATA_2); 102 tmp |= SDCE_MISC_INT_EN; 103 writew(tmp, host->ioaddr + SD_CE_ATA_2); 104 105 /* start sending the 74 clocks */ 106 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); 107 tmp |= SDCFG_GEN_PAD_CLK_ON; 108 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); 109 110 /* slowest speed is about 100KHz or 10usec per clock */ 111 udelay(740); 112 count = 0; 113 114 while (count++ < MAX_WAIT_COUNT) { 115 if ((readw(host->ioaddr + SD_CE_ATA_2) 116 & SDCE_MISC_INT) == 0) 117 break; 118 udelay(10); 119 } 120 121 if (count == MAX_WAIT_COUNT) 122 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); 123 124 /* clear the interrupt bit if posted */ 125 tmp = readw(host->ioaddr + SD_CE_ATA_2); 126 tmp |= SDCE_MISC_INT; 127 writew(tmp, host->ioaddr + SD_CE_ATA_2); 128 } 129 pxa->power_mode = power_mode; 130 } 131 132 static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 133 { 134 u16 ctrl_2; 135 136 /* 137 * Set V18_EN -- UHS modes do not work without this. 138 * does not change signaling voltage 139 */ 140 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 141 142 /* Select Bus Speed Mode for host */ 143 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 144 switch (uhs) { 145 case MMC_TIMING_UHS_SDR12: 146 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 147 break; 148 case MMC_TIMING_UHS_SDR25: 149 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 150 break; 151 case MMC_TIMING_UHS_SDR50: 152 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; 153 break; 154 case MMC_TIMING_UHS_SDR104: 155 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; 156 break; 157 case MMC_TIMING_UHS_DDR50: 158 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; 159 break; 160 } 161 162 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 163 dev_dbg(mmc_dev(host->mmc), 164 "%s uhs = %d, ctrl_2 = %04X\n", 165 __func__, uhs, ctrl_2); 166 167 return 0; 168 } 169 170 static struct sdhci_ops pxav3_sdhci_ops = { 171 .platform_reset_exit = pxav3_set_private_registers, 172 .set_uhs_signaling = pxav3_set_uhs_signaling, 173 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, 174 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 175 }; 176 177 #ifdef CONFIG_OF 178 static const struct of_device_id sdhci_pxav3_of_match[] = { 179 { 180 .compatible = "mrvl,pxav3-mmc", 181 }, 182 {}, 183 }; 184 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); 185 186 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 187 { 188 struct sdhci_pxa_platdata *pdata; 189 struct device_node *np = dev->of_node; 190 u32 bus_width; 191 u32 clk_delay_cycles; 192 enum of_gpio_flags gpio_flags; 193 194 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 195 if (!pdata) 196 return NULL; 197 198 if (of_find_property(np, "non-removable", NULL)) 199 pdata->flags |= PXA_FLAG_CARD_PERMANENT; 200 201 of_property_read_u32(np, "bus-width", &bus_width); 202 if (bus_width == 8) 203 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 204 205 of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 206 if (clk_delay_cycles > 0) 207 pdata->clk_delay_cycles = clk_delay_cycles; 208 209 pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags); 210 if (gpio_flags != OF_GPIO_ACTIVE_LOW) 211 pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 212 213 return pdata; 214 } 215 #else 216 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 217 { 218 return NULL; 219 } 220 #endif 221 222 static int sdhci_pxav3_probe(struct platform_device *pdev) 223 { 224 struct sdhci_pltfm_host *pltfm_host; 225 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 226 struct device *dev = &pdev->dev; 227 struct sdhci_host *host = NULL; 228 struct sdhci_pxa *pxa = NULL; 229 const struct of_device_id *match; 230 231 int ret; 232 struct clk *clk; 233 234 pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); 235 if (!pxa) 236 return -ENOMEM; 237 238 host = sdhci_pltfm_init(pdev, NULL); 239 if (IS_ERR(host)) { 240 kfree(pxa); 241 return PTR_ERR(host); 242 } 243 pltfm_host = sdhci_priv(host); 244 pltfm_host->priv = pxa; 245 246 clk = clk_get(dev, NULL); 247 if (IS_ERR(clk)) { 248 dev_err(dev, "failed to get io clock\n"); 249 ret = PTR_ERR(clk); 250 goto err_clk_get; 251 } 252 pltfm_host->clk = clk; 253 clk_prepare_enable(clk); 254 255 host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 256 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 257 | SDHCI_QUIRK_32BIT_ADMA_SIZE 258 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 259 260 /* enable 1/8V DDR capable */ 261 host->mmc->caps |= MMC_CAP_1_8V_DDR; 262 263 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); 264 if (match) 265 pdata = pxav3_get_mmc_pdata(dev); 266 267 if (pdata) { 268 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 269 /* on-chip device */ 270 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 271 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 272 } 273 274 /* If slot design supports 8 bit data, indicate this to MMC. */ 275 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 276 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 277 278 if (pdata->quirks) 279 host->quirks |= pdata->quirks; 280 if (pdata->quirks2) 281 host->quirks2 |= pdata->quirks2; 282 if (pdata->host_caps) 283 host->mmc->caps |= pdata->host_caps; 284 if (pdata->host_caps2) 285 host->mmc->caps2 |= pdata->host_caps2; 286 if (pdata->pm_caps) 287 host->mmc->pm_caps |= pdata->pm_caps; 288 289 if (gpio_is_valid(pdata->ext_cd_gpio)) { 290 ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio); 291 if (ret) { 292 dev_err(mmc_dev(host->mmc), 293 "failed to allocate card detect gpio\n"); 294 goto err_cd_req; 295 } 296 } 297 } 298 299 host->ops = &pxav3_sdhci_ops; 300 301 sdhci_get_of_property(pdev); 302 303 pm_runtime_set_active(&pdev->dev); 304 pm_runtime_enable(&pdev->dev); 305 pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); 306 pm_runtime_use_autosuspend(&pdev->dev); 307 pm_suspend_ignore_children(&pdev->dev, 1); 308 pm_runtime_get_noresume(&pdev->dev); 309 310 ret = sdhci_add_host(host); 311 if (ret) { 312 dev_err(&pdev->dev, "failed to add host\n"); 313 pm_runtime_forbid(&pdev->dev); 314 pm_runtime_disable(&pdev->dev); 315 goto err_add_host; 316 } 317 318 platform_set_drvdata(pdev, host); 319 320 if (pdata->pm_caps & MMC_PM_KEEP_POWER) { 321 device_init_wakeup(&pdev->dev, 1); 322 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ; 323 } else { 324 device_init_wakeup(&pdev->dev, 0); 325 } 326 327 pm_runtime_put_autosuspend(&pdev->dev); 328 329 return 0; 330 331 err_add_host: 332 clk_disable_unprepare(clk); 333 clk_put(clk); 334 err_cd_req: 335 err_clk_get: 336 sdhci_pltfm_free(pdev); 337 kfree(pxa); 338 return ret; 339 } 340 341 static int sdhci_pxav3_remove(struct platform_device *pdev) 342 { 343 struct sdhci_host *host = platform_get_drvdata(pdev); 344 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 345 struct sdhci_pxa *pxa = pltfm_host->priv; 346 347 pm_runtime_get_sync(&pdev->dev); 348 sdhci_remove_host(host, 1); 349 pm_runtime_disable(&pdev->dev); 350 351 clk_disable_unprepare(pltfm_host->clk); 352 clk_put(pltfm_host->clk); 353 354 sdhci_pltfm_free(pdev); 355 kfree(pxa); 356 357 platform_set_drvdata(pdev, NULL); 358 359 return 0; 360 } 361 362 #ifdef CONFIG_PM_SLEEP 363 static int sdhci_pxav3_suspend(struct device *dev) 364 { 365 int ret; 366 struct sdhci_host *host = dev_get_drvdata(dev); 367 368 pm_runtime_get_sync(dev); 369 ret = sdhci_suspend_host(host); 370 pm_runtime_mark_last_busy(dev); 371 pm_runtime_put_autosuspend(dev); 372 373 return ret; 374 } 375 376 static int sdhci_pxav3_resume(struct device *dev) 377 { 378 int ret; 379 struct sdhci_host *host = dev_get_drvdata(dev); 380 381 pm_runtime_get_sync(dev); 382 ret = sdhci_resume_host(host); 383 pm_runtime_mark_last_busy(dev); 384 pm_runtime_put_autosuspend(dev); 385 386 return ret; 387 } 388 #endif 389 390 #ifdef CONFIG_PM_RUNTIME 391 static int sdhci_pxav3_runtime_suspend(struct device *dev) 392 { 393 struct sdhci_host *host = dev_get_drvdata(dev); 394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 395 unsigned long flags; 396 397 if (pltfm_host->clk) { 398 spin_lock_irqsave(&host->lock, flags); 399 host->runtime_suspended = true; 400 spin_unlock_irqrestore(&host->lock, flags); 401 402 clk_disable_unprepare(pltfm_host->clk); 403 } 404 405 return 0; 406 } 407 408 static int sdhci_pxav3_runtime_resume(struct device *dev) 409 { 410 struct sdhci_host *host = dev_get_drvdata(dev); 411 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 412 unsigned long flags; 413 414 if (pltfm_host->clk) { 415 clk_prepare_enable(pltfm_host->clk); 416 417 spin_lock_irqsave(&host->lock, flags); 418 host->runtime_suspended = false; 419 spin_unlock_irqrestore(&host->lock, flags); 420 } 421 422 return 0; 423 } 424 #endif 425 426 #ifdef CONFIG_PM 427 static const struct dev_pm_ops sdhci_pxav3_pmops = { 428 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) 429 SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, 430 sdhci_pxav3_runtime_resume, NULL) 431 }; 432 433 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) 434 435 #else 436 #define SDHCI_PXAV3_PMOPS NULL 437 #endif 438 439 static struct platform_driver sdhci_pxav3_driver = { 440 .driver = { 441 .name = "sdhci-pxav3", 442 #ifdef CONFIG_OF 443 .of_match_table = sdhci_pxav3_of_match, 444 #endif 445 .owner = THIS_MODULE, 446 .pm = SDHCI_PXAV3_PMOPS, 447 }, 448 .probe = sdhci_pxav3_probe, 449 .remove = sdhci_pxav3_remove, 450 }; 451 452 module_platform_driver(sdhci_pxav3_driver); 453 454 MODULE_DESCRIPTION("SDHCI driver for pxav3"); 455 MODULE_AUTHOR("Marvell International Ltd."); 456 MODULE_LICENSE("GPL v2"); 457 458