1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Marvell International Ltd. 4 * Zhangfei Gao <zhangfei.gao@marvell.com> 5 * Kevin Wang <dwang4@marvell.com> 6 * Jun Nie <njun@marvell.com> 7 * Qiming Wu <wuqm@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 */ 10 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/module.h> 16 #include <linux/io.h> 17 #include <linux/mmc/card.h> 18 #include <linux/mmc/host.h> 19 #include <linux/platform_data/pxa_sdhci.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 24 #include "sdhci.h" 25 #include "sdhci-pltfm.h" 26 27 #define SD_FIFO_PARAM 0xe0 28 #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 29 #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 30 #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 31 #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 32 CLK_GATE_ON | CLK_GATE_CTL) 33 34 #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 35 #define SDCLK_SEL_SHIFT 8 36 #define SDCLK_SEL_MASK 0x3 37 #define SDCLK_DELAY_SHIFT 10 38 #define SDCLK_DELAY_MASK 0x3c 39 40 #define SD_CE_ATA_2 0xea 41 #define MMC_CARD 0x1000 42 #define MMC_WIDTH 0x0100 43 44 static void pxav2_reset(struct sdhci_host *host, u8 mask) 45 { 46 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 47 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 48 49 sdhci_reset(host, mask); 50 51 if (mask == SDHCI_RESET_ALL) { 52 u16 tmp = 0; 53 54 /* 55 * tune timing of read data/command when crc error happen 56 * no performance impact 57 */ 58 if (pdata && pdata->clk_delay_sel == 1) { 59 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 60 61 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 62 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 63 << SDCLK_DELAY_SHIFT; 64 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 65 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 66 67 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 68 } 69 70 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { 71 tmp = readw(host->ioaddr + SD_FIFO_PARAM); 72 tmp &= ~CLK_GATE_SETTING_BITS; 73 writew(tmp, host->ioaddr + SD_FIFO_PARAM); 74 } else { 75 tmp = readw(host->ioaddr + SD_FIFO_PARAM); 76 tmp &= ~CLK_GATE_SETTING_BITS; 77 tmp |= CLK_GATE_SETTING_BITS; 78 writew(tmp, host->ioaddr + SD_FIFO_PARAM); 79 } 80 } 81 } 82 83 static u16 pxav1_readw(struct sdhci_host *host, int reg) 84 { 85 /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ 86 if (reg == SDHCI_HOST_VERSION) 87 return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; 88 89 return readw(host->ioaddr + reg); 90 } 91 92 static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) 93 { 94 u8 ctrl; 95 u16 tmp; 96 97 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 98 tmp = readw(host->ioaddr + SD_CE_ATA_2); 99 if (width == MMC_BUS_WIDTH_8) { 100 ctrl &= ~SDHCI_CTRL_4BITBUS; 101 tmp |= MMC_CARD | MMC_WIDTH; 102 } else { 103 tmp &= ~(MMC_CARD | MMC_WIDTH); 104 if (width == MMC_BUS_WIDTH_4) 105 ctrl |= SDHCI_CTRL_4BITBUS; 106 else 107 ctrl &= ~SDHCI_CTRL_4BITBUS; 108 } 109 writew(tmp, host->ioaddr + SD_CE_ATA_2); 110 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 111 } 112 113 struct sdhci_pxa_variant { 114 const struct sdhci_ops *ops; 115 unsigned int extra_quirks; 116 }; 117 118 static const struct sdhci_ops pxav1_sdhci_ops = { 119 .read_w = pxav1_readw, 120 .set_clock = sdhci_set_clock, 121 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 122 .set_bus_width = pxav2_mmc_set_bus_width, 123 .reset = pxav2_reset, 124 .set_uhs_signaling = sdhci_set_uhs_signaling, 125 }; 126 127 static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { 128 .ops = &pxav1_sdhci_ops, 129 .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE, 130 }; 131 132 static const struct sdhci_ops pxav2_sdhci_ops = { 133 .set_clock = sdhci_set_clock, 134 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 135 .set_bus_width = pxav2_mmc_set_bus_width, 136 .reset = pxav2_reset, 137 .set_uhs_signaling = sdhci_set_uhs_signaling, 138 }; 139 140 static const struct sdhci_pxa_variant pxav2_variant = { 141 .ops = &pxav2_sdhci_ops, 142 }; 143 144 #ifdef CONFIG_OF 145 static const struct of_device_id sdhci_pxav2_of_match[] = { 146 { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, }, 147 { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, }, 148 {}, 149 }; 150 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); 151 152 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 153 { 154 struct sdhci_pxa_platdata *pdata; 155 struct device_node *np = dev->of_node; 156 u32 bus_width; 157 u32 clk_delay_cycles; 158 159 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 160 if (!pdata) 161 return NULL; 162 163 if (of_find_property(np, "non-removable", NULL)) 164 pdata->flags |= PXA_FLAG_CARD_PERMANENT; 165 166 of_property_read_u32(np, "bus-width", &bus_width); 167 if (bus_width == 8) 168 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 169 170 of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 171 if (clk_delay_cycles > 0) { 172 pdata->clk_delay_sel = 1; 173 pdata->clk_delay_cycles = clk_delay_cycles; 174 } 175 176 return pdata; 177 } 178 #else 179 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 180 { 181 return NULL; 182 } 183 #endif 184 185 static int sdhci_pxav2_probe(struct platform_device *pdev) 186 { 187 struct sdhci_pltfm_host *pltfm_host; 188 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 189 struct device *dev = &pdev->dev; 190 struct sdhci_host *host = NULL; 191 const struct sdhci_pxa_variant *variant; 192 193 int ret; 194 struct clk *clk; 195 196 host = sdhci_pltfm_init(pdev, NULL, 0); 197 if (IS_ERR(host)) 198 return PTR_ERR(host); 199 200 pltfm_host = sdhci_priv(host); 201 202 clk = devm_clk_get(dev, "PXA-SDHCLK"); 203 if (IS_ERR(clk)) { 204 dev_err(dev, "failed to get io clock\n"); 205 ret = PTR_ERR(clk); 206 goto free; 207 } 208 pltfm_host->clk = clk; 209 ret = clk_prepare_enable(clk); 210 if (ret) { 211 dev_err(&pdev->dev, "failed to enable io clock\n"); 212 goto free; 213 } 214 215 host->quirks = SDHCI_QUIRK_BROKEN_ADMA 216 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 217 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 218 219 variant = of_device_get_match_data(dev); 220 if (variant) 221 pdata = pxav2_get_mmc_pdata(dev); 222 else 223 variant = &pxav2_variant; 224 225 if (pdata) { 226 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 227 /* on-chip device */ 228 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 229 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 230 } 231 232 /* If slot design supports 8 bit data, indicate this to MMC. */ 233 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 234 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 235 236 if (pdata->quirks) 237 host->quirks |= pdata->quirks; 238 if (pdata->host_caps) 239 host->mmc->caps |= pdata->host_caps; 240 if (pdata->pm_caps) 241 host->mmc->pm_caps |= pdata->pm_caps; 242 } 243 244 host->quirks |= variant->extra_quirks; 245 host->ops = variant->ops; 246 247 ret = sdhci_add_host(host); 248 if (ret) 249 goto disable_clk; 250 251 return 0; 252 253 disable_clk: 254 clk_disable_unprepare(clk); 255 free: 256 sdhci_pltfm_free(pdev); 257 return ret; 258 } 259 260 static struct platform_driver sdhci_pxav2_driver = { 261 .driver = { 262 .name = "sdhci-pxav2", 263 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 264 .of_match_table = of_match_ptr(sdhci_pxav2_of_match), 265 .pm = &sdhci_pltfm_pmops, 266 }, 267 .probe = sdhci_pxav2_probe, 268 .remove = sdhci_pltfm_unregister, 269 }; 270 271 module_platform_driver(sdhci_pxav2_driver); 272 273 MODULE_DESCRIPTION("SDHCI driver for pxav2"); 274 MODULE_AUTHOR("Marvell International Ltd."); 275 MODULE_LICENSE("GPL v2"); 276 277