19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 29f5d71e4SZhangfei Gao /* 39f5d71e4SZhangfei Gao * Copyright (C) 2010 Marvell International Ltd. 49f5d71e4SZhangfei Gao * Zhangfei Gao <zhangfei.gao@marvell.com> 59f5d71e4SZhangfei Gao * Kevin Wang <dwang4@marvell.com> 69f5d71e4SZhangfei Gao * Jun Nie <njun@marvell.com> 79f5d71e4SZhangfei Gao * Qiming Wu <wuqm@marvell.com> 89f5d71e4SZhangfei Gao * Philip Rakity <prakity@marvell.com> 99f5d71e4SZhangfei Gao */ 109f5d71e4SZhangfei Gao 119f5d71e4SZhangfei Gao #include <linux/err.h> 129f5d71e4SZhangfei Gao #include <linux/init.h> 139f5d71e4SZhangfei Gao #include <linux/platform_device.h> 149f5d71e4SZhangfei Gao #include <linux/clk.h> 1588b47679SPaul Gortmaker #include <linux/module.h> 169f5d71e4SZhangfei Gao #include <linux/io.h> 179f5d71e4SZhangfei Gao #include <linux/mmc/card.h> 189f5d71e4SZhangfei Gao #include <linux/mmc/host.h> 19bfed345eSZhangfei Gao #include <linux/platform_data/pxa_sdhci.h> 209f5d71e4SZhangfei Gao #include <linux/slab.h> 21b650352dSChris Ball #include <linux/of.h> 22b650352dSChris Ball #include <linux/of_device.h> 2324552ccbSDoug Brown #include <linux/mmc/sdio.h> 2424552ccbSDoug Brown #include <linux/mmc/mmc.h> 25*f35ca223SDoug Brown #include <linux/pinctrl/consumer.h> 26b650352dSChris Ball 279f5d71e4SZhangfei Gao #include "sdhci.h" 289f5d71e4SZhangfei Gao #include "sdhci-pltfm.h" 299f5d71e4SZhangfei Gao 309f5d71e4SZhangfei Gao #define SD_FIFO_PARAM 0xe0 319f5d71e4SZhangfei Gao #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 329f5d71e4SZhangfei Gao #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 339f5d71e4SZhangfei Gao #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 349f5d71e4SZhangfei Gao #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 359f5d71e4SZhangfei Gao CLK_GATE_ON | CLK_GATE_CTL) 369f5d71e4SZhangfei Gao 379f5d71e4SZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 389f5d71e4SZhangfei Gao #define SDCLK_SEL_SHIFT 8 399f5d71e4SZhangfei Gao #define SDCLK_SEL_MASK 0x3 409f5d71e4SZhangfei Gao #define SDCLK_DELAY_SHIFT 10 419f5d71e4SZhangfei Gao #define SDCLK_DELAY_MASK 0x3c 429f5d71e4SZhangfei Gao 439f5d71e4SZhangfei Gao #define SD_CE_ATA_2 0xea 449f5d71e4SZhangfei Gao #define MMC_CARD 0x1000 459f5d71e4SZhangfei Gao #define MMC_WIDTH 0x0100 469f5d71e4SZhangfei Gao 4724552ccbSDoug Brown struct sdhci_pxav2_host { 4824552ccbSDoug Brown struct mmc_request *sdio_mrq; 49*f35ca223SDoug Brown struct pinctrl *pinctrl; 50*f35ca223SDoug Brown struct pinctrl_state *pins_default; 51*f35ca223SDoug Brown struct pinctrl_state *pins_cmd_gpio; 5224552ccbSDoug Brown }; 5324552ccbSDoug Brown 5403231f9bSRussell King static void pxav2_reset(struct sdhci_host *host, u8 mask) 559f5d71e4SZhangfei Gao { 569f5d71e4SZhangfei Gao struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 579f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 589f5d71e4SZhangfei Gao 5903231f9bSRussell King sdhci_reset(host, mask); 6003231f9bSRussell King 619f5d71e4SZhangfei Gao if (mask == SDHCI_RESET_ALL) { 629f5d71e4SZhangfei Gao u16 tmp = 0; 639f5d71e4SZhangfei Gao 649f5d71e4SZhangfei Gao /* 659f5d71e4SZhangfei Gao * tune timing of read data/command when crc error happen 669f5d71e4SZhangfei Gao * no performance impact 679f5d71e4SZhangfei Gao */ 68329f2237STanmay Upadhyay if (pdata && pdata->clk_delay_sel == 1) { 699f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 709f5d71e4SZhangfei Gao 719f5d71e4SZhangfei Gao tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 729f5d71e4SZhangfei Gao tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 739f5d71e4SZhangfei Gao << SDCLK_DELAY_SHIFT; 749f5d71e4SZhangfei Gao tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 759f5d71e4SZhangfei Gao tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 769f5d71e4SZhangfei Gao 779f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 789f5d71e4SZhangfei Gao } 799f5d71e4SZhangfei Gao 80329f2237STanmay Upadhyay if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { 819f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 829f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 839f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 849f5d71e4SZhangfei Gao } else { 859f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 869f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 879f5d71e4SZhangfei Gao tmp |= CLK_GATE_SETTING_BITS; 889f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 899f5d71e4SZhangfei Gao } 909f5d71e4SZhangfei Gao } 919f5d71e4SZhangfei Gao } 929f5d71e4SZhangfei Gao 937f7a201aSDoug Brown static u16 pxav1_readw(struct sdhci_host *host, int reg) 947f7a201aSDoug Brown { 957f7a201aSDoug Brown /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ 967f7a201aSDoug Brown if (reg == SDHCI_HOST_VERSION) 977f7a201aSDoug Brown return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; 987f7a201aSDoug Brown 997f7a201aSDoug Brown return readw(host->ioaddr + reg); 1007f7a201aSDoug Brown } 1017f7a201aSDoug Brown 10224552ccbSDoug Brown static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) 10324552ccbSDoug Brown { 10424552ccbSDoug Brown struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); 10524552ccbSDoug Brown struct mmc_request *sdio_mrq; 10624552ccbSDoug Brown 10724552ccbSDoug Brown if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) { 10824552ccbSDoug Brown /* The dummy CMD0 for the SDIO workaround just completed */ 10924552ccbSDoug Brown sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); 11024552ccbSDoug Brown intmask &= ~SDHCI_INT_CMD_MASK; 111*f35ca223SDoug Brown 112*f35ca223SDoug Brown /* Restore MMC function to CMD pin */ 113*f35ca223SDoug Brown if (pxav2_host->pinctrl && pxav2_host->pins_default) 114*f35ca223SDoug Brown pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default); 115*f35ca223SDoug Brown 11624552ccbSDoug Brown sdio_mrq = pxav2_host->sdio_mrq; 11724552ccbSDoug Brown pxav2_host->sdio_mrq = NULL; 11824552ccbSDoug Brown mmc_request_done(host->mmc, sdio_mrq); 11924552ccbSDoug Brown } 12024552ccbSDoug Brown 12124552ccbSDoug Brown return intmask; 12224552ccbSDoug Brown } 12324552ccbSDoug Brown 12424552ccbSDoug Brown static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) 12524552ccbSDoug Brown { 12624552ccbSDoug Brown u16 tmp; 12724552ccbSDoug Brown struct sdhci_pxav2_host *pxav2_host; 12824552ccbSDoug Brown 12924552ccbSDoug Brown /* If this is an SDIO command, perform errata workaround for silicon bug */ 13024552ccbSDoug Brown if (mrq->cmd && !mrq->cmd->error && 13124552ccbSDoug Brown (mrq->cmd->opcode == SD_IO_RW_DIRECT || 13224552ccbSDoug Brown mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { 13324552ccbSDoug Brown /* Reset data port */ 13424552ccbSDoug Brown tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); 13524552ccbSDoug Brown tmp |= 0x400; 13624552ccbSDoug Brown writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL); 13724552ccbSDoug Brown 13824552ccbSDoug Brown /* Clock is now stopped, so restart it by sending a dummy CMD0 */ 13924552ccbSDoug Brown pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); 14024552ccbSDoug Brown pxav2_host->sdio_mrq = mrq; 141*f35ca223SDoug Brown 142*f35ca223SDoug Brown /* Set CMD as high output rather than MMC function while we do CMD0 */ 143*f35ca223SDoug Brown if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio) 144*f35ca223SDoug Brown pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio); 145*f35ca223SDoug Brown 14624552ccbSDoug Brown sdhci_writel(host, 0, SDHCI_ARGUMENT); 14724552ccbSDoug Brown sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); 14824552ccbSDoug Brown sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), 14924552ccbSDoug Brown SDHCI_COMMAND); 15024552ccbSDoug Brown 15124552ccbSDoug Brown /* Don't finish this request until the dummy CMD0 finishes */ 15224552ccbSDoug Brown return; 15324552ccbSDoug Brown } 15424552ccbSDoug Brown 15524552ccbSDoug Brown mmc_request_done(host->mmc, mrq); 15624552ccbSDoug Brown } 15724552ccbSDoug Brown 1582317f56cSRussell King static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) 1599f5d71e4SZhangfei Gao { 1609f5d71e4SZhangfei Gao u8 ctrl; 1619f5d71e4SZhangfei Gao u16 tmp; 1629f5d71e4SZhangfei Gao 1639f5d71e4SZhangfei Gao ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 1649f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CE_ATA_2); 1659f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_8) { 1669f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1679f5d71e4SZhangfei Gao tmp |= MMC_CARD | MMC_WIDTH; 1689f5d71e4SZhangfei Gao } else { 1699f5d71e4SZhangfei Gao tmp &= ~(MMC_CARD | MMC_WIDTH); 1709f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_4) 1719f5d71e4SZhangfei Gao ctrl |= SDHCI_CTRL_4BITBUS; 1729f5d71e4SZhangfei Gao else 1739f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1749f5d71e4SZhangfei Gao } 1759f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CE_ATA_2); 1769f5d71e4SZhangfei Gao writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 1779f5d71e4SZhangfei Gao } 1789f5d71e4SZhangfei Gao 179dfe9746aSDoug Brown struct sdhci_pxa_variant { 180dfe9746aSDoug Brown const struct sdhci_ops *ops; 181dfe9746aSDoug Brown unsigned int extra_quirks; 182dfe9746aSDoug Brown }; 183dfe9746aSDoug Brown 184dfe9746aSDoug Brown static const struct sdhci_ops pxav1_sdhci_ops = { 1857f7a201aSDoug Brown .read_w = pxav1_readw, 186dfe9746aSDoug Brown .set_clock = sdhci_set_clock, 18724552ccbSDoug Brown .irq = pxav1_irq, 188dfe9746aSDoug Brown .get_max_clock = sdhci_pltfm_clk_get_max_clock, 189dfe9746aSDoug Brown .set_bus_width = pxav2_mmc_set_bus_width, 190dfe9746aSDoug Brown .reset = pxav2_reset, 191dfe9746aSDoug Brown .set_uhs_signaling = sdhci_set_uhs_signaling, 19224552ccbSDoug Brown .request_done = pxav1_request_done, 193dfe9746aSDoug Brown }; 194dfe9746aSDoug Brown 195dfe9746aSDoug Brown static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { 196dfe9746aSDoug Brown .ops = &pxav1_sdhci_ops, 197dfe9746aSDoug Brown .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE, 198dfe9746aSDoug Brown }; 199dfe9746aSDoug Brown 200c915568dSLars-Peter Clausen static const struct sdhci_ops pxav2_sdhci_ops = { 2011771059cSRussell King .set_clock = sdhci_set_clock, 202d005d943SLars-Peter Clausen .get_max_clock = sdhci_pltfm_clk_get_max_clock, 2032317f56cSRussell King .set_bus_width = pxav2_mmc_set_bus_width, 20403231f9bSRussell King .reset = pxav2_reset, 20596d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 2069f5d71e4SZhangfei Gao }; 2079f5d71e4SZhangfei Gao 208dfe9746aSDoug Brown static const struct sdhci_pxa_variant pxav2_variant = { 209dfe9746aSDoug Brown .ops = &pxav2_sdhci_ops, 210dfe9746aSDoug Brown }; 211dfe9746aSDoug Brown 212b650352dSChris Ball #ifdef CONFIG_OF 213b650352dSChris Ball static const struct of_device_id sdhci_pxav2_of_match[] = { 214dfe9746aSDoug Brown { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, }, 215dfe9746aSDoug Brown { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, }, 216b650352dSChris Ball {}, 217b650352dSChris Ball }; 218b650352dSChris Ball MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); 219b650352dSChris Ball 220b650352dSChris Ball static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 221b650352dSChris Ball { 222b650352dSChris Ball struct sdhci_pxa_platdata *pdata; 223b650352dSChris Ball struct device_node *np = dev->of_node; 224b650352dSChris Ball u32 bus_width; 225b650352dSChris Ball u32 clk_delay_cycles; 226b650352dSChris Ball 227b650352dSChris Ball pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 228b650352dSChris Ball if (!pdata) 229b650352dSChris Ball return NULL; 230b650352dSChris Ball 231b650352dSChris Ball if (of_find_property(np, "non-removable", NULL)) 232b650352dSChris Ball pdata->flags |= PXA_FLAG_CARD_PERMANENT; 233b650352dSChris Ball 234b650352dSChris Ball of_property_read_u32(np, "bus-width", &bus_width); 235b650352dSChris Ball if (bus_width == 8) 236b650352dSChris Ball pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 237b650352dSChris Ball 238b650352dSChris Ball of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 239b650352dSChris Ball if (clk_delay_cycles > 0) { 240b650352dSChris Ball pdata->clk_delay_sel = 1; 241b650352dSChris Ball pdata->clk_delay_cycles = clk_delay_cycles; 242b650352dSChris Ball } 243b650352dSChris Ball 244b650352dSChris Ball return pdata; 245b650352dSChris Ball } 246b650352dSChris Ball #else 247b650352dSChris Ball static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 248b650352dSChris Ball { 249b650352dSChris Ball return NULL; 250b650352dSChris Ball } 251b650352dSChris Ball #endif 252b650352dSChris Ball 253c3be1efdSBill Pemberton static int sdhci_pxav2_probe(struct platform_device *pdev) 2549f5d71e4SZhangfei Gao { 2559f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host; 2569f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 257*f35ca223SDoug Brown struct sdhci_pxav2_host *pxav2_host; 2589f5d71e4SZhangfei Gao struct device *dev = &pdev->dev; 2599f5d71e4SZhangfei Gao struct sdhci_host *host = NULL; 260dfe9746aSDoug Brown const struct sdhci_pxa_variant *variant; 261b650352dSChris Ball 2629f5d71e4SZhangfei Gao int ret; 263e41c48b4SDoug Brown struct clk *clk, *clk_core; 2649f5d71e4SZhangfei Gao 265*f35ca223SDoug Brown host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host)); 2666a686c31SSebastian Hesselbarth if (IS_ERR(host)) 2679f5d71e4SZhangfei Gao return PTR_ERR(host); 2686a686c31SSebastian Hesselbarth 2699f5d71e4SZhangfei Gao pltfm_host = sdhci_priv(host); 270*f35ca223SDoug Brown pxav2_host = sdhci_pltfm_priv(pltfm_host); 2719f5d71e4SZhangfei Gao 272c7c60bf6SDoug Brown clk = devm_clk_get(dev, "io"); 273c7c60bf6SDoug Brown if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER) 274c7c60bf6SDoug Brown clk = devm_clk_get(dev, NULL); 2759f5d71e4SZhangfei Gao if (IS_ERR(clk)) { 2769f5d71e4SZhangfei Gao ret = PTR_ERR(clk); 277c7c60bf6SDoug Brown dev_err_probe(dev, ret, "failed to get io clock\n"); 2783fd1d86fSMasahiro Yamada goto free; 2799f5d71e4SZhangfei Gao } 2809f5d71e4SZhangfei Gao pltfm_host->clk = clk; 28121b22284SAlexey Khoroshilov ret = clk_prepare_enable(clk); 28221b22284SAlexey Khoroshilov if (ret) { 283c7c60bf6SDoug Brown dev_err(dev, "failed to enable io clock\n"); 2843fd1d86fSMasahiro Yamada goto free; 28521b22284SAlexey Khoroshilov } 2869f5d71e4SZhangfei Gao 287e41c48b4SDoug Brown clk_core = devm_clk_get_optional_enabled(dev, "core"); 288e41c48b4SDoug Brown if (IS_ERR(clk_core)) { 289e41c48b4SDoug Brown ret = PTR_ERR(clk_core); 290e41c48b4SDoug Brown dev_err_probe(dev, ret, "failed to enable core clock\n"); 291e41c48b4SDoug Brown goto disable_clk; 292e41c48b4SDoug Brown } 293e41c48b4SDoug Brown 2949f5d71e4SZhangfei Gao host->quirks = SDHCI_QUIRK_BROKEN_ADMA 2959f5d71e4SZhangfei Gao | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 2969f5d71e4SZhangfei Gao | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 2979f5d71e4SZhangfei Gao 298dfe9746aSDoug Brown variant = of_device_get_match_data(dev); 299dfe9746aSDoug Brown if (variant) 300b650352dSChris Ball pdata = pxav2_get_mmc_pdata(dev); 301dfe9746aSDoug Brown else 302dfe9746aSDoug Brown variant = &pxav2_variant; 303dfe9746aSDoug Brown 3049f5d71e4SZhangfei Gao if (pdata) { 3059f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 3069f5d71e4SZhangfei Gao /* on-chip device */ 3079f5d71e4SZhangfei Gao host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 3089f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_NONREMOVABLE; 3099f5d71e4SZhangfei Gao } 3109f5d71e4SZhangfei Gao 3119f5d71e4SZhangfei Gao /* If slot design supports 8 bit data, indicate this to MMC. */ 3129f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 3139f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_8_BIT_DATA; 3149f5d71e4SZhangfei Gao 3159f5d71e4SZhangfei Gao if (pdata->quirks) 3169f5d71e4SZhangfei Gao host->quirks |= pdata->quirks; 3179f5d71e4SZhangfei Gao if (pdata->host_caps) 3189f5d71e4SZhangfei Gao host->mmc->caps |= pdata->host_caps; 3199f5d71e4SZhangfei Gao if (pdata->pm_caps) 3209f5d71e4SZhangfei Gao host->mmc->pm_caps |= pdata->pm_caps; 3219f5d71e4SZhangfei Gao } 3229f5d71e4SZhangfei Gao 323dfe9746aSDoug Brown host->quirks |= variant->extra_quirks; 324dfe9746aSDoug Brown host->ops = variant->ops; 3259f5d71e4SZhangfei Gao 326*f35ca223SDoug Brown /* Set up optional pinctrl for PXA168 SDIO IRQ fix */ 327*f35ca223SDoug Brown pxav2_host->pinctrl = devm_pinctrl_get(dev); 328*f35ca223SDoug Brown if (!IS_ERR(pxav2_host->pinctrl)) { 329*f35ca223SDoug Brown pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl, 330*f35ca223SDoug Brown "state_cmd_gpio"); 331*f35ca223SDoug Brown if (IS_ERR(pxav2_host->pins_cmd_gpio)) 332*f35ca223SDoug Brown pxav2_host->pins_cmd_gpio = NULL; 333*f35ca223SDoug Brown pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl, 334*f35ca223SDoug Brown "default"); 335*f35ca223SDoug Brown if (IS_ERR(pxav2_host->pins_default)) 336*f35ca223SDoug Brown pxav2_host->pins_default = NULL; 337*f35ca223SDoug Brown } else { 338*f35ca223SDoug Brown pxav2_host->pinctrl = NULL; 339*f35ca223SDoug Brown } 340*f35ca223SDoug Brown 3419f5d71e4SZhangfei Gao ret = sdhci_add_host(host); 342fb8617e1SJisheng Zhang if (ret) 3433fd1d86fSMasahiro Yamada goto disable_clk; 3449f5d71e4SZhangfei Gao 3459f5d71e4SZhangfei Gao return 0; 3469f5d71e4SZhangfei Gao 3473fd1d86fSMasahiro Yamada disable_clk: 348164378efSChao Xie clk_disable_unprepare(clk); 3493fd1d86fSMasahiro Yamada free: 3509f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 3519f5d71e4SZhangfei Gao return ret; 3529f5d71e4SZhangfei Gao } 3539f5d71e4SZhangfei Gao 3549f5d71e4SZhangfei Gao static struct platform_driver sdhci_pxav2_driver = { 3559f5d71e4SZhangfei Gao .driver = { 3569f5d71e4SZhangfei Gao .name = "sdhci-pxav2", 35721b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 35859d22309SAxel Lin .of_match_table = of_match_ptr(sdhci_pxav2_of_match), 359fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops, 3609f5d71e4SZhangfei Gao }, 3619f5d71e4SZhangfei Gao .probe = sdhci_pxav2_probe, 3623fd1d86fSMasahiro Yamada .remove = sdhci_pltfm_unregister, 3639f5d71e4SZhangfei Gao }; 3649f5d71e4SZhangfei Gao 365d1f81a64SAxel Lin module_platform_driver(sdhci_pxav2_driver); 3669f5d71e4SZhangfei Gao 3679f5d71e4SZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav2"); 3689f5d71e4SZhangfei Gao MODULE_AUTHOR("Marvell International Ltd."); 3699f5d71e4SZhangfei Gao MODULE_LICENSE("GPL v2"); 3709f5d71e4SZhangfei Gao 371