19f5d71e4SZhangfei Gao /* 29f5d71e4SZhangfei Gao * Copyright (C) 2010 Marvell International Ltd. 39f5d71e4SZhangfei Gao * Zhangfei Gao <zhangfei.gao@marvell.com> 49f5d71e4SZhangfei Gao * Kevin Wang <dwang4@marvell.com> 59f5d71e4SZhangfei Gao * Jun Nie <njun@marvell.com> 69f5d71e4SZhangfei Gao * Qiming Wu <wuqm@marvell.com> 79f5d71e4SZhangfei Gao * Philip Rakity <prakity@marvell.com> 89f5d71e4SZhangfei Gao * 99f5d71e4SZhangfei Gao * This software is licensed under the terms of the GNU General Public 109f5d71e4SZhangfei Gao * License version 2, as published by the Free Software Foundation, and 119f5d71e4SZhangfei Gao * may be copied, distributed, and modified under those terms. 129f5d71e4SZhangfei Gao * 139f5d71e4SZhangfei Gao * This program is distributed in the hope that it will be useful, 149f5d71e4SZhangfei Gao * but WITHOUT ANY WARRANTY; without even the implied warranty of 159f5d71e4SZhangfei Gao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 169f5d71e4SZhangfei Gao * GNU General Public License for more details. 179f5d71e4SZhangfei Gao * 189f5d71e4SZhangfei Gao */ 199f5d71e4SZhangfei Gao 209f5d71e4SZhangfei Gao #include <linux/err.h> 219f5d71e4SZhangfei Gao #include <linux/init.h> 229f5d71e4SZhangfei Gao #include <linux/platform_device.h> 239f5d71e4SZhangfei Gao #include <linux/clk.h> 2488b47679SPaul Gortmaker #include <linux/module.h> 259f5d71e4SZhangfei Gao #include <linux/io.h> 269f5d71e4SZhangfei Gao #include <linux/gpio.h> 279f5d71e4SZhangfei Gao #include <linux/mmc/card.h> 289f5d71e4SZhangfei Gao #include <linux/mmc/host.h> 29bfed345eSZhangfei Gao #include <linux/platform_data/pxa_sdhci.h> 309f5d71e4SZhangfei Gao #include <linux/slab.h> 31b650352dSChris Ball #include <linux/of.h> 32b650352dSChris Ball #include <linux/of_device.h> 33b650352dSChris Ball 349f5d71e4SZhangfei Gao #include "sdhci.h" 359f5d71e4SZhangfei Gao #include "sdhci-pltfm.h" 369f5d71e4SZhangfei Gao 379f5d71e4SZhangfei Gao #define SD_FIFO_PARAM 0xe0 389f5d71e4SZhangfei Gao #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 399f5d71e4SZhangfei Gao #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 409f5d71e4SZhangfei Gao #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 419f5d71e4SZhangfei Gao #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 429f5d71e4SZhangfei Gao CLK_GATE_ON | CLK_GATE_CTL) 439f5d71e4SZhangfei Gao 449f5d71e4SZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 459f5d71e4SZhangfei Gao #define SDCLK_SEL_SHIFT 8 469f5d71e4SZhangfei Gao #define SDCLK_SEL_MASK 0x3 479f5d71e4SZhangfei Gao #define SDCLK_DELAY_SHIFT 10 489f5d71e4SZhangfei Gao #define SDCLK_DELAY_MASK 0x3c 499f5d71e4SZhangfei Gao 509f5d71e4SZhangfei Gao #define SD_CE_ATA_2 0xea 519f5d71e4SZhangfei Gao #define MMC_CARD 0x1000 529f5d71e4SZhangfei Gao #define MMC_WIDTH 0x0100 539f5d71e4SZhangfei Gao 549f5d71e4SZhangfei Gao static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask) 559f5d71e4SZhangfei Gao { 569f5d71e4SZhangfei Gao struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 579f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 589f5d71e4SZhangfei Gao 599f5d71e4SZhangfei Gao if (mask == SDHCI_RESET_ALL) { 609f5d71e4SZhangfei Gao u16 tmp = 0; 619f5d71e4SZhangfei Gao 629f5d71e4SZhangfei Gao /* 639f5d71e4SZhangfei Gao * tune timing of read data/command when crc error happen 649f5d71e4SZhangfei Gao * no performance impact 659f5d71e4SZhangfei Gao */ 66329f2237STanmay Upadhyay if (pdata && pdata->clk_delay_sel == 1) { 679f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 689f5d71e4SZhangfei Gao 699f5d71e4SZhangfei Gao tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 709f5d71e4SZhangfei Gao tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 719f5d71e4SZhangfei Gao << SDCLK_DELAY_SHIFT; 729f5d71e4SZhangfei Gao tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 739f5d71e4SZhangfei Gao tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 749f5d71e4SZhangfei Gao 759f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 769f5d71e4SZhangfei Gao } 779f5d71e4SZhangfei Gao 78329f2237STanmay Upadhyay if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { 799f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 809f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 819f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 829f5d71e4SZhangfei Gao } else { 839f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 849f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 859f5d71e4SZhangfei Gao tmp |= CLK_GATE_SETTING_BITS; 869f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 879f5d71e4SZhangfei Gao } 889f5d71e4SZhangfei Gao } 899f5d71e4SZhangfei Gao } 909f5d71e4SZhangfei Gao 919f5d71e4SZhangfei Gao static int pxav2_mmc_set_width(struct sdhci_host *host, int width) 929f5d71e4SZhangfei Gao { 939f5d71e4SZhangfei Gao u8 ctrl; 949f5d71e4SZhangfei Gao u16 tmp; 959f5d71e4SZhangfei Gao 969f5d71e4SZhangfei Gao ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 979f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CE_ATA_2); 989f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_8) { 999f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1009f5d71e4SZhangfei Gao tmp |= MMC_CARD | MMC_WIDTH; 1019f5d71e4SZhangfei Gao } else { 1029f5d71e4SZhangfei Gao tmp &= ~(MMC_CARD | MMC_WIDTH); 1039f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_4) 1049f5d71e4SZhangfei Gao ctrl |= SDHCI_CTRL_4BITBUS; 1059f5d71e4SZhangfei Gao else 1069f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1079f5d71e4SZhangfei Gao } 1089f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CE_ATA_2); 1099f5d71e4SZhangfei Gao writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 1109f5d71e4SZhangfei Gao 1119f5d71e4SZhangfei Gao return 0; 1129f5d71e4SZhangfei Gao } 1139f5d71e4SZhangfei Gao 1149f5d71e4SZhangfei Gao static u32 pxav2_get_max_clock(struct sdhci_host *host) 1159f5d71e4SZhangfei Gao { 1169f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1179f5d71e4SZhangfei Gao 1189f5d71e4SZhangfei Gao return clk_get_rate(pltfm_host->clk); 1199f5d71e4SZhangfei Gao } 1209f5d71e4SZhangfei Gao 1219f5d71e4SZhangfei Gao static struct sdhci_ops pxav2_sdhci_ops = { 1229f5d71e4SZhangfei Gao .get_max_clock = pxav2_get_max_clock, 1239f5d71e4SZhangfei Gao .platform_reset_exit = pxav2_set_private_registers, 1249f5d71e4SZhangfei Gao .platform_8bit_width = pxav2_mmc_set_width, 1259f5d71e4SZhangfei Gao }; 1269f5d71e4SZhangfei Gao 127b650352dSChris Ball #ifdef CONFIG_OF 128b650352dSChris Ball static const struct of_device_id sdhci_pxav2_of_match[] = { 129b650352dSChris Ball { 130b650352dSChris Ball .compatible = "mrvl,pxav2-mmc", 131b650352dSChris Ball }, 132b650352dSChris Ball {}, 133b650352dSChris Ball }; 134b650352dSChris Ball MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); 135b650352dSChris Ball 136b650352dSChris Ball static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 137b650352dSChris Ball { 138b650352dSChris Ball struct sdhci_pxa_platdata *pdata; 139b650352dSChris Ball struct device_node *np = dev->of_node; 140b650352dSChris Ball u32 bus_width; 141b650352dSChris Ball u32 clk_delay_cycles; 142b650352dSChris Ball 143b650352dSChris Ball pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 144b650352dSChris Ball if (!pdata) 145b650352dSChris Ball return NULL; 146b650352dSChris Ball 147b650352dSChris Ball if (of_find_property(np, "non-removable", NULL)) 148b650352dSChris Ball pdata->flags |= PXA_FLAG_CARD_PERMANENT; 149b650352dSChris Ball 150b650352dSChris Ball of_property_read_u32(np, "bus-width", &bus_width); 151b650352dSChris Ball if (bus_width == 8) 152b650352dSChris Ball pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 153b650352dSChris Ball 154b650352dSChris Ball of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 155b650352dSChris Ball if (clk_delay_cycles > 0) { 156b650352dSChris Ball pdata->clk_delay_sel = 1; 157b650352dSChris Ball pdata->clk_delay_cycles = clk_delay_cycles; 158b650352dSChris Ball } 159b650352dSChris Ball 160b650352dSChris Ball return pdata; 161b650352dSChris Ball } 162b650352dSChris Ball #else 163b650352dSChris Ball static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 164b650352dSChris Ball { 165b650352dSChris Ball return NULL; 166b650352dSChris Ball } 167b650352dSChris Ball #endif 168b650352dSChris Ball 169c3be1efdSBill Pemberton static int sdhci_pxav2_probe(struct platform_device *pdev) 1709f5d71e4SZhangfei Gao { 1719f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host; 1729f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 1739f5d71e4SZhangfei Gao struct device *dev = &pdev->dev; 1749f5d71e4SZhangfei Gao struct sdhci_host *host = NULL; 1759f5d71e4SZhangfei Gao struct sdhci_pxa *pxa = NULL; 176b650352dSChris Ball const struct of_device_id *match; 177b650352dSChris Ball 1789f5d71e4SZhangfei Gao int ret; 1799f5d71e4SZhangfei Gao struct clk *clk; 1809f5d71e4SZhangfei Gao 1819f5d71e4SZhangfei Gao pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); 1829f5d71e4SZhangfei Gao if (!pxa) 1839f5d71e4SZhangfei Gao return -ENOMEM; 1849f5d71e4SZhangfei Gao 1859f5d71e4SZhangfei Gao host = sdhci_pltfm_init(pdev, NULL); 1869f5d71e4SZhangfei Gao if (IS_ERR(host)) { 1879f5d71e4SZhangfei Gao kfree(pxa); 1889f5d71e4SZhangfei Gao return PTR_ERR(host); 1899f5d71e4SZhangfei Gao } 1909f5d71e4SZhangfei Gao pltfm_host = sdhci_priv(host); 1919f5d71e4SZhangfei Gao pltfm_host->priv = pxa; 1929f5d71e4SZhangfei Gao 1939f5d71e4SZhangfei Gao clk = clk_get(dev, "PXA-SDHCLK"); 1949f5d71e4SZhangfei Gao if (IS_ERR(clk)) { 1959f5d71e4SZhangfei Gao dev_err(dev, "failed to get io clock\n"); 1969f5d71e4SZhangfei Gao ret = PTR_ERR(clk); 1979f5d71e4SZhangfei Gao goto err_clk_get; 1989f5d71e4SZhangfei Gao } 1999f5d71e4SZhangfei Gao pltfm_host->clk = clk; 200164378efSChao Xie clk_prepare_enable(clk); 2019f5d71e4SZhangfei Gao 2029f5d71e4SZhangfei Gao host->quirks = SDHCI_QUIRK_BROKEN_ADMA 2039f5d71e4SZhangfei Gao | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 2049f5d71e4SZhangfei Gao | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 2059f5d71e4SZhangfei Gao 206b650352dSChris Ball match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev); 207b650352dSChris Ball if (match) { 208b650352dSChris Ball pdata = pxav2_get_mmc_pdata(dev); 209b650352dSChris Ball } 2109f5d71e4SZhangfei Gao if (pdata) { 2119f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 2129f5d71e4SZhangfei Gao /* on-chip device */ 2139f5d71e4SZhangfei Gao host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 2149f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_NONREMOVABLE; 2159f5d71e4SZhangfei Gao } 2169f5d71e4SZhangfei Gao 2179f5d71e4SZhangfei Gao /* If slot design supports 8 bit data, indicate this to MMC. */ 2189f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 2199f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_8_BIT_DATA; 2209f5d71e4SZhangfei Gao 2219f5d71e4SZhangfei Gao if (pdata->quirks) 2229f5d71e4SZhangfei Gao host->quirks |= pdata->quirks; 2239f5d71e4SZhangfei Gao if (pdata->host_caps) 2249f5d71e4SZhangfei Gao host->mmc->caps |= pdata->host_caps; 2259f5d71e4SZhangfei Gao if (pdata->pm_caps) 2269f5d71e4SZhangfei Gao host->mmc->pm_caps |= pdata->pm_caps; 2279f5d71e4SZhangfei Gao } 2289f5d71e4SZhangfei Gao 2299f5d71e4SZhangfei Gao host->ops = &pxav2_sdhci_ops; 2309f5d71e4SZhangfei Gao 2319f5d71e4SZhangfei Gao ret = sdhci_add_host(host); 2329f5d71e4SZhangfei Gao if (ret) { 2339f5d71e4SZhangfei Gao dev_err(&pdev->dev, "failed to add host\n"); 2349f5d71e4SZhangfei Gao goto err_add_host; 2359f5d71e4SZhangfei Gao } 2369f5d71e4SZhangfei Gao 2379f5d71e4SZhangfei Gao platform_set_drvdata(pdev, host); 2389f5d71e4SZhangfei Gao 2399f5d71e4SZhangfei Gao return 0; 2409f5d71e4SZhangfei Gao 2419f5d71e4SZhangfei Gao err_add_host: 242164378efSChao Xie clk_disable_unprepare(clk); 2439f5d71e4SZhangfei Gao clk_put(clk); 2449f5d71e4SZhangfei Gao err_clk_get: 2459f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 2469f5d71e4SZhangfei Gao kfree(pxa); 2479f5d71e4SZhangfei Gao return ret; 2489f5d71e4SZhangfei Gao } 2499f5d71e4SZhangfei Gao 2509f5d71e4SZhangfei Gao static int __devexit sdhci_pxav2_remove(struct platform_device *pdev) 2519f5d71e4SZhangfei Gao { 2529f5d71e4SZhangfei Gao struct sdhci_host *host = platform_get_drvdata(pdev); 2539f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2549f5d71e4SZhangfei Gao struct sdhci_pxa *pxa = pltfm_host->priv; 2559f5d71e4SZhangfei Gao 2569f5d71e4SZhangfei Gao sdhci_remove_host(host, 1); 2579f5d71e4SZhangfei Gao 258164378efSChao Xie clk_disable_unprepare(pltfm_host->clk); 2599f5d71e4SZhangfei Gao clk_put(pltfm_host->clk); 2609f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 2619f5d71e4SZhangfei Gao kfree(pxa); 2629f5d71e4SZhangfei Gao 2639f5d71e4SZhangfei Gao platform_set_drvdata(pdev, NULL); 2649f5d71e4SZhangfei Gao 2659f5d71e4SZhangfei Gao return 0; 2669f5d71e4SZhangfei Gao } 2679f5d71e4SZhangfei Gao 2689f5d71e4SZhangfei Gao static struct platform_driver sdhci_pxav2_driver = { 2699f5d71e4SZhangfei Gao .driver = { 2709f5d71e4SZhangfei Gao .name = "sdhci-pxav2", 2719f5d71e4SZhangfei Gao .owner = THIS_MODULE, 272b650352dSChris Ball #ifdef CONFIG_OF 273b650352dSChris Ball .of_match_table = sdhci_pxav2_of_match, 274b650352dSChris Ball #endif 27529495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 2769f5d71e4SZhangfei Gao }, 2779f5d71e4SZhangfei Gao .probe = sdhci_pxav2_probe, 2780433c143SBill Pemberton .remove = sdhci_pxav2_remove, 2799f5d71e4SZhangfei Gao }; 2809f5d71e4SZhangfei Gao 281d1f81a64SAxel Lin module_platform_driver(sdhci_pxav2_driver); 2829f5d71e4SZhangfei Gao 2839f5d71e4SZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav2"); 2849f5d71e4SZhangfei Gao MODULE_AUTHOR("Marvell International Ltd."); 2859f5d71e4SZhangfei Gao MODULE_LICENSE("GPL v2"); 2869f5d71e4SZhangfei Gao 287