19f5d71e4SZhangfei Gao /* 29f5d71e4SZhangfei Gao * Copyright (C) 2010 Marvell International Ltd. 39f5d71e4SZhangfei Gao * Zhangfei Gao <zhangfei.gao@marvell.com> 49f5d71e4SZhangfei Gao * Kevin Wang <dwang4@marvell.com> 59f5d71e4SZhangfei Gao * Jun Nie <njun@marvell.com> 69f5d71e4SZhangfei Gao * Qiming Wu <wuqm@marvell.com> 79f5d71e4SZhangfei Gao * Philip Rakity <prakity@marvell.com> 89f5d71e4SZhangfei Gao * 99f5d71e4SZhangfei Gao * This software is licensed under the terms of the GNU General Public 109f5d71e4SZhangfei Gao * License version 2, as published by the Free Software Foundation, and 119f5d71e4SZhangfei Gao * may be copied, distributed, and modified under those terms. 129f5d71e4SZhangfei Gao * 139f5d71e4SZhangfei Gao * This program is distributed in the hope that it will be useful, 149f5d71e4SZhangfei Gao * but WITHOUT ANY WARRANTY; without even the implied warranty of 159f5d71e4SZhangfei Gao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 169f5d71e4SZhangfei Gao * GNU General Public License for more details. 179f5d71e4SZhangfei Gao * 189f5d71e4SZhangfei Gao */ 199f5d71e4SZhangfei Gao 209f5d71e4SZhangfei Gao #include <linux/err.h> 219f5d71e4SZhangfei Gao #include <linux/init.h> 229f5d71e4SZhangfei Gao #include <linux/platform_device.h> 239f5d71e4SZhangfei Gao #include <linux/clk.h> 249f5d71e4SZhangfei Gao #include <linux/io.h> 259f5d71e4SZhangfei Gao #include <linux/gpio.h> 269f5d71e4SZhangfei Gao #include <linux/mmc/card.h> 279f5d71e4SZhangfei Gao #include <linux/mmc/host.h> 289f5d71e4SZhangfei Gao #include <plat/sdhci.h> 299f5d71e4SZhangfei Gao #include <linux/slab.h> 309f5d71e4SZhangfei Gao #include "sdhci.h" 319f5d71e4SZhangfei Gao #include "sdhci-pltfm.h" 329f5d71e4SZhangfei Gao 339f5d71e4SZhangfei Gao #define SD_FIFO_PARAM 0xe0 349f5d71e4SZhangfei Gao #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 359f5d71e4SZhangfei Gao #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 369f5d71e4SZhangfei Gao #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 379f5d71e4SZhangfei Gao #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 389f5d71e4SZhangfei Gao CLK_GATE_ON | CLK_GATE_CTL) 399f5d71e4SZhangfei Gao 409f5d71e4SZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 419f5d71e4SZhangfei Gao #define SDCLK_SEL_SHIFT 8 429f5d71e4SZhangfei Gao #define SDCLK_SEL_MASK 0x3 439f5d71e4SZhangfei Gao #define SDCLK_DELAY_SHIFT 10 449f5d71e4SZhangfei Gao #define SDCLK_DELAY_MASK 0x3c 459f5d71e4SZhangfei Gao 469f5d71e4SZhangfei Gao #define SD_CE_ATA_2 0xea 479f5d71e4SZhangfei Gao #define MMC_CARD 0x1000 489f5d71e4SZhangfei Gao #define MMC_WIDTH 0x0100 499f5d71e4SZhangfei Gao 509f5d71e4SZhangfei Gao static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask) 519f5d71e4SZhangfei Gao { 529f5d71e4SZhangfei Gao struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 539f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 549f5d71e4SZhangfei Gao 559f5d71e4SZhangfei Gao if (mask == SDHCI_RESET_ALL) { 569f5d71e4SZhangfei Gao u16 tmp = 0; 579f5d71e4SZhangfei Gao 589f5d71e4SZhangfei Gao /* 599f5d71e4SZhangfei Gao * tune timing of read data/command when crc error happen 609f5d71e4SZhangfei Gao * no performance impact 619f5d71e4SZhangfei Gao */ 629f5d71e4SZhangfei Gao if (pdata->clk_delay_sel == 1) { 639f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 649f5d71e4SZhangfei Gao 659f5d71e4SZhangfei Gao tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 669f5d71e4SZhangfei Gao tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 679f5d71e4SZhangfei Gao << SDCLK_DELAY_SHIFT; 689f5d71e4SZhangfei Gao tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 699f5d71e4SZhangfei Gao tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 709f5d71e4SZhangfei Gao 719f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 729f5d71e4SZhangfei Gao } 739f5d71e4SZhangfei Gao 749f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING) { 759f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 769f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 779f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 789f5d71e4SZhangfei Gao } else { 799f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 809f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 819f5d71e4SZhangfei Gao tmp |= CLK_GATE_SETTING_BITS; 829f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 839f5d71e4SZhangfei Gao } 849f5d71e4SZhangfei Gao } 859f5d71e4SZhangfei Gao } 869f5d71e4SZhangfei Gao 879f5d71e4SZhangfei Gao static int pxav2_mmc_set_width(struct sdhci_host *host, int width) 889f5d71e4SZhangfei Gao { 899f5d71e4SZhangfei Gao u8 ctrl; 909f5d71e4SZhangfei Gao u16 tmp; 919f5d71e4SZhangfei Gao 929f5d71e4SZhangfei Gao ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 939f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CE_ATA_2); 949f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_8) { 959f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 969f5d71e4SZhangfei Gao tmp |= MMC_CARD | MMC_WIDTH; 979f5d71e4SZhangfei Gao } else { 989f5d71e4SZhangfei Gao tmp &= ~(MMC_CARD | MMC_WIDTH); 999f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_4) 1009f5d71e4SZhangfei Gao ctrl |= SDHCI_CTRL_4BITBUS; 1019f5d71e4SZhangfei Gao else 1029f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1039f5d71e4SZhangfei Gao } 1049f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CE_ATA_2); 1059f5d71e4SZhangfei Gao writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 1069f5d71e4SZhangfei Gao 1079f5d71e4SZhangfei Gao return 0; 1089f5d71e4SZhangfei Gao } 1099f5d71e4SZhangfei Gao 1109f5d71e4SZhangfei Gao static u32 pxav2_get_max_clock(struct sdhci_host *host) 1119f5d71e4SZhangfei Gao { 1129f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1139f5d71e4SZhangfei Gao 1149f5d71e4SZhangfei Gao return clk_get_rate(pltfm_host->clk); 1159f5d71e4SZhangfei Gao } 1169f5d71e4SZhangfei Gao 1179f5d71e4SZhangfei Gao static struct sdhci_ops pxav2_sdhci_ops = { 1189f5d71e4SZhangfei Gao .get_max_clock = pxav2_get_max_clock, 1199f5d71e4SZhangfei Gao .platform_reset_exit = pxav2_set_private_registers, 1209f5d71e4SZhangfei Gao .platform_8bit_width = pxav2_mmc_set_width, 1219f5d71e4SZhangfei Gao }; 1229f5d71e4SZhangfei Gao 1239f5d71e4SZhangfei Gao static int __devinit sdhci_pxav2_probe(struct platform_device *pdev) 1249f5d71e4SZhangfei Gao { 1259f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host; 1269f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 1279f5d71e4SZhangfei Gao struct device *dev = &pdev->dev; 1289f5d71e4SZhangfei Gao struct sdhci_host *host = NULL; 1299f5d71e4SZhangfei Gao struct sdhci_pxa *pxa = NULL; 1309f5d71e4SZhangfei Gao int ret; 1319f5d71e4SZhangfei Gao struct clk *clk; 1329f5d71e4SZhangfei Gao 1339f5d71e4SZhangfei Gao pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); 1349f5d71e4SZhangfei Gao if (!pxa) 1359f5d71e4SZhangfei Gao return -ENOMEM; 1369f5d71e4SZhangfei Gao 1379f5d71e4SZhangfei Gao host = sdhci_pltfm_init(pdev, NULL); 1389f5d71e4SZhangfei Gao if (IS_ERR(host)) { 1399f5d71e4SZhangfei Gao kfree(pxa); 1409f5d71e4SZhangfei Gao return PTR_ERR(host); 1419f5d71e4SZhangfei Gao } 1429f5d71e4SZhangfei Gao pltfm_host = sdhci_priv(host); 1439f5d71e4SZhangfei Gao pltfm_host->priv = pxa; 1449f5d71e4SZhangfei Gao 1459f5d71e4SZhangfei Gao clk = clk_get(dev, "PXA-SDHCLK"); 1469f5d71e4SZhangfei Gao if (IS_ERR(clk)) { 1479f5d71e4SZhangfei Gao dev_err(dev, "failed to get io clock\n"); 1489f5d71e4SZhangfei Gao ret = PTR_ERR(clk); 1499f5d71e4SZhangfei Gao goto err_clk_get; 1509f5d71e4SZhangfei Gao } 1519f5d71e4SZhangfei Gao pltfm_host->clk = clk; 1529f5d71e4SZhangfei Gao clk_enable(clk); 1539f5d71e4SZhangfei Gao 1549f5d71e4SZhangfei Gao host->quirks = SDHCI_QUIRK_BROKEN_ADMA 1559f5d71e4SZhangfei Gao | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 1569f5d71e4SZhangfei Gao | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 1579f5d71e4SZhangfei Gao 1589f5d71e4SZhangfei Gao if (pdata) { 1599f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 1609f5d71e4SZhangfei Gao /* on-chip device */ 1619f5d71e4SZhangfei Gao host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1629f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_NONREMOVABLE; 1639f5d71e4SZhangfei Gao } 1649f5d71e4SZhangfei Gao 1659f5d71e4SZhangfei Gao /* If slot design supports 8 bit data, indicate this to MMC. */ 1669f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 1679f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_8_BIT_DATA; 1689f5d71e4SZhangfei Gao 1699f5d71e4SZhangfei Gao if (pdata->quirks) 1709f5d71e4SZhangfei Gao host->quirks |= pdata->quirks; 1719f5d71e4SZhangfei Gao if (pdata->host_caps) 1729f5d71e4SZhangfei Gao host->mmc->caps |= pdata->host_caps; 1739f5d71e4SZhangfei Gao if (pdata->pm_caps) 1749f5d71e4SZhangfei Gao host->mmc->pm_caps |= pdata->pm_caps; 1759f5d71e4SZhangfei Gao } 1769f5d71e4SZhangfei Gao 1779f5d71e4SZhangfei Gao host->ops = &pxav2_sdhci_ops; 1789f5d71e4SZhangfei Gao 1799f5d71e4SZhangfei Gao ret = sdhci_add_host(host); 1809f5d71e4SZhangfei Gao if (ret) { 1819f5d71e4SZhangfei Gao dev_err(&pdev->dev, "failed to add host\n"); 1829f5d71e4SZhangfei Gao goto err_add_host; 1839f5d71e4SZhangfei Gao } 1849f5d71e4SZhangfei Gao 1859f5d71e4SZhangfei Gao platform_set_drvdata(pdev, host); 1869f5d71e4SZhangfei Gao 1879f5d71e4SZhangfei Gao return 0; 1889f5d71e4SZhangfei Gao 1899f5d71e4SZhangfei Gao err_add_host: 1909f5d71e4SZhangfei Gao clk_disable(clk); 1919f5d71e4SZhangfei Gao clk_put(clk); 1929f5d71e4SZhangfei Gao err_clk_get: 1939f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 1949f5d71e4SZhangfei Gao kfree(pxa); 1959f5d71e4SZhangfei Gao return ret; 1969f5d71e4SZhangfei Gao } 1979f5d71e4SZhangfei Gao 1989f5d71e4SZhangfei Gao static int __devexit sdhci_pxav2_remove(struct platform_device *pdev) 1999f5d71e4SZhangfei Gao { 2009f5d71e4SZhangfei Gao struct sdhci_host *host = platform_get_drvdata(pdev); 2019f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2029f5d71e4SZhangfei Gao struct sdhci_pxa *pxa = pltfm_host->priv; 2039f5d71e4SZhangfei Gao 2049f5d71e4SZhangfei Gao sdhci_remove_host(host, 1); 2059f5d71e4SZhangfei Gao 2069f5d71e4SZhangfei Gao clk_disable(pltfm_host->clk); 2079f5d71e4SZhangfei Gao clk_put(pltfm_host->clk); 2089f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 2099f5d71e4SZhangfei Gao kfree(pxa); 2109f5d71e4SZhangfei Gao 2119f5d71e4SZhangfei Gao platform_set_drvdata(pdev, NULL); 2129f5d71e4SZhangfei Gao 2139f5d71e4SZhangfei Gao return 0; 2149f5d71e4SZhangfei Gao } 2159f5d71e4SZhangfei Gao 2169f5d71e4SZhangfei Gao static struct platform_driver sdhci_pxav2_driver = { 2179f5d71e4SZhangfei Gao .driver = { 2189f5d71e4SZhangfei Gao .name = "sdhci-pxav2", 2199f5d71e4SZhangfei Gao .owner = THIS_MODULE, 2209f5d71e4SZhangfei Gao }, 2219f5d71e4SZhangfei Gao .probe = sdhci_pxav2_probe, 2229f5d71e4SZhangfei Gao .remove = __devexit_p(sdhci_pxav2_remove), 2239f5d71e4SZhangfei Gao #ifdef CONFIG_PM 2249f5d71e4SZhangfei Gao .suspend = sdhci_pltfm_suspend, 2259f5d71e4SZhangfei Gao .resume = sdhci_pltfm_resume, 2269f5d71e4SZhangfei Gao #endif 2279f5d71e4SZhangfei Gao }; 2289f5d71e4SZhangfei Gao static int __init sdhci_pxav2_init(void) 2299f5d71e4SZhangfei Gao { 2309f5d71e4SZhangfei Gao return platform_driver_register(&sdhci_pxav2_driver); 2319f5d71e4SZhangfei Gao } 2329f5d71e4SZhangfei Gao 2339f5d71e4SZhangfei Gao static void __exit sdhci_pxav2_exit(void) 2349f5d71e4SZhangfei Gao { 2359f5d71e4SZhangfei Gao platform_driver_unregister(&sdhci_pxav2_driver); 2369f5d71e4SZhangfei Gao } 2379f5d71e4SZhangfei Gao 2389f5d71e4SZhangfei Gao module_init(sdhci_pxav2_init); 2399f5d71e4SZhangfei Gao module_exit(sdhci_pxav2_exit); 2409f5d71e4SZhangfei Gao 2419f5d71e4SZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav2"); 2429f5d71e4SZhangfei Gao MODULE_AUTHOR("Marvell International Ltd."); 2439f5d71e4SZhangfei Gao MODULE_LICENSE("GPL v2"); 2449f5d71e4SZhangfei Gao 245