19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 29f5d71e4SZhangfei Gao /* 39f5d71e4SZhangfei Gao * Copyright (C) 2010 Marvell International Ltd. 49f5d71e4SZhangfei Gao * Zhangfei Gao <zhangfei.gao@marvell.com> 59f5d71e4SZhangfei Gao * Kevin Wang <dwang4@marvell.com> 69f5d71e4SZhangfei Gao * Jun Nie <njun@marvell.com> 79f5d71e4SZhangfei Gao * Qiming Wu <wuqm@marvell.com> 89f5d71e4SZhangfei Gao * Philip Rakity <prakity@marvell.com> 99f5d71e4SZhangfei Gao */ 109f5d71e4SZhangfei Gao 119f5d71e4SZhangfei Gao #include <linux/err.h> 129f5d71e4SZhangfei Gao #include <linux/init.h> 139f5d71e4SZhangfei Gao #include <linux/platform_device.h> 149f5d71e4SZhangfei Gao #include <linux/clk.h> 1588b47679SPaul Gortmaker #include <linux/module.h> 169f5d71e4SZhangfei Gao #include <linux/io.h> 179f5d71e4SZhangfei Gao #include <linux/mmc/card.h> 189f5d71e4SZhangfei Gao #include <linux/mmc/host.h> 19bfed345eSZhangfei Gao #include <linux/platform_data/pxa_sdhci.h> 209f5d71e4SZhangfei Gao #include <linux/slab.h> 21b650352dSChris Ball #include <linux/of.h> 22b650352dSChris Ball #include <linux/of_device.h> 23b650352dSChris Ball 249f5d71e4SZhangfei Gao #include "sdhci.h" 259f5d71e4SZhangfei Gao #include "sdhci-pltfm.h" 269f5d71e4SZhangfei Gao 279f5d71e4SZhangfei Gao #define SD_FIFO_PARAM 0xe0 289f5d71e4SZhangfei Gao #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 299f5d71e4SZhangfei Gao #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 309f5d71e4SZhangfei Gao #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 319f5d71e4SZhangfei Gao #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 329f5d71e4SZhangfei Gao CLK_GATE_ON | CLK_GATE_CTL) 339f5d71e4SZhangfei Gao 349f5d71e4SZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 359f5d71e4SZhangfei Gao #define SDCLK_SEL_SHIFT 8 369f5d71e4SZhangfei Gao #define SDCLK_SEL_MASK 0x3 379f5d71e4SZhangfei Gao #define SDCLK_DELAY_SHIFT 10 389f5d71e4SZhangfei Gao #define SDCLK_DELAY_MASK 0x3c 399f5d71e4SZhangfei Gao 409f5d71e4SZhangfei Gao #define SD_CE_ATA_2 0xea 419f5d71e4SZhangfei Gao #define MMC_CARD 0x1000 429f5d71e4SZhangfei Gao #define MMC_WIDTH 0x0100 439f5d71e4SZhangfei Gao 4403231f9bSRussell King static void pxav2_reset(struct sdhci_host *host, u8 mask) 459f5d71e4SZhangfei Gao { 469f5d71e4SZhangfei Gao struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 479f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 489f5d71e4SZhangfei Gao 4903231f9bSRussell King sdhci_reset(host, mask); 5003231f9bSRussell King 519f5d71e4SZhangfei Gao if (mask == SDHCI_RESET_ALL) { 529f5d71e4SZhangfei Gao u16 tmp = 0; 539f5d71e4SZhangfei Gao 549f5d71e4SZhangfei Gao /* 559f5d71e4SZhangfei Gao * tune timing of read data/command when crc error happen 569f5d71e4SZhangfei Gao * no performance impact 579f5d71e4SZhangfei Gao */ 58329f2237STanmay Upadhyay if (pdata && pdata->clk_delay_sel == 1) { 599f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 609f5d71e4SZhangfei Gao 619f5d71e4SZhangfei Gao tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 629f5d71e4SZhangfei Gao tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 639f5d71e4SZhangfei Gao << SDCLK_DELAY_SHIFT; 649f5d71e4SZhangfei Gao tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 659f5d71e4SZhangfei Gao tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 669f5d71e4SZhangfei Gao 679f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 689f5d71e4SZhangfei Gao } 699f5d71e4SZhangfei Gao 70329f2237STanmay Upadhyay if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { 719f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 729f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 739f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 749f5d71e4SZhangfei Gao } else { 759f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 769f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 779f5d71e4SZhangfei Gao tmp |= CLK_GATE_SETTING_BITS; 789f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 799f5d71e4SZhangfei Gao } 809f5d71e4SZhangfei Gao } 819f5d71e4SZhangfei Gao } 829f5d71e4SZhangfei Gao 83*7f7a201aSDoug Brown static u16 pxav1_readw(struct sdhci_host *host, int reg) 84*7f7a201aSDoug Brown { 85*7f7a201aSDoug Brown /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ 86*7f7a201aSDoug Brown if (reg == SDHCI_HOST_VERSION) 87*7f7a201aSDoug Brown return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; 88*7f7a201aSDoug Brown 89*7f7a201aSDoug Brown return readw(host->ioaddr + reg); 90*7f7a201aSDoug Brown } 91*7f7a201aSDoug Brown 922317f56cSRussell King static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) 939f5d71e4SZhangfei Gao { 949f5d71e4SZhangfei Gao u8 ctrl; 959f5d71e4SZhangfei Gao u16 tmp; 969f5d71e4SZhangfei Gao 979f5d71e4SZhangfei Gao ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 989f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CE_ATA_2); 999f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_8) { 1009f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1019f5d71e4SZhangfei Gao tmp |= MMC_CARD | MMC_WIDTH; 1029f5d71e4SZhangfei Gao } else { 1039f5d71e4SZhangfei Gao tmp &= ~(MMC_CARD | MMC_WIDTH); 1049f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_4) 1059f5d71e4SZhangfei Gao ctrl |= SDHCI_CTRL_4BITBUS; 1069f5d71e4SZhangfei Gao else 1079f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1089f5d71e4SZhangfei Gao } 1099f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CE_ATA_2); 1109f5d71e4SZhangfei Gao writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 1119f5d71e4SZhangfei Gao } 1129f5d71e4SZhangfei Gao 113dfe9746aSDoug Brown struct sdhci_pxa_variant { 114dfe9746aSDoug Brown const struct sdhci_ops *ops; 115dfe9746aSDoug Brown unsigned int extra_quirks; 116dfe9746aSDoug Brown }; 117dfe9746aSDoug Brown 118dfe9746aSDoug Brown static const struct sdhci_ops pxav1_sdhci_ops = { 119*7f7a201aSDoug Brown .read_w = pxav1_readw, 120dfe9746aSDoug Brown .set_clock = sdhci_set_clock, 121dfe9746aSDoug Brown .get_max_clock = sdhci_pltfm_clk_get_max_clock, 122dfe9746aSDoug Brown .set_bus_width = pxav2_mmc_set_bus_width, 123dfe9746aSDoug Brown .reset = pxav2_reset, 124dfe9746aSDoug Brown .set_uhs_signaling = sdhci_set_uhs_signaling, 125dfe9746aSDoug Brown }; 126dfe9746aSDoug Brown 127dfe9746aSDoug Brown static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { 128dfe9746aSDoug Brown .ops = &pxav1_sdhci_ops, 129dfe9746aSDoug Brown .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE, 130dfe9746aSDoug Brown }; 131dfe9746aSDoug Brown 132c915568dSLars-Peter Clausen static const struct sdhci_ops pxav2_sdhci_ops = { 1331771059cSRussell King .set_clock = sdhci_set_clock, 134d005d943SLars-Peter Clausen .get_max_clock = sdhci_pltfm_clk_get_max_clock, 1352317f56cSRussell King .set_bus_width = pxav2_mmc_set_bus_width, 13603231f9bSRussell King .reset = pxav2_reset, 13796d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 1389f5d71e4SZhangfei Gao }; 1399f5d71e4SZhangfei Gao 140dfe9746aSDoug Brown static const struct sdhci_pxa_variant pxav2_variant = { 141dfe9746aSDoug Brown .ops = &pxav2_sdhci_ops, 142dfe9746aSDoug Brown }; 143dfe9746aSDoug Brown 144b650352dSChris Ball #ifdef CONFIG_OF 145b650352dSChris Ball static const struct of_device_id sdhci_pxav2_of_match[] = { 146dfe9746aSDoug Brown { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, }, 147dfe9746aSDoug Brown { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, }, 148b650352dSChris Ball {}, 149b650352dSChris Ball }; 150b650352dSChris Ball MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); 151b650352dSChris Ball 152b650352dSChris Ball static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 153b650352dSChris Ball { 154b650352dSChris Ball struct sdhci_pxa_platdata *pdata; 155b650352dSChris Ball struct device_node *np = dev->of_node; 156b650352dSChris Ball u32 bus_width; 157b650352dSChris Ball u32 clk_delay_cycles; 158b650352dSChris Ball 159b650352dSChris Ball pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 160b650352dSChris Ball if (!pdata) 161b650352dSChris Ball return NULL; 162b650352dSChris Ball 163b650352dSChris Ball if (of_find_property(np, "non-removable", NULL)) 164b650352dSChris Ball pdata->flags |= PXA_FLAG_CARD_PERMANENT; 165b650352dSChris Ball 166b650352dSChris Ball of_property_read_u32(np, "bus-width", &bus_width); 167b650352dSChris Ball if (bus_width == 8) 168b650352dSChris Ball pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 169b650352dSChris Ball 170b650352dSChris Ball of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 171b650352dSChris Ball if (clk_delay_cycles > 0) { 172b650352dSChris Ball pdata->clk_delay_sel = 1; 173b650352dSChris Ball pdata->clk_delay_cycles = clk_delay_cycles; 174b650352dSChris Ball } 175b650352dSChris Ball 176b650352dSChris Ball return pdata; 177b650352dSChris Ball } 178b650352dSChris Ball #else 179b650352dSChris Ball static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 180b650352dSChris Ball { 181b650352dSChris Ball return NULL; 182b650352dSChris Ball } 183b650352dSChris Ball #endif 184b650352dSChris Ball 185c3be1efdSBill Pemberton static int sdhci_pxav2_probe(struct platform_device *pdev) 1869f5d71e4SZhangfei Gao { 1879f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host; 1889f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 1899f5d71e4SZhangfei Gao struct device *dev = &pdev->dev; 1909f5d71e4SZhangfei Gao struct sdhci_host *host = NULL; 191dfe9746aSDoug Brown const struct sdhci_pxa_variant *variant; 192b650352dSChris Ball 1939f5d71e4SZhangfei Gao int ret; 1949f5d71e4SZhangfei Gao struct clk *clk; 1959f5d71e4SZhangfei Gao 1960e748234SChristian Daudt host = sdhci_pltfm_init(pdev, NULL, 0); 1976a686c31SSebastian Hesselbarth if (IS_ERR(host)) 1989f5d71e4SZhangfei Gao return PTR_ERR(host); 1996a686c31SSebastian Hesselbarth 2009f5d71e4SZhangfei Gao pltfm_host = sdhci_priv(host); 2019f5d71e4SZhangfei Gao 2023fd1d86fSMasahiro Yamada clk = devm_clk_get(dev, "PXA-SDHCLK"); 2039f5d71e4SZhangfei Gao if (IS_ERR(clk)) { 2049f5d71e4SZhangfei Gao dev_err(dev, "failed to get io clock\n"); 2059f5d71e4SZhangfei Gao ret = PTR_ERR(clk); 2063fd1d86fSMasahiro Yamada goto free; 2079f5d71e4SZhangfei Gao } 2089f5d71e4SZhangfei Gao pltfm_host->clk = clk; 20921b22284SAlexey Khoroshilov ret = clk_prepare_enable(clk); 21021b22284SAlexey Khoroshilov if (ret) { 21121b22284SAlexey Khoroshilov dev_err(&pdev->dev, "failed to enable io clock\n"); 2123fd1d86fSMasahiro Yamada goto free; 21321b22284SAlexey Khoroshilov } 2149f5d71e4SZhangfei Gao 2159f5d71e4SZhangfei Gao host->quirks = SDHCI_QUIRK_BROKEN_ADMA 2169f5d71e4SZhangfei Gao | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 2179f5d71e4SZhangfei Gao | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 2189f5d71e4SZhangfei Gao 219dfe9746aSDoug Brown variant = of_device_get_match_data(dev); 220dfe9746aSDoug Brown if (variant) 221b650352dSChris Ball pdata = pxav2_get_mmc_pdata(dev); 222dfe9746aSDoug Brown else 223dfe9746aSDoug Brown variant = &pxav2_variant; 224dfe9746aSDoug Brown 2259f5d71e4SZhangfei Gao if (pdata) { 2269f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 2279f5d71e4SZhangfei Gao /* on-chip device */ 2289f5d71e4SZhangfei Gao host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 2299f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_NONREMOVABLE; 2309f5d71e4SZhangfei Gao } 2319f5d71e4SZhangfei Gao 2329f5d71e4SZhangfei Gao /* If slot design supports 8 bit data, indicate this to MMC. */ 2339f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 2349f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_8_BIT_DATA; 2359f5d71e4SZhangfei Gao 2369f5d71e4SZhangfei Gao if (pdata->quirks) 2379f5d71e4SZhangfei Gao host->quirks |= pdata->quirks; 2389f5d71e4SZhangfei Gao if (pdata->host_caps) 2399f5d71e4SZhangfei Gao host->mmc->caps |= pdata->host_caps; 2409f5d71e4SZhangfei Gao if (pdata->pm_caps) 2419f5d71e4SZhangfei Gao host->mmc->pm_caps |= pdata->pm_caps; 2429f5d71e4SZhangfei Gao } 2439f5d71e4SZhangfei Gao 244dfe9746aSDoug Brown host->quirks |= variant->extra_quirks; 245dfe9746aSDoug Brown host->ops = variant->ops; 2469f5d71e4SZhangfei Gao 2479f5d71e4SZhangfei Gao ret = sdhci_add_host(host); 248fb8617e1SJisheng Zhang if (ret) 2493fd1d86fSMasahiro Yamada goto disable_clk; 2509f5d71e4SZhangfei Gao 2519f5d71e4SZhangfei Gao return 0; 2529f5d71e4SZhangfei Gao 2533fd1d86fSMasahiro Yamada disable_clk: 254164378efSChao Xie clk_disable_unprepare(clk); 2553fd1d86fSMasahiro Yamada free: 2569f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 2579f5d71e4SZhangfei Gao return ret; 2589f5d71e4SZhangfei Gao } 2599f5d71e4SZhangfei Gao 2609f5d71e4SZhangfei Gao static struct platform_driver sdhci_pxav2_driver = { 2619f5d71e4SZhangfei Gao .driver = { 2629f5d71e4SZhangfei Gao .name = "sdhci-pxav2", 26321b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 26459d22309SAxel Lin .of_match_table = of_match_ptr(sdhci_pxav2_of_match), 265fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops, 2669f5d71e4SZhangfei Gao }, 2679f5d71e4SZhangfei Gao .probe = sdhci_pxav2_probe, 2683fd1d86fSMasahiro Yamada .remove = sdhci_pltfm_unregister, 2699f5d71e4SZhangfei Gao }; 2709f5d71e4SZhangfei Gao 271d1f81a64SAxel Lin module_platform_driver(sdhci_pxav2_driver); 2729f5d71e4SZhangfei Gao 2739f5d71e4SZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav2"); 2749f5d71e4SZhangfei Gao MODULE_AUTHOR("Marvell International Ltd."); 2759f5d71e4SZhangfei Gao MODULE_LICENSE("GPL v2"); 2769f5d71e4SZhangfei Gao 277