19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 29f5d71e4SZhangfei Gao /* 39f5d71e4SZhangfei Gao * Copyright (C) 2010 Marvell International Ltd. 49f5d71e4SZhangfei Gao * Zhangfei Gao <zhangfei.gao@marvell.com> 59f5d71e4SZhangfei Gao * Kevin Wang <dwang4@marvell.com> 69f5d71e4SZhangfei Gao * Jun Nie <njun@marvell.com> 79f5d71e4SZhangfei Gao * Qiming Wu <wuqm@marvell.com> 89f5d71e4SZhangfei Gao * Philip Rakity <prakity@marvell.com> 99f5d71e4SZhangfei Gao */ 109f5d71e4SZhangfei Gao 119f5d71e4SZhangfei Gao #include <linux/err.h> 129f5d71e4SZhangfei Gao #include <linux/init.h> 139f5d71e4SZhangfei Gao #include <linux/platform_device.h> 149f5d71e4SZhangfei Gao #include <linux/clk.h> 1588b47679SPaul Gortmaker #include <linux/module.h> 169f5d71e4SZhangfei Gao #include <linux/io.h> 179f5d71e4SZhangfei Gao #include <linux/mmc/card.h> 189f5d71e4SZhangfei Gao #include <linux/mmc/host.h> 19bfed345eSZhangfei Gao #include <linux/platform_data/pxa_sdhci.h> 209f5d71e4SZhangfei Gao #include <linux/slab.h> 21b650352dSChris Ball #include <linux/of.h> 22b650352dSChris Ball #include <linux/of_device.h> 23*24552ccbSDoug Brown #include <linux/mmc/sdio.h> 24*24552ccbSDoug Brown #include <linux/mmc/mmc.h> 25b650352dSChris Ball 269f5d71e4SZhangfei Gao #include "sdhci.h" 279f5d71e4SZhangfei Gao #include "sdhci-pltfm.h" 289f5d71e4SZhangfei Gao 299f5d71e4SZhangfei Gao #define SD_FIFO_PARAM 0xe0 309f5d71e4SZhangfei Gao #define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ 319f5d71e4SZhangfei Gao #define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ 329f5d71e4SZhangfei Gao #define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ 339f5d71e4SZhangfei Gao #define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ 349f5d71e4SZhangfei Gao CLK_GATE_ON | CLK_GATE_CTL) 359f5d71e4SZhangfei Gao 369f5d71e4SZhangfei Gao #define SD_CLOCK_BURST_SIZE_SETUP 0xe6 379f5d71e4SZhangfei Gao #define SDCLK_SEL_SHIFT 8 389f5d71e4SZhangfei Gao #define SDCLK_SEL_MASK 0x3 399f5d71e4SZhangfei Gao #define SDCLK_DELAY_SHIFT 10 409f5d71e4SZhangfei Gao #define SDCLK_DELAY_MASK 0x3c 419f5d71e4SZhangfei Gao 429f5d71e4SZhangfei Gao #define SD_CE_ATA_2 0xea 439f5d71e4SZhangfei Gao #define MMC_CARD 0x1000 449f5d71e4SZhangfei Gao #define MMC_WIDTH 0x0100 459f5d71e4SZhangfei Gao 46*24552ccbSDoug Brown struct sdhci_pxav2_host { 47*24552ccbSDoug Brown struct mmc_request *sdio_mrq; 48*24552ccbSDoug Brown }; 49*24552ccbSDoug Brown 5003231f9bSRussell King static void pxav2_reset(struct sdhci_host *host, u8 mask) 519f5d71e4SZhangfei Gao { 529f5d71e4SZhangfei Gao struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 539f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 549f5d71e4SZhangfei Gao 5503231f9bSRussell King sdhci_reset(host, mask); 5603231f9bSRussell King 579f5d71e4SZhangfei Gao if (mask == SDHCI_RESET_ALL) { 589f5d71e4SZhangfei Gao u16 tmp = 0; 599f5d71e4SZhangfei Gao 609f5d71e4SZhangfei Gao /* 619f5d71e4SZhangfei Gao * tune timing of read data/command when crc error happen 629f5d71e4SZhangfei Gao * no performance impact 639f5d71e4SZhangfei Gao */ 64329f2237STanmay Upadhyay if (pdata && pdata->clk_delay_sel == 1) { 659f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 669f5d71e4SZhangfei Gao 679f5d71e4SZhangfei Gao tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); 689f5d71e4SZhangfei Gao tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 699f5d71e4SZhangfei Gao << SDCLK_DELAY_SHIFT; 709f5d71e4SZhangfei Gao tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); 719f5d71e4SZhangfei Gao tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; 729f5d71e4SZhangfei Gao 739f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 749f5d71e4SZhangfei Gao } 759f5d71e4SZhangfei Gao 76329f2237STanmay Upadhyay if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { 779f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 789f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 799f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 809f5d71e4SZhangfei Gao } else { 819f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_FIFO_PARAM); 829f5d71e4SZhangfei Gao tmp &= ~CLK_GATE_SETTING_BITS; 839f5d71e4SZhangfei Gao tmp |= CLK_GATE_SETTING_BITS; 849f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_FIFO_PARAM); 859f5d71e4SZhangfei Gao } 869f5d71e4SZhangfei Gao } 879f5d71e4SZhangfei Gao } 889f5d71e4SZhangfei Gao 897f7a201aSDoug Brown static u16 pxav1_readw(struct sdhci_host *host, int reg) 907f7a201aSDoug Brown { 917f7a201aSDoug Brown /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ 927f7a201aSDoug Brown if (reg == SDHCI_HOST_VERSION) 937f7a201aSDoug Brown return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; 947f7a201aSDoug Brown 957f7a201aSDoug Brown return readw(host->ioaddr + reg); 967f7a201aSDoug Brown } 977f7a201aSDoug Brown 98*24552ccbSDoug Brown static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) 99*24552ccbSDoug Brown { 100*24552ccbSDoug Brown struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); 101*24552ccbSDoug Brown struct mmc_request *sdio_mrq; 102*24552ccbSDoug Brown 103*24552ccbSDoug Brown if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) { 104*24552ccbSDoug Brown /* The dummy CMD0 for the SDIO workaround just completed */ 105*24552ccbSDoug Brown sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); 106*24552ccbSDoug Brown intmask &= ~SDHCI_INT_CMD_MASK; 107*24552ccbSDoug Brown sdio_mrq = pxav2_host->sdio_mrq; 108*24552ccbSDoug Brown pxav2_host->sdio_mrq = NULL; 109*24552ccbSDoug Brown mmc_request_done(host->mmc, sdio_mrq); 110*24552ccbSDoug Brown } 111*24552ccbSDoug Brown 112*24552ccbSDoug Brown return intmask; 113*24552ccbSDoug Brown } 114*24552ccbSDoug Brown 115*24552ccbSDoug Brown static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) 116*24552ccbSDoug Brown { 117*24552ccbSDoug Brown u16 tmp; 118*24552ccbSDoug Brown struct sdhci_pxav2_host *pxav2_host; 119*24552ccbSDoug Brown 120*24552ccbSDoug Brown /* If this is an SDIO command, perform errata workaround for silicon bug */ 121*24552ccbSDoug Brown if (mrq->cmd && !mrq->cmd->error && 122*24552ccbSDoug Brown (mrq->cmd->opcode == SD_IO_RW_DIRECT || 123*24552ccbSDoug Brown mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { 124*24552ccbSDoug Brown /* Reset data port */ 125*24552ccbSDoug Brown tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); 126*24552ccbSDoug Brown tmp |= 0x400; 127*24552ccbSDoug Brown writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL); 128*24552ccbSDoug Brown 129*24552ccbSDoug Brown /* Clock is now stopped, so restart it by sending a dummy CMD0 */ 130*24552ccbSDoug Brown pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); 131*24552ccbSDoug Brown pxav2_host->sdio_mrq = mrq; 132*24552ccbSDoug Brown sdhci_writel(host, 0, SDHCI_ARGUMENT); 133*24552ccbSDoug Brown sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); 134*24552ccbSDoug Brown sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), 135*24552ccbSDoug Brown SDHCI_COMMAND); 136*24552ccbSDoug Brown 137*24552ccbSDoug Brown /* Don't finish this request until the dummy CMD0 finishes */ 138*24552ccbSDoug Brown return; 139*24552ccbSDoug Brown } 140*24552ccbSDoug Brown 141*24552ccbSDoug Brown mmc_request_done(host->mmc, mrq); 142*24552ccbSDoug Brown } 143*24552ccbSDoug Brown 1442317f56cSRussell King static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) 1459f5d71e4SZhangfei Gao { 1469f5d71e4SZhangfei Gao u8 ctrl; 1479f5d71e4SZhangfei Gao u16 tmp; 1489f5d71e4SZhangfei Gao 1499f5d71e4SZhangfei Gao ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 1509f5d71e4SZhangfei Gao tmp = readw(host->ioaddr + SD_CE_ATA_2); 1519f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_8) { 1529f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1539f5d71e4SZhangfei Gao tmp |= MMC_CARD | MMC_WIDTH; 1549f5d71e4SZhangfei Gao } else { 1559f5d71e4SZhangfei Gao tmp &= ~(MMC_CARD | MMC_WIDTH); 1569f5d71e4SZhangfei Gao if (width == MMC_BUS_WIDTH_4) 1579f5d71e4SZhangfei Gao ctrl |= SDHCI_CTRL_4BITBUS; 1589f5d71e4SZhangfei Gao else 1599f5d71e4SZhangfei Gao ctrl &= ~SDHCI_CTRL_4BITBUS; 1609f5d71e4SZhangfei Gao } 1619f5d71e4SZhangfei Gao writew(tmp, host->ioaddr + SD_CE_ATA_2); 1629f5d71e4SZhangfei Gao writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); 1639f5d71e4SZhangfei Gao } 1649f5d71e4SZhangfei Gao 165dfe9746aSDoug Brown struct sdhci_pxa_variant { 166dfe9746aSDoug Brown const struct sdhci_ops *ops; 167dfe9746aSDoug Brown unsigned int extra_quirks; 168dfe9746aSDoug Brown }; 169dfe9746aSDoug Brown 170dfe9746aSDoug Brown static const struct sdhci_ops pxav1_sdhci_ops = { 1717f7a201aSDoug Brown .read_w = pxav1_readw, 172dfe9746aSDoug Brown .set_clock = sdhci_set_clock, 173*24552ccbSDoug Brown .irq = pxav1_irq, 174dfe9746aSDoug Brown .get_max_clock = sdhci_pltfm_clk_get_max_clock, 175dfe9746aSDoug Brown .set_bus_width = pxav2_mmc_set_bus_width, 176dfe9746aSDoug Brown .reset = pxav2_reset, 177dfe9746aSDoug Brown .set_uhs_signaling = sdhci_set_uhs_signaling, 178*24552ccbSDoug Brown .request_done = pxav1_request_done, 179dfe9746aSDoug Brown }; 180dfe9746aSDoug Brown 181dfe9746aSDoug Brown static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { 182dfe9746aSDoug Brown .ops = &pxav1_sdhci_ops, 183dfe9746aSDoug Brown .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE, 184dfe9746aSDoug Brown }; 185dfe9746aSDoug Brown 186c915568dSLars-Peter Clausen static const struct sdhci_ops pxav2_sdhci_ops = { 1871771059cSRussell King .set_clock = sdhci_set_clock, 188d005d943SLars-Peter Clausen .get_max_clock = sdhci_pltfm_clk_get_max_clock, 1892317f56cSRussell King .set_bus_width = pxav2_mmc_set_bus_width, 19003231f9bSRussell King .reset = pxav2_reset, 19196d7b78cSRussell King .set_uhs_signaling = sdhci_set_uhs_signaling, 1929f5d71e4SZhangfei Gao }; 1939f5d71e4SZhangfei Gao 194dfe9746aSDoug Brown static const struct sdhci_pxa_variant pxav2_variant = { 195dfe9746aSDoug Brown .ops = &pxav2_sdhci_ops, 196dfe9746aSDoug Brown }; 197dfe9746aSDoug Brown 198b650352dSChris Ball #ifdef CONFIG_OF 199b650352dSChris Ball static const struct of_device_id sdhci_pxav2_of_match[] = { 200dfe9746aSDoug Brown { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, }, 201dfe9746aSDoug Brown { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, }, 202b650352dSChris Ball {}, 203b650352dSChris Ball }; 204b650352dSChris Ball MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); 205b650352dSChris Ball 206b650352dSChris Ball static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 207b650352dSChris Ball { 208b650352dSChris Ball struct sdhci_pxa_platdata *pdata; 209b650352dSChris Ball struct device_node *np = dev->of_node; 210b650352dSChris Ball u32 bus_width; 211b650352dSChris Ball u32 clk_delay_cycles; 212b650352dSChris Ball 213b650352dSChris Ball pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 214b650352dSChris Ball if (!pdata) 215b650352dSChris Ball return NULL; 216b650352dSChris Ball 217b650352dSChris Ball if (of_find_property(np, "non-removable", NULL)) 218b650352dSChris Ball pdata->flags |= PXA_FLAG_CARD_PERMANENT; 219b650352dSChris Ball 220b650352dSChris Ball of_property_read_u32(np, "bus-width", &bus_width); 221b650352dSChris Ball if (bus_width == 8) 222b650352dSChris Ball pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; 223b650352dSChris Ball 224b650352dSChris Ball of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); 225b650352dSChris Ball if (clk_delay_cycles > 0) { 226b650352dSChris Ball pdata->clk_delay_sel = 1; 227b650352dSChris Ball pdata->clk_delay_cycles = clk_delay_cycles; 228b650352dSChris Ball } 229b650352dSChris Ball 230b650352dSChris Ball return pdata; 231b650352dSChris Ball } 232b650352dSChris Ball #else 233b650352dSChris Ball static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev) 234b650352dSChris Ball { 235b650352dSChris Ball return NULL; 236b650352dSChris Ball } 237b650352dSChris Ball #endif 238b650352dSChris Ball 239c3be1efdSBill Pemberton static int sdhci_pxav2_probe(struct platform_device *pdev) 2409f5d71e4SZhangfei Gao { 2419f5d71e4SZhangfei Gao struct sdhci_pltfm_host *pltfm_host; 2429f5d71e4SZhangfei Gao struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 2439f5d71e4SZhangfei Gao struct device *dev = &pdev->dev; 2449f5d71e4SZhangfei Gao struct sdhci_host *host = NULL; 245dfe9746aSDoug Brown const struct sdhci_pxa_variant *variant; 246b650352dSChris Ball 2479f5d71e4SZhangfei Gao int ret; 248e41c48b4SDoug Brown struct clk *clk, *clk_core; 2499f5d71e4SZhangfei Gao 250*24552ccbSDoug Brown host = sdhci_pltfm_init(pdev, NULL, sizeof(struct sdhci_pxav2_host)); 2516a686c31SSebastian Hesselbarth if (IS_ERR(host)) 2529f5d71e4SZhangfei Gao return PTR_ERR(host); 2536a686c31SSebastian Hesselbarth 2549f5d71e4SZhangfei Gao pltfm_host = sdhci_priv(host); 2559f5d71e4SZhangfei Gao 256c7c60bf6SDoug Brown clk = devm_clk_get(dev, "io"); 257c7c60bf6SDoug Brown if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER) 258c7c60bf6SDoug Brown clk = devm_clk_get(dev, NULL); 2599f5d71e4SZhangfei Gao if (IS_ERR(clk)) { 2609f5d71e4SZhangfei Gao ret = PTR_ERR(clk); 261c7c60bf6SDoug Brown dev_err_probe(dev, ret, "failed to get io clock\n"); 2623fd1d86fSMasahiro Yamada goto free; 2639f5d71e4SZhangfei Gao } 2649f5d71e4SZhangfei Gao pltfm_host->clk = clk; 26521b22284SAlexey Khoroshilov ret = clk_prepare_enable(clk); 26621b22284SAlexey Khoroshilov if (ret) { 267c7c60bf6SDoug Brown dev_err(dev, "failed to enable io clock\n"); 2683fd1d86fSMasahiro Yamada goto free; 26921b22284SAlexey Khoroshilov } 2709f5d71e4SZhangfei Gao 271e41c48b4SDoug Brown clk_core = devm_clk_get_optional_enabled(dev, "core"); 272e41c48b4SDoug Brown if (IS_ERR(clk_core)) { 273e41c48b4SDoug Brown ret = PTR_ERR(clk_core); 274e41c48b4SDoug Brown dev_err_probe(dev, ret, "failed to enable core clock\n"); 275e41c48b4SDoug Brown goto disable_clk; 276e41c48b4SDoug Brown } 277e41c48b4SDoug Brown 2789f5d71e4SZhangfei Gao host->quirks = SDHCI_QUIRK_BROKEN_ADMA 2799f5d71e4SZhangfei Gao | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 2809f5d71e4SZhangfei Gao | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 2819f5d71e4SZhangfei Gao 282dfe9746aSDoug Brown variant = of_device_get_match_data(dev); 283dfe9746aSDoug Brown if (variant) 284b650352dSChris Ball pdata = pxav2_get_mmc_pdata(dev); 285dfe9746aSDoug Brown else 286dfe9746aSDoug Brown variant = &pxav2_variant; 287dfe9746aSDoug Brown 2889f5d71e4SZhangfei Gao if (pdata) { 2899f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { 2909f5d71e4SZhangfei Gao /* on-chip device */ 2919f5d71e4SZhangfei Gao host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 2929f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_NONREMOVABLE; 2939f5d71e4SZhangfei Gao } 2949f5d71e4SZhangfei Gao 2959f5d71e4SZhangfei Gao /* If slot design supports 8 bit data, indicate this to MMC. */ 2969f5d71e4SZhangfei Gao if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 2979f5d71e4SZhangfei Gao host->mmc->caps |= MMC_CAP_8_BIT_DATA; 2989f5d71e4SZhangfei Gao 2999f5d71e4SZhangfei Gao if (pdata->quirks) 3009f5d71e4SZhangfei Gao host->quirks |= pdata->quirks; 3019f5d71e4SZhangfei Gao if (pdata->host_caps) 3029f5d71e4SZhangfei Gao host->mmc->caps |= pdata->host_caps; 3039f5d71e4SZhangfei Gao if (pdata->pm_caps) 3049f5d71e4SZhangfei Gao host->mmc->pm_caps |= pdata->pm_caps; 3059f5d71e4SZhangfei Gao } 3069f5d71e4SZhangfei Gao 307dfe9746aSDoug Brown host->quirks |= variant->extra_quirks; 308dfe9746aSDoug Brown host->ops = variant->ops; 3099f5d71e4SZhangfei Gao 3109f5d71e4SZhangfei Gao ret = sdhci_add_host(host); 311fb8617e1SJisheng Zhang if (ret) 3123fd1d86fSMasahiro Yamada goto disable_clk; 3139f5d71e4SZhangfei Gao 3149f5d71e4SZhangfei Gao return 0; 3159f5d71e4SZhangfei Gao 3163fd1d86fSMasahiro Yamada disable_clk: 317164378efSChao Xie clk_disable_unprepare(clk); 3183fd1d86fSMasahiro Yamada free: 3199f5d71e4SZhangfei Gao sdhci_pltfm_free(pdev); 3209f5d71e4SZhangfei Gao return ret; 3219f5d71e4SZhangfei Gao } 3229f5d71e4SZhangfei Gao 3239f5d71e4SZhangfei Gao static struct platform_driver sdhci_pxav2_driver = { 3249f5d71e4SZhangfei Gao .driver = { 3259f5d71e4SZhangfei Gao .name = "sdhci-pxav2", 32621b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 32759d22309SAxel Lin .of_match_table = of_match_ptr(sdhci_pxav2_of_match), 328fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops, 3299f5d71e4SZhangfei Gao }, 3309f5d71e4SZhangfei Gao .probe = sdhci_pxav2_probe, 3313fd1d86fSMasahiro Yamada .remove = sdhci_pltfm_unregister, 3329f5d71e4SZhangfei Gao }; 3339f5d71e4SZhangfei Gao 334d1f81a64SAxel Lin module_platform_driver(sdhci_pxav2_driver); 3359f5d71e4SZhangfei Gao 3369f5d71e4SZhangfei Gao MODULE_DESCRIPTION("SDHCI driver for pxav2"); 3379f5d71e4SZhangfei Gao MODULE_AUTHOR("Marvell International Ltd."); 3389f5d71e4SZhangfei Gao MODULE_LICENSE("GPL v2"); 3399f5d71e4SZhangfei Gao 340