1 /* 2 * Copyright 2010 MontaVista Software, LLC. 3 * 4 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H 12 #define _DRIVERS_MMC_SDHCI_PLTFM_H 13 14 #include <linux/clk.h> 15 #include <linux/platform_device.h> 16 #include "sdhci.h" 17 18 struct sdhci_pltfm_data { 19 struct sdhci_ops *ops; 20 unsigned int quirks; 21 }; 22 23 struct sdhci_pltfm_host { 24 struct clk *clk; 25 void *priv; /* to handle quirks across io-accessor calls */ 26 27 /* migrate from sdhci_of_host */ 28 unsigned int clock; 29 u16 xfer_mode_shadow; 30 }; 31 32 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER 33 /* 34 * These accessors are designed for big endian hosts doing I/O to 35 * little endian controllers incorporating a 32-bit hardware byte swapper. 36 */ 37 static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) 38 { 39 return in_be32(host->ioaddr + reg); 40 } 41 42 static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) 43 { 44 return in_be16(host->ioaddr + (reg ^ 0x2)); 45 } 46 47 static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) 48 { 49 return in_8(host->ioaddr + (reg ^ 0x3)); 50 } 51 52 static inline void sdhci_be32bs_writel(struct sdhci_host *host, 53 u32 val, int reg) 54 { 55 out_be32(host->ioaddr + reg, val); 56 } 57 58 static inline void sdhci_be32bs_writew(struct sdhci_host *host, 59 u16 val, int reg) 60 { 61 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 62 int base = reg & ~0x3; 63 int shift = (reg & 0x2) * 8; 64 65 switch (reg) { 66 case SDHCI_TRANSFER_MODE: 67 /* 68 * Postpone this write, we must do it together with a 69 * command write that is down below. 70 */ 71 pltfm_host->xfer_mode_shadow = val; 72 return; 73 case SDHCI_COMMAND: 74 sdhci_be32bs_writel(host, 75 val << 16 | pltfm_host->xfer_mode_shadow, 76 SDHCI_TRANSFER_MODE); 77 return; 78 } 79 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); 80 } 81 82 static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) 83 { 84 int base = reg & ~0x3; 85 int shift = (reg & 0x3) * 8; 86 87 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); 88 } 89 #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */ 90 91 extern void sdhci_get_of_property(struct platform_device *pdev); 92 93 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, 94 struct sdhci_pltfm_data *pdata); 95 extern void sdhci_pltfm_free(struct platform_device *pdev); 96 97 extern int sdhci_pltfm_register(struct platform_device *pdev, 98 struct sdhci_pltfm_data *pdata); 99 extern int sdhci_pltfm_unregister(struct platform_device *pdev); 100 101 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host); 102 103 #ifdef CONFIG_PM 104 extern const struct dev_pm_ops sdhci_pltfm_pmops; 105 #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops) 106 #else 107 #define SDHCI_PLTFM_PMOPS NULL 108 #endif 109 110 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ 111