1 /* 2 * Copyright 2010 MontaVista Software, LLC. 3 * 4 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H 12 #define _DRIVERS_MMC_SDHCI_PLTFM_H 13 14 #include <linux/clk.h> 15 #include <linux/platform_device.h> 16 #include "sdhci.h" 17 18 struct sdhci_pltfm_data { 19 const struct sdhci_ops *ops; 20 unsigned int quirks; 21 unsigned int quirks2; 22 }; 23 24 struct sdhci_pltfm_host { 25 struct clk *clk; 26 void *priv; /* to handle quirks across io-accessor calls */ 27 28 /* migrate from sdhci_of_host */ 29 unsigned int clock; 30 u16 xfer_mode_shadow; 31 32 unsigned long private[0] ____cacheline_aligned; 33 }; 34 35 #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER 36 /* 37 * These accessors are designed for big endian hosts doing I/O to 38 * little endian controllers incorporating a 32-bit hardware byte swapper. 39 */ 40 static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) 41 { 42 return in_be32(host->ioaddr + reg); 43 } 44 45 static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) 46 { 47 return in_be16(host->ioaddr + (reg ^ 0x2)); 48 } 49 50 static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) 51 { 52 return in_8(host->ioaddr + (reg ^ 0x3)); 53 } 54 55 static inline void sdhci_be32bs_writel(struct sdhci_host *host, 56 u32 val, int reg) 57 { 58 out_be32(host->ioaddr + reg, val); 59 } 60 61 static inline void sdhci_be32bs_writew(struct sdhci_host *host, 62 u16 val, int reg) 63 { 64 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 65 int base = reg & ~0x3; 66 int shift = (reg & 0x2) * 8; 67 68 switch (reg) { 69 case SDHCI_TRANSFER_MODE: 70 /* 71 * Postpone this write, we must do it together with a 72 * command write that is down below. 73 */ 74 pltfm_host->xfer_mode_shadow = val; 75 return; 76 case SDHCI_COMMAND: 77 sdhci_be32bs_writel(host, 78 val << 16 | pltfm_host->xfer_mode_shadow, 79 SDHCI_TRANSFER_MODE); 80 return; 81 } 82 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); 83 } 84 85 static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) 86 { 87 int base = reg & ~0x3; 88 int shift = (reg & 0x3) * 8; 89 90 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); 91 } 92 #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */ 93 94 extern void sdhci_get_of_property(struct platform_device *pdev); 95 96 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, 97 const struct sdhci_pltfm_data *pdata, 98 size_t priv_size); 99 extern void sdhci_pltfm_free(struct platform_device *pdev); 100 101 extern int sdhci_pltfm_register(struct platform_device *pdev, 102 const struct sdhci_pltfm_data *pdata, 103 size_t priv_size); 104 extern int sdhci_pltfm_unregister(struct platform_device *pdev); 105 106 extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host); 107 108 static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host) 109 { 110 return (void *)host->private; 111 } 112 113 #ifdef CONFIG_PM 114 extern int sdhci_pltfm_suspend(struct device *dev); 115 extern int sdhci_pltfm_resume(struct device *dev); 116 extern const struct dev_pm_ops sdhci_pltfm_pmops; 117 #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops) 118 #else 119 #define SDHCI_PLTFM_PMOPS NULL 120 #endif 121 122 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ 123