1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2515033f9SAnton Vorontsov /* 3515033f9SAnton Vorontsov * Copyright 2010 MontaVista Software, LLC. 4515033f9SAnton Vorontsov * 5515033f9SAnton Vorontsov * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 6515033f9SAnton Vorontsov */ 7515033f9SAnton Vorontsov 8515033f9SAnton Vorontsov #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H 9515033f9SAnton Vorontsov #define _DRIVERS_MMC_SDHCI_PLTFM_H 10515033f9SAnton Vorontsov 114b711cb1SWolfram Sang #include <linux/clk.h> 1285d6509dSShawn Guo #include <linux/platform_device.h> 13f0de8369SShawn Guo #include "sdhci.h" 1420b1597bSAnton Vorontsov 1594cc6a86SShawn Guo struct sdhci_pltfm_data { 16ad1df8c2SLars-Peter Clausen const struct sdhci_ops *ops; 1794cc6a86SShawn Guo unsigned int quirks; 18ad82ab65SAl Cooper unsigned int quirks2; 1994cc6a86SShawn Guo }; 2094cc6a86SShawn Guo 214b711cb1SWolfram Sang struct sdhci_pltfm_host { 224b711cb1SWolfram Sang struct clk *clk; 23e307148fSShawn Guo 24e307148fSShawn Guo /* migrate from sdhci_of_host */ 25e307148fSShawn Guo unsigned int clock; 26e307148fSShawn Guo u16 xfer_mode_shadow; 270e748234SChristian Daudt 281a91a36aSGustavo A. R. Silva unsigned long private[] ____cacheline_aligned; 294b711cb1SWolfram Sang }; 304b711cb1SWolfram Sang 3138576af1SShawn Guo #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER 32f0de8369SShawn Guo /* 33f0de8369SShawn Guo * These accessors are designed for big endian hosts doing I/O to 34f0de8369SShawn Guo * little endian controllers incorporating a 32-bit hardware byte swapper. 35f0de8369SShawn Guo */ 36f0de8369SShawn Guo static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) 37f0de8369SShawn Guo { 38f0de8369SShawn Guo return in_be32(host->ioaddr + reg); 39f0de8369SShawn Guo } 40f0de8369SShawn Guo 41f0de8369SShawn Guo static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) 42f0de8369SShawn Guo { 43f0de8369SShawn Guo return in_be16(host->ioaddr + (reg ^ 0x2)); 44f0de8369SShawn Guo } 45f0de8369SShawn Guo 46f0de8369SShawn Guo static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) 47f0de8369SShawn Guo { 48f0de8369SShawn Guo return in_8(host->ioaddr + (reg ^ 0x3)); 49f0de8369SShawn Guo } 50f0de8369SShawn Guo 51f0de8369SShawn Guo static inline void sdhci_be32bs_writel(struct sdhci_host *host, 52f0de8369SShawn Guo u32 val, int reg) 53f0de8369SShawn Guo { 54f0de8369SShawn Guo out_be32(host->ioaddr + reg, val); 55f0de8369SShawn Guo } 56f0de8369SShawn Guo 57f0de8369SShawn Guo static inline void sdhci_be32bs_writew(struct sdhci_host *host, 58f0de8369SShawn Guo u16 val, int reg) 59f0de8369SShawn Guo { 60f0de8369SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 61f0de8369SShawn Guo int base = reg & ~0x3; 62f0de8369SShawn Guo int shift = (reg & 0x2) * 8; 63f0de8369SShawn Guo 64f0de8369SShawn Guo switch (reg) { 65f0de8369SShawn Guo case SDHCI_TRANSFER_MODE: 66f0de8369SShawn Guo /* 67f0de8369SShawn Guo * Postpone this write, we must do it together with a 68f0de8369SShawn Guo * command write that is down below. 69f0de8369SShawn Guo */ 70f0de8369SShawn Guo pltfm_host->xfer_mode_shadow = val; 71f0de8369SShawn Guo return; 72f0de8369SShawn Guo case SDHCI_COMMAND: 73f0de8369SShawn Guo sdhci_be32bs_writel(host, 74f0de8369SShawn Guo val << 16 | pltfm_host->xfer_mode_shadow, 75f0de8369SShawn Guo SDHCI_TRANSFER_MODE); 76f0de8369SShawn Guo return; 77f0de8369SShawn Guo } 78f0de8369SShawn Guo clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); 79f0de8369SShawn Guo } 80f0de8369SShawn Guo 81f0de8369SShawn Guo static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) 82f0de8369SShawn Guo { 83f0de8369SShawn Guo int base = reg & ~0x3; 84f0de8369SShawn Guo int shift = (reg & 0x3) * 8; 85f0de8369SShawn Guo 86f0de8369SShawn Guo clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); 87f0de8369SShawn Guo } 88f0de8369SShawn Guo #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */ 8938576af1SShawn Guo 908199d312SAdrian Hunter void sdhci_get_property(struct platform_device *pdev); 918199d312SAdrian Hunter 928199d312SAdrian Hunter static inline void sdhci_get_of_property(struct platform_device *pdev) 938199d312SAdrian Hunter { 948199d312SAdrian Hunter return sdhci_get_property(pdev); 958199d312SAdrian Hunter } 9638576af1SShawn Guo 9785d6509dSShawn Guo extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, 980e748234SChristian Daudt const struct sdhci_pltfm_data *pdata, 990e748234SChristian Daudt size_t priv_size); 10085d6509dSShawn Guo extern void sdhci_pltfm_free(struct platform_device *pdev); 10185d6509dSShawn Guo 10285d6509dSShawn Guo extern int sdhci_pltfm_register(struct platform_device *pdev, 1030e748234SChristian Daudt const struct sdhci_pltfm_data *pdata, 1040e748234SChristian Daudt size_t priv_size); 10585d6509dSShawn Guo extern int sdhci_pltfm_unregister(struct platform_device *pdev); 10685d6509dSShawn Guo 107d005d943SLars-Peter Clausen extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host); 108d005d943SLars-Peter Clausen 1090e748234SChristian Daudt static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host) 1100e748234SChristian Daudt { 111178b0fa0SMasahiro Yamada return host->private; 1120e748234SChristian Daudt } 1130e748234SChristian Daudt 11483a7b32aSMasahiro Yamada int sdhci_pltfm_suspend(struct device *dev); 11583a7b32aSMasahiro Yamada int sdhci_pltfm_resume(struct device *dev); 11629495aa0SManuel Lauss extern const struct dev_pm_ops sdhci_pltfm_pmops; 11720b1597bSAnton Vorontsov 118515033f9SAnton Vorontsov #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ 119