1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SDHCI_PCI_H 3 #define __SDHCI_PCI_H 4 5 /* 6 * PCI device IDs, sub IDs 7 */ 8 9 #define PCI_DEVICE_ID_O2_SDS0 0x8420 10 #define PCI_DEVICE_ID_O2_SDS1 0x8421 11 #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 12 #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 13 #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 14 15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 16 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 17 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 18 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 19 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 20 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 21 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 22 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 23 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 24 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 27 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 29 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 30 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 31 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 32 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 33 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 34 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 35 #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 36 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 37 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 38 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 39 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 40 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 41 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 42 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 43 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 44 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 45 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 46 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 47 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 48 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 49 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 50 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 51 52 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 53 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 54 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 55 56 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 57 58 /* 59 * PCI device class and mask 60 */ 61 62 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 63 #define PCI_CLASS_MASK 0xFFFF00 64 65 /* 66 * Macros for PCI device-description 67 */ 68 69 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 70 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 71 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 72 73 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 74 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 75 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 76 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 77 } 78 79 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 80 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 81 .subvendor = _PCI_VEND(subvend), \ 82 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 83 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 84 } 85 86 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 87 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 88 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 89 .class = (cl), .class_mask = (cl_msk), \ 90 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 91 } 92 93 /* 94 * PCI registers 95 */ 96 97 #define PCI_SDHCI_IFPIO 0x00 98 #define PCI_SDHCI_IFDMA 0x01 99 #define PCI_SDHCI_IFVENDOR 0x02 100 101 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 102 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 103 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 104 105 #define MAX_SLOTS 8 106 107 struct sdhci_pci_chip; 108 struct sdhci_pci_slot; 109 110 struct sdhci_pci_fixes { 111 unsigned int quirks; 112 unsigned int quirks2; 113 bool allow_runtime_pm; 114 bool own_cd_for_runtime_pm; 115 116 int (*probe) (struct sdhci_pci_chip *); 117 118 int (*probe_slot) (struct sdhci_pci_slot *); 119 int (*add_host) (struct sdhci_pci_slot *); 120 void (*remove_slot) (struct sdhci_pci_slot *, int); 121 122 #ifdef CONFIG_PM_SLEEP 123 int (*suspend) (struct sdhci_pci_chip *); 124 int (*resume) (struct sdhci_pci_chip *); 125 #endif 126 #ifdef CONFIG_PM 127 int (*runtime_suspend) (struct sdhci_pci_chip *); 128 int (*runtime_resume) (struct sdhci_pci_chip *); 129 #endif 130 131 const struct sdhci_ops *ops; 132 size_t priv_size; 133 }; 134 135 struct sdhci_pci_slot { 136 struct sdhci_pci_chip *chip; 137 struct sdhci_host *host; 138 struct sdhci_pci_data *data; 139 140 int rst_n_gpio; 141 int cd_gpio; 142 int cd_irq; 143 144 int cd_idx; 145 bool cd_override_level; 146 147 void (*hw_reset)(struct sdhci_host *host); 148 unsigned long private[0] ____cacheline_aligned; 149 }; 150 151 struct sdhci_pci_chip { 152 struct pci_dev *pdev; 153 154 unsigned int quirks; 155 unsigned int quirks2; 156 bool allow_runtime_pm; 157 bool pm_retune; 158 bool rpm_retune; 159 const struct sdhci_pci_fixes *fixes; 160 161 int num_slots; /* Slots on controller */ 162 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 163 }; 164 165 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 166 { 167 return (void *)slot->private; 168 } 169 170 #ifdef CONFIG_PM_SLEEP 171 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 172 #endif 173 174 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot); 175 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip); 176 #ifdef CONFIG_PM_SLEEP 177 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip); 178 #endif 179 180 #endif /* __SDHCI_PCI_H */ 181