1 #ifndef __SDHCI_PCI_H 2 #define __SDHCI_PCI_H 3 4 /* 5 * PCI device IDs, sub IDs 6 */ 7 8 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 9 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 10 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 11 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 12 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 13 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 14 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 15 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 16 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 17 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 18 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 19 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 20 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 21 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 22 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 23 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 24 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 25 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 26 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 27 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 28 #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 29 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 30 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 31 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 32 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 33 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 34 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 35 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 36 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 37 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 38 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 39 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 40 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 41 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 42 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 43 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 44 45 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 46 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 47 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 48 49 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 50 51 /* 52 * PCI device class and mask 53 */ 54 55 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 56 #define PCI_CLASS_MASK 0xFFFF00 57 58 /* 59 * Macros for PCI device-description 60 */ 61 62 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 63 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 64 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 65 66 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 67 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 68 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 69 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 70 } 71 72 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 73 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 74 .subvendor = _PCI_VEND(subvend), \ 75 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 76 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 77 } 78 79 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 80 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 81 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 82 .class = (cl), .class_mask = (cl_msk), \ 83 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 84 } 85 86 /* 87 * PCI registers 88 */ 89 90 #define PCI_SDHCI_IFPIO 0x00 91 #define PCI_SDHCI_IFDMA 0x01 92 #define PCI_SDHCI_IFVENDOR 0x02 93 94 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 95 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 96 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 97 98 #define MAX_SLOTS 8 99 100 struct sdhci_pci_chip; 101 struct sdhci_pci_slot; 102 103 struct sdhci_pci_fixes { 104 unsigned int quirks; 105 unsigned int quirks2; 106 bool allow_runtime_pm; 107 bool own_cd_for_runtime_pm; 108 109 int (*probe) (struct sdhci_pci_chip *); 110 111 int (*probe_slot) (struct sdhci_pci_slot *); 112 int (*add_host) (struct sdhci_pci_slot *); 113 void (*remove_slot) (struct sdhci_pci_slot *, int); 114 115 #ifdef CONFIG_PM_SLEEP 116 int (*suspend) (struct sdhci_pci_chip *); 117 int (*resume) (struct sdhci_pci_chip *); 118 #endif 119 #ifdef CONFIG_PM 120 int (*runtime_suspend) (struct sdhci_pci_chip *); 121 int (*runtime_resume) (struct sdhci_pci_chip *); 122 #endif 123 124 const struct sdhci_ops *ops; 125 size_t priv_size; 126 }; 127 128 struct sdhci_pci_slot { 129 struct sdhci_pci_chip *chip; 130 struct sdhci_host *host; 131 struct sdhci_pci_data *data; 132 133 int rst_n_gpio; 134 int cd_gpio; 135 int cd_irq; 136 137 int cd_idx; 138 bool cd_override_level; 139 140 void (*hw_reset)(struct sdhci_host *host); 141 unsigned long private[0] ____cacheline_aligned; 142 }; 143 144 struct sdhci_pci_chip { 145 struct pci_dev *pdev; 146 147 unsigned int quirks; 148 unsigned int quirks2; 149 bool allow_runtime_pm; 150 bool pm_retune; 151 bool rpm_retune; 152 const struct sdhci_pci_fixes *fixes; 153 154 int num_slots; /* Slots on controller */ 155 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 156 }; 157 158 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 159 { 160 return (void *)slot->private; 161 } 162 163 #ifdef CONFIG_PM_SLEEP 164 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 165 #endif 166 167 #endif /* __SDHCI_PCI_H */ 168