1 #ifndef __SDHCI_PCI_H 2 #define __SDHCI_PCI_H 3 4 /* 5 * PCI device IDs, sub IDs 6 */ 7 8 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 9 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 10 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 11 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 12 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 13 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 14 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 15 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 16 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 17 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 18 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 19 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 20 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 21 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 22 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 23 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 24 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 25 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 26 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 27 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 28 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 29 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 30 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 31 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 32 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 33 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 34 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 35 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 36 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 37 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 38 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 39 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 40 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 41 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 42 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 43 44 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 45 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 46 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 47 48 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 49 50 /* 51 * PCI device class and mask 52 */ 53 54 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 55 #define PCI_CLASS_MASK 0xFFFF00 56 57 /* 58 * Macros for PCI device-description 59 */ 60 61 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 62 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 63 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 64 65 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 66 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 67 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 68 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 69 } 70 71 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 72 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 73 .subvendor = _PCI_VEND(subvend), \ 74 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 75 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 76 } 77 78 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 79 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 80 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 81 .class = (cl), .class_mask = (cl_msk), \ 82 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 83 } 84 85 /* 86 * PCI registers 87 */ 88 89 #define PCI_SDHCI_IFPIO 0x00 90 #define PCI_SDHCI_IFDMA 0x01 91 #define PCI_SDHCI_IFVENDOR 0x02 92 93 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 94 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 95 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 96 97 #define MAX_SLOTS 8 98 99 struct sdhci_pci_chip; 100 struct sdhci_pci_slot; 101 102 struct sdhci_pci_fixes { 103 unsigned int quirks; 104 unsigned int quirks2; 105 bool allow_runtime_pm; 106 bool own_cd_for_runtime_pm; 107 108 int (*probe) (struct sdhci_pci_chip *); 109 110 int (*probe_slot) (struct sdhci_pci_slot *); 111 int (*add_host) (struct sdhci_pci_slot *); 112 void (*remove_slot) (struct sdhci_pci_slot *, int); 113 114 #ifdef CONFIG_PM_SLEEP 115 int (*suspend) (struct sdhci_pci_chip *); 116 int (*resume) (struct sdhci_pci_chip *); 117 #endif 118 #ifdef CONFIG_PM 119 int (*runtime_suspend) (struct sdhci_pci_chip *); 120 int (*runtime_resume) (struct sdhci_pci_chip *); 121 #endif 122 123 const struct sdhci_ops *ops; 124 size_t priv_size; 125 }; 126 127 struct sdhci_pci_slot { 128 struct sdhci_pci_chip *chip; 129 struct sdhci_host *host; 130 struct sdhci_pci_data *data; 131 132 int rst_n_gpio; 133 int cd_gpio; 134 int cd_irq; 135 136 int cd_idx; 137 bool cd_override_level; 138 139 void (*hw_reset)(struct sdhci_host *host); 140 unsigned long private[0] ____cacheline_aligned; 141 }; 142 143 struct sdhci_pci_chip { 144 struct pci_dev *pdev; 145 146 unsigned int quirks; 147 unsigned int quirks2; 148 bool allow_runtime_pm; 149 bool pm_retune; 150 bool rpm_retune; 151 const struct sdhci_pci_fixes *fixes; 152 153 int num_slots; /* Slots on controller */ 154 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 155 }; 156 157 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 158 { 159 return (void *)slot->private; 160 } 161 162 #ifdef CONFIG_PM_SLEEP 163 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 164 #endif 165 166 #endif /* __SDHCI_PCI_H */ 167