1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SDHCI_PCI_H 3 #define __SDHCI_PCI_H 4 5 /* 6 * PCI device IDs, sub IDs 7 */ 8 9 #define PCI_DEVICE_ID_O2_SDS0 0x8420 10 #define PCI_DEVICE_ID_O2_SDS1 0x8421 11 #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 12 #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 13 #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 14 15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 16 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 17 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 18 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 19 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 20 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 21 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 22 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 23 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 24 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 27 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 29 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 30 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 31 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 32 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 33 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 34 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 35 #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 36 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 37 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 38 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 39 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 40 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 41 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 42 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 43 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 44 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 45 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 46 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 47 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 48 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 49 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 50 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 51 #define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4 52 #define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8 53 #define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47 54 #define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48 55 #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4 56 #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5 57 58 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 59 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 60 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 61 62 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 63 #define PCI_SUBDEVICE_ID_NI_78E3 0x78e3 64 65 #define PCI_VENDOR_ID_ARASAN 0x16e6 66 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670 67 68 #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 69 70 /* 71 * PCI device class and mask 72 */ 73 74 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 75 #define PCI_CLASS_MASK 0xFFFF00 76 77 /* 78 * Macros for PCI device-description 79 */ 80 81 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 82 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 83 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 84 85 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 86 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 88 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 89 } 90 91 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 92 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 93 .subvendor = _PCI_VEND(subvend), \ 94 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 95 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 96 } 97 98 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 99 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 100 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 101 .class = (cl), .class_mask = (cl_msk), \ 102 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 103 } 104 105 /* 106 * PCI registers 107 */ 108 109 #define PCI_SDHCI_IFPIO 0x00 110 #define PCI_SDHCI_IFDMA 0x01 111 #define PCI_SDHCI_IFVENDOR 0x02 112 113 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 114 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 115 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 116 117 #define MAX_SLOTS 8 118 119 struct sdhci_pci_chip; 120 struct sdhci_pci_slot; 121 122 struct sdhci_pci_fixes { 123 unsigned int quirks; 124 unsigned int quirks2; 125 bool allow_runtime_pm; 126 bool own_cd_for_runtime_pm; 127 128 int (*probe) (struct sdhci_pci_chip *); 129 130 int (*probe_slot) (struct sdhci_pci_slot *); 131 int (*add_host) (struct sdhci_pci_slot *); 132 void (*remove_slot) (struct sdhci_pci_slot *, int); 133 134 #ifdef CONFIG_PM_SLEEP 135 int (*suspend) (struct sdhci_pci_chip *); 136 int (*resume) (struct sdhci_pci_chip *); 137 #endif 138 #ifdef CONFIG_PM 139 int (*runtime_suspend) (struct sdhci_pci_chip *); 140 int (*runtime_resume) (struct sdhci_pci_chip *); 141 #endif 142 143 const struct sdhci_ops *ops; 144 size_t priv_size; 145 }; 146 147 struct sdhci_pci_slot { 148 struct sdhci_pci_chip *chip; 149 struct sdhci_host *host; 150 struct sdhci_pci_data *data; 151 152 int rst_n_gpio; 153 int cd_gpio; 154 int cd_irq; 155 156 int cd_idx; 157 bool cd_override_level; 158 159 void (*hw_reset)(struct sdhci_host *host); 160 unsigned long private[0] ____cacheline_aligned; 161 }; 162 163 struct sdhci_pci_chip { 164 struct pci_dev *pdev; 165 166 unsigned int quirks; 167 unsigned int quirks2; 168 bool allow_runtime_pm; 169 bool pm_retune; 170 bool rpm_retune; 171 const struct sdhci_pci_fixes *fixes; 172 173 int num_slots; /* Slots on controller */ 174 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 175 }; 176 177 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 178 { 179 return (void *)slot->private; 180 } 181 182 #ifdef CONFIG_PM_SLEEP 183 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 184 #endif 185 int sdhci_pci_enable_dma(struct sdhci_host *host); 186 187 extern const struct sdhci_pci_fixes sdhci_arasan; 188 extern const struct sdhci_pci_fixes sdhci_snps; 189 extern const struct sdhci_pci_fixes sdhci_o2; 190 191 #endif /* __SDHCI_PCI_H */ 192