1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SDHCI_PCI_H 3 #define __SDHCI_PCI_H 4 5 /* 6 * PCI device IDs, sub IDs 7 */ 8 9 #define PCI_DEVICE_ID_O2_SDS0 0x8420 10 #define PCI_DEVICE_ID_O2_SDS1 0x8421 11 #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 12 #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 13 #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 14 15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 16 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 17 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 18 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 19 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 20 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 21 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 22 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 23 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 24 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 27 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 29 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 30 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 31 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 32 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 33 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 34 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 35 #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 36 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 37 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 38 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 39 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 40 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 41 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 42 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 43 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 44 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 45 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 46 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 47 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 48 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 49 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 50 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 51 #define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4 52 #define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8 53 #define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47 54 #define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48 55 #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4 56 #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5 57 #define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5 58 59 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 60 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 61 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 62 63 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 64 #define PCI_SUBDEVICE_ID_NI_78E3 0x78e3 65 66 #define PCI_VENDOR_ID_ARASAN 0x16e6 67 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670 68 69 #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 70 71 /* 72 * PCI device class and mask 73 */ 74 75 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 76 #define PCI_CLASS_MASK 0xFFFF00 77 78 /* 79 * Macros for PCI device-description 80 */ 81 82 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 83 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 84 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 85 86 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 87 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 88 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 89 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 90 } 91 92 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 93 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 94 .subvendor = _PCI_VEND(subvend), \ 95 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 96 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 97 } 98 99 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 100 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 101 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 102 .class = (cl), .class_mask = (cl_msk), \ 103 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 104 } 105 106 /* 107 * PCI registers 108 */ 109 110 #define PCI_SDHCI_IFPIO 0x00 111 #define PCI_SDHCI_IFDMA 0x01 112 #define PCI_SDHCI_IFVENDOR 0x02 113 114 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 115 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 116 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 117 118 #define MAX_SLOTS 8 119 120 struct sdhci_pci_chip; 121 struct sdhci_pci_slot; 122 123 struct sdhci_pci_fixes { 124 unsigned int quirks; 125 unsigned int quirks2; 126 bool allow_runtime_pm; 127 bool own_cd_for_runtime_pm; 128 129 int (*probe) (struct sdhci_pci_chip *); 130 131 int (*probe_slot) (struct sdhci_pci_slot *); 132 int (*add_host) (struct sdhci_pci_slot *); 133 void (*remove_slot) (struct sdhci_pci_slot *, int); 134 135 #ifdef CONFIG_PM_SLEEP 136 int (*suspend) (struct sdhci_pci_chip *); 137 int (*resume) (struct sdhci_pci_chip *); 138 #endif 139 #ifdef CONFIG_PM 140 int (*runtime_suspend) (struct sdhci_pci_chip *); 141 int (*runtime_resume) (struct sdhci_pci_chip *); 142 #endif 143 144 const struct sdhci_ops *ops; 145 size_t priv_size; 146 }; 147 148 struct sdhci_pci_slot { 149 struct sdhci_pci_chip *chip; 150 struct sdhci_host *host; 151 struct sdhci_pci_data *data; 152 153 int rst_n_gpio; 154 int cd_gpio; 155 int cd_irq; 156 157 int cd_idx; 158 bool cd_override_level; 159 160 void (*hw_reset)(struct sdhci_host *host); 161 unsigned long private[0] ____cacheline_aligned; 162 }; 163 164 struct sdhci_pci_chip { 165 struct pci_dev *pdev; 166 167 unsigned int quirks; 168 unsigned int quirks2; 169 bool allow_runtime_pm; 170 bool pm_retune; 171 bool rpm_retune; 172 const struct sdhci_pci_fixes *fixes; 173 174 int num_slots; /* Slots on controller */ 175 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 176 }; 177 178 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 179 { 180 return (void *)slot->private; 181 } 182 183 #ifdef CONFIG_PM_SLEEP 184 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 185 #endif 186 int sdhci_pci_enable_dma(struct sdhci_host *host); 187 188 extern const struct sdhci_pci_fixes sdhci_arasan; 189 extern const struct sdhci_pci_fixes sdhci_snps; 190 extern const struct sdhci_pci_fixes sdhci_o2; 191 192 #endif /* __SDHCI_PCI_H */ 193