1 #ifndef __SDHCI_PCI_H 2 #define __SDHCI_PCI_H 3 4 /* 5 * PCI device IDs, sub IDs 6 */ 7 8 #define PCI_DEVICE_ID_O2_SDS0 0x8420 9 #define PCI_DEVICE_ID_O2_SDS1 0x8421 10 #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 11 #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 12 #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 13 14 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 16 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 17 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 18 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 19 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 20 #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 21 #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 22 #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 23 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 24 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 27 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 29 #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 30 #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 31 #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 32 #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 33 #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 34 #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 35 #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 36 #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 37 #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 38 #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 39 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 40 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 41 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 42 #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 43 #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 44 #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 45 #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 46 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 47 #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 48 #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 49 #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 50 51 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 52 #define PCI_DEVICE_ID_VIA_95D0 0x95d0 53 #define PCI_DEVICE_ID_REALTEK_5250 0x5250 54 55 #define PCI_SUBDEVICE_ID_NI_7884 0x7884 56 57 /* 58 * PCI device class and mask 59 */ 60 61 #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 62 #define PCI_CLASS_MASK 0xFFFF00 63 64 /* 65 * Macros for PCI device-description 66 */ 67 68 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 69 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 70 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 71 72 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 73 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 74 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 75 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 76 } 77 78 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 79 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 80 .subvendor = _PCI_VEND(subvend), \ 81 .subdevice = _PCI_SUBDEV(subvend, subdev), \ 82 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 83 } 84 85 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 86 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 88 .class = (cl), .class_mask = (cl_msk), \ 89 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 90 } 91 92 /* 93 * PCI registers 94 */ 95 96 #define PCI_SDHCI_IFPIO 0x00 97 #define PCI_SDHCI_IFDMA 0x01 98 #define PCI_SDHCI_IFVENDOR 0x02 99 100 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 101 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 102 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 103 104 #define MAX_SLOTS 8 105 106 struct sdhci_pci_chip; 107 struct sdhci_pci_slot; 108 109 struct sdhci_pci_fixes { 110 unsigned int quirks; 111 unsigned int quirks2; 112 bool allow_runtime_pm; 113 bool own_cd_for_runtime_pm; 114 115 int (*probe) (struct sdhci_pci_chip *); 116 117 int (*probe_slot) (struct sdhci_pci_slot *); 118 int (*add_host) (struct sdhci_pci_slot *); 119 void (*remove_slot) (struct sdhci_pci_slot *, int); 120 121 #ifdef CONFIG_PM_SLEEP 122 int (*suspend) (struct sdhci_pci_chip *); 123 int (*resume) (struct sdhci_pci_chip *); 124 #endif 125 #ifdef CONFIG_PM 126 int (*runtime_suspend) (struct sdhci_pci_chip *); 127 int (*runtime_resume) (struct sdhci_pci_chip *); 128 #endif 129 130 const struct sdhci_ops *ops; 131 size_t priv_size; 132 }; 133 134 struct sdhci_pci_slot { 135 struct sdhci_pci_chip *chip; 136 struct sdhci_host *host; 137 struct sdhci_pci_data *data; 138 139 int rst_n_gpio; 140 int cd_gpio; 141 int cd_irq; 142 143 int cd_idx; 144 bool cd_override_level; 145 146 void (*hw_reset)(struct sdhci_host *host); 147 unsigned long private[0] ____cacheline_aligned; 148 }; 149 150 struct sdhci_pci_chip { 151 struct pci_dev *pdev; 152 153 unsigned int quirks; 154 unsigned int quirks2; 155 bool allow_runtime_pm; 156 bool pm_retune; 157 bool rpm_retune; 158 const struct sdhci_pci_fixes *fixes; 159 160 int num_slots; /* Slots on controller */ 161 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 162 }; 163 164 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 165 { 166 return (void *)slot->private; 167 } 168 169 #ifdef CONFIG_PM_SLEEP 170 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 171 #endif 172 173 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot); 174 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip); 175 #ifdef CONFIG_PM_SLEEP 176 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip); 177 #endif 178 179 #endif /* __SDHCI_PCI_H */ 180