1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2522624f9SAdam Lee #ifndef __SDHCI_PCI_H 3522624f9SAdam Lee #define __SDHCI_PCI_H 4522624f9SAdam Lee 5522624f9SAdam Lee /* 6c949c907SMatthias Kraemer * PCI device IDs, sub IDs 7522624f9SAdam Lee */ 8522624f9SAdam Lee 9361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SDS0 0x8420 10361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SDS1 0x8421 11361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 12361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 13361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 14361eeda0SAdrian Hunter 15522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 16522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 17522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 18522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 19522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 20522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 21066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 22066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 23066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 241f64cec2SAndy Shevchenko #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 25522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 26522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 27522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 28522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 29522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 3043e968ceSDerek Browne #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 311f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 321f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 331f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 3406bf9c56SAdrian Hunter #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 35cdaba732SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 364fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 374fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 384fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 3901d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 4001d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 4101d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 424fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 434fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 444fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 452d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 462d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 472d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 48bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 49bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 50bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 51522624f9SAdam Lee 52c949c907SMatthias Kraemer #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 53c949c907SMatthias Kraemer #define PCI_DEVICE_ID_VIA_95D0 0x95d0 54c949c907SMatthias Kraemer #define PCI_DEVICE_ID_REALTEK_5250 0x5250 55c949c907SMatthias Kraemer 56c949c907SMatthias Kraemer #define PCI_SUBDEVICE_ID_NI_7884 0x7884 57c949c907SMatthias Kraemer 58d72d72cdSAtul Garg #define PCI_VENDOR_ID_ARASAN 0x16e6 59d72d72cdSAtul Garg #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670 60d72d72cdSAtul Garg 61c949c907SMatthias Kraemer /* 62c949c907SMatthias Kraemer * PCI device class and mask 63c949c907SMatthias Kraemer */ 64c949c907SMatthias Kraemer 65c949c907SMatthias Kraemer #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 66c949c907SMatthias Kraemer #define PCI_CLASS_MASK 0xFFFF00 67c949c907SMatthias Kraemer 68c949c907SMatthias Kraemer /* 69c949c907SMatthias Kraemer * Macros for PCI device-description 70c949c907SMatthias Kraemer */ 71c949c907SMatthias Kraemer 72c949c907SMatthias Kraemer #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 73c949c907SMatthias Kraemer #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 74c949c907SMatthias Kraemer #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 75c949c907SMatthias Kraemer 76c949c907SMatthias Kraemer #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 77c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 78c949c907SMatthias Kraemer .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 79c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 80c949c907SMatthias Kraemer } 81c949c907SMatthias Kraemer 82c949c907SMatthias Kraemer #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 83c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 84c949c907SMatthias Kraemer .subvendor = _PCI_VEND(subvend), \ 85c949c907SMatthias Kraemer .subdevice = _PCI_SUBDEV(subvend, subdev), \ 86c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 87c949c907SMatthias Kraemer } 88c949c907SMatthias Kraemer 89c949c907SMatthias Kraemer #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 90c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 91c949c907SMatthias Kraemer .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 92c949c907SMatthias Kraemer .class = (cl), .class_mask = (cl_msk), \ 93c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 94c949c907SMatthias Kraemer } 95c949c907SMatthias Kraemer 96522624f9SAdam Lee /* 97522624f9SAdam Lee * PCI registers 98522624f9SAdam Lee */ 99522624f9SAdam Lee 100522624f9SAdam Lee #define PCI_SDHCI_IFPIO 0x00 101522624f9SAdam Lee #define PCI_SDHCI_IFDMA 0x01 102522624f9SAdam Lee #define PCI_SDHCI_IFVENDOR 0x02 103522624f9SAdam Lee 104522624f9SAdam Lee #define PCI_SLOT_INFO 0x40 /* 8 bits */ 105522624f9SAdam Lee #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 106522624f9SAdam Lee #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 107522624f9SAdam Lee 108522624f9SAdam Lee #define MAX_SLOTS 8 109522624f9SAdam Lee 110522624f9SAdam Lee struct sdhci_pci_chip; 111522624f9SAdam Lee struct sdhci_pci_slot; 112522624f9SAdam Lee 113522624f9SAdam Lee struct sdhci_pci_fixes { 114522624f9SAdam Lee unsigned int quirks; 115522624f9SAdam Lee unsigned int quirks2; 116522624f9SAdam Lee bool allow_runtime_pm; 11777a0122eSAdrian Hunter bool own_cd_for_runtime_pm; 118522624f9SAdam Lee 119522624f9SAdam Lee int (*probe) (struct sdhci_pci_chip *); 120522624f9SAdam Lee 121522624f9SAdam Lee int (*probe_slot) (struct sdhci_pci_slot *); 12261c951deSAdrian Hunter int (*add_host) (struct sdhci_pci_slot *); 123522624f9SAdam Lee void (*remove_slot) (struct sdhci_pci_slot *, int); 124522624f9SAdam Lee 125b7813f0fSAdrian Hunter #ifdef CONFIG_PM_SLEEP 126522624f9SAdam Lee int (*suspend) (struct sdhci_pci_chip *); 127522624f9SAdam Lee int (*resume) (struct sdhci_pci_chip *); 128b7813f0fSAdrian Hunter #endif 129966d696aSAdrian Hunter #ifdef CONFIG_PM 130966d696aSAdrian Hunter int (*runtime_suspend) (struct sdhci_pci_chip *); 131966d696aSAdrian Hunter int (*runtime_resume) (struct sdhci_pci_chip *); 132966d696aSAdrian Hunter #endif 1336bc09063SAdrian Hunter 1346bc09063SAdrian Hunter const struct sdhci_ops *ops; 135ac9f67b5SAdrian Hunter size_t priv_size; 136522624f9SAdam Lee }; 137522624f9SAdam Lee 138522624f9SAdam Lee struct sdhci_pci_slot { 139522624f9SAdam Lee struct sdhci_pci_chip *chip; 140522624f9SAdam Lee struct sdhci_host *host; 141522624f9SAdam Lee struct sdhci_pci_data *data; 142522624f9SAdam Lee 143522624f9SAdam Lee int rst_n_gpio; 144522624f9SAdam Lee int cd_gpio; 145522624f9SAdam Lee int cd_irq; 146522624f9SAdam Lee 147ff59c520SAdrian Hunter int cd_idx; 148ff59c520SAdrian Hunter bool cd_override_level; 149ff59c520SAdrian Hunter 150522624f9SAdam Lee void (*hw_reset)(struct sdhci_host *host); 151ac9f67b5SAdrian Hunter unsigned long private[0] ____cacheline_aligned; 152522624f9SAdam Lee }; 153522624f9SAdam Lee 154522624f9SAdam Lee struct sdhci_pci_chip { 155522624f9SAdam Lee struct pci_dev *pdev; 156522624f9SAdam Lee 157522624f9SAdam Lee unsigned int quirks; 158522624f9SAdam Lee unsigned int quirks2; 159522624f9SAdam Lee bool allow_runtime_pm; 160d38dcad4SAdrian Hunter bool pm_retune; 161d38dcad4SAdrian Hunter bool rpm_retune; 162522624f9SAdam Lee const struct sdhci_pci_fixes *fixes; 163522624f9SAdam Lee 164522624f9SAdam Lee int num_slots; /* Slots on controller */ 165522624f9SAdam Lee struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 166522624f9SAdam Lee }; 167522624f9SAdam Lee 168ac9f67b5SAdrian Hunter static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 169ac9f67b5SAdrian Hunter { 170ac9f67b5SAdrian Hunter return (void *)slot->private; 171ac9f67b5SAdrian Hunter } 172ac9f67b5SAdrian Hunter 17330cf2803SAdrian Hunter #ifdef CONFIG_PM_SLEEP 17430cf2803SAdrian Hunter int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 17530cf2803SAdrian Hunter #endif 176d72d72cdSAtul Garg int sdhci_pci_enable_dma(struct sdhci_host *host); 177361eeda0SAdrian Hunter int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot); 178361eeda0SAdrian Hunter int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip); 179361eeda0SAdrian Hunter #ifdef CONFIG_PM_SLEEP 180361eeda0SAdrian Hunter int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip); 181361eeda0SAdrian Hunter #endif 182361eeda0SAdrian Hunter 183d72d72cdSAtul Garg extern const struct sdhci_pci_fixes sdhci_arasan; 184d72d72cdSAtul Garg 185522624f9SAdam Lee #endif /* __SDHCI_PCI_H */ 186