1522624f9SAdam Lee #ifndef __SDHCI_PCI_H 2522624f9SAdam Lee #define __SDHCI_PCI_H 3522624f9SAdam Lee 4522624f9SAdam Lee /* 5522624f9SAdam Lee * PCI device IDs 6522624f9SAdam Lee */ 7522624f9SAdam Lee 8522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 9522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 10522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 11522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 12522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 13522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 14066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 15066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 16066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 17522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190 18522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 19522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 20522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 21522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 22522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 2343e968ceSDerek Browne #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 241f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 251f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 261f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 2706bf9c56SAdrian Hunter #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 284fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 294fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 304fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 314fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 324fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 334fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 34522624f9SAdam Lee 35522624f9SAdam Lee /* 36522624f9SAdam Lee * PCI registers 37522624f9SAdam Lee */ 38522624f9SAdam Lee 39522624f9SAdam Lee #define PCI_SDHCI_IFPIO 0x00 40522624f9SAdam Lee #define PCI_SDHCI_IFDMA 0x01 41522624f9SAdam Lee #define PCI_SDHCI_IFVENDOR 0x02 42522624f9SAdam Lee 43522624f9SAdam Lee #define PCI_SLOT_INFO 0x40 /* 8 bits */ 44522624f9SAdam Lee #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 45522624f9SAdam Lee #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 46522624f9SAdam Lee 47522624f9SAdam Lee #define MAX_SLOTS 8 48522624f9SAdam Lee 49522624f9SAdam Lee struct sdhci_pci_chip; 50522624f9SAdam Lee struct sdhci_pci_slot; 51522624f9SAdam Lee 52522624f9SAdam Lee struct sdhci_pci_fixes { 53522624f9SAdam Lee unsigned int quirks; 54522624f9SAdam Lee unsigned int quirks2; 55522624f9SAdam Lee bool allow_runtime_pm; 5677a0122eSAdrian Hunter bool own_cd_for_runtime_pm; 57522624f9SAdam Lee 58522624f9SAdam Lee int (*probe) (struct sdhci_pci_chip *); 59522624f9SAdam Lee 60522624f9SAdam Lee int (*probe_slot) (struct sdhci_pci_slot *); 61522624f9SAdam Lee void (*remove_slot) (struct sdhci_pci_slot *, int); 62522624f9SAdam Lee 63522624f9SAdam Lee int (*suspend) (struct sdhci_pci_chip *); 64522624f9SAdam Lee int (*resume) (struct sdhci_pci_chip *); 65522624f9SAdam Lee }; 66522624f9SAdam Lee 67522624f9SAdam Lee struct sdhci_pci_slot { 68522624f9SAdam Lee struct sdhci_pci_chip *chip; 69522624f9SAdam Lee struct sdhci_host *host; 70522624f9SAdam Lee struct sdhci_pci_data *data; 71522624f9SAdam Lee 72522624f9SAdam Lee int pci_bar; 73522624f9SAdam Lee int rst_n_gpio; 74522624f9SAdam Lee int cd_gpio; 75522624f9SAdam Lee int cd_irq; 76522624f9SAdam Lee 77ff59c520SAdrian Hunter char *cd_con_id; 78ff59c520SAdrian Hunter int cd_idx; 79ff59c520SAdrian Hunter bool cd_override_level; 80ff59c520SAdrian Hunter 81522624f9SAdam Lee void (*hw_reset)(struct sdhci_host *host); 82e1bfad6dSAdrian Hunter int (*select_drive_strength)(struct sdhci_host *host, 83e1bfad6dSAdrian Hunter struct mmc_card *card, 84e1bfad6dSAdrian Hunter unsigned int max_dtr, int host_drv, 85e1bfad6dSAdrian Hunter int card_drv, int *drv_type); 86522624f9SAdam Lee }; 87522624f9SAdam Lee 88522624f9SAdam Lee struct sdhci_pci_chip { 89522624f9SAdam Lee struct pci_dev *pdev; 90522624f9SAdam Lee 91522624f9SAdam Lee unsigned int quirks; 92522624f9SAdam Lee unsigned int quirks2; 93522624f9SAdam Lee bool allow_runtime_pm; 94522624f9SAdam Lee const struct sdhci_pci_fixes *fixes; 95522624f9SAdam Lee 96522624f9SAdam Lee int num_slots; /* Slots on controller */ 97522624f9SAdam Lee struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 98522624f9SAdam Lee }; 99522624f9SAdam Lee 100522624f9SAdam Lee #endif /* __SDHCI_PCI_H */ 101