1522624f9SAdam Lee #ifndef __SDHCI_PCI_H 2522624f9SAdam Lee #define __SDHCI_PCI_H 3522624f9SAdam Lee 4522624f9SAdam Lee /* 5522624f9SAdam Lee * PCI device IDs 6522624f9SAdam Lee */ 7522624f9SAdam Lee 8522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 9522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 10522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 11522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 12522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 13522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 14522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190 15522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 16522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 17522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 18522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 19522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 2043e968ceSDerek Browne #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 21522624f9SAdam Lee 22522624f9SAdam Lee /* 23522624f9SAdam Lee * PCI registers 24522624f9SAdam Lee */ 25522624f9SAdam Lee 26522624f9SAdam Lee #define PCI_SDHCI_IFPIO 0x00 27522624f9SAdam Lee #define PCI_SDHCI_IFDMA 0x01 28522624f9SAdam Lee #define PCI_SDHCI_IFVENDOR 0x02 29522624f9SAdam Lee 30522624f9SAdam Lee #define PCI_SLOT_INFO 0x40 /* 8 bits */ 31522624f9SAdam Lee #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 32522624f9SAdam Lee #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 33522624f9SAdam Lee 34522624f9SAdam Lee #define MAX_SLOTS 8 35522624f9SAdam Lee 36522624f9SAdam Lee struct sdhci_pci_chip; 37522624f9SAdam Lee struct sdhci_pci_slot; 38522624f9SAdam Lee 39522624f9SAdam Lee struct sdhci_pci_fixes { 40522624f9SAdam Lee unsigned int quirks; 41522624f9SAdam Lee unsigned int quirks2; 42522624f9SAdam Lee bool allow_runtime_pm; 4377a0122eSAdrian Hunter bool own_cd_for_runtime_pm; 44522624f9SAdam Lee 45522624f9SAdam Lee int (*probe) (struct sdhci_pci_chip *); 46522624f9SAdam Lee 47522624f9SAdam Lee int (*probe_slot) (struct sdhci_pci_slot *); 48522624f9SAdam Lee void (*remove_slot) (struct sdhci_pci_slot *, int); 49522624f9SAdam Lee 50522624f9SAdam Lee int (*suspend) (struct sdhci_pci_chip *); 51522624f9SAdam Lee int (*resume) (struct sdhci_pci_chip *); 52522624f9SAdam Lee }; 53522624f9SAdam Lee 54522624f9SAdam Lee struct sdhci_pci_slot { 55522624f9SAdam Lee struct sdhci_pci_chip *chip; 56522624f9SAdam Lee struct sdhci_host *host; 57522624f9SAdam Lee struct sdhci_pci_data *data; 58522624f9SAdam Lee 59522624f9SAdam Lee int pci_bar; 60522624f9SAdam Lee int rst_n_gpio; 61522624f9SAdam Lee int cd_gpio; 62522624f9SAdam Lee int cd_irq; 63522624f9SAdam Lee 64522624f9SAdam Lee void (*hw_reset)(struct sdhci_host *host); 65522624f9SAdam Lee }; 66522624f9SAdam Lee 67522624f9SAdam Lee struct sdhci_pci_chip { 68522624f9SAdam Lee struct pci_dev *pdev; 69522624f9SAdam Lee 70522624f9SAdam Lee unsigned int quirks; 71522624f9SAdam Lee unsigned int quirks2; 72522624f9SAdam Lee bool allow_runtime_pm; 73522624f9SAdam Lee const struct sdhci_pci_fixes *fixes; 74522624f9SAdam Lee 75522624f9SAdam Lee int num_slots; /* Slots on controller */ 76522624f9SAdam Lee struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 77522624f9SAdam Lee }; 78522624f9SAdam Lee 79522624f9SAdam Lee #endif /* __SDHCI_PCI_H */ 80