1522624f9SAdam Lee #ifndef __SDHCI_PCI_H 2522624f9SAdam Lee #define __SDHCI_PCI_H 3522624f9SAdam Lee 4522624f9SAdam Lee /* 5c949c907SMatthias Kraemer * PCI device IDs, sub IDs 6522624f9SAdam Lee */ 7522624f9SAdam Lee 8361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SDS0 0x8420 9361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SDS1 0x8421 10361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 11361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 12361eeda0SAdrian Hunter #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 13361eeda0SAdrian Hunter 14522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 15522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a 16522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 17522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 18522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 19522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 20066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 21066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 22066173b6SAlan Cox #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 231f64cec2SAndy Shevchenko #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 24522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 25522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa 26522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb 27522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 28522624f9SAdam Lee #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 2943e968ceSDerek Browne #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 301f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b 311f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c 321f7f2652SAdrian Hunter #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d 3306bf9c56SAdrian Hunter #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db 34cdaba732SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db 354fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca 364fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc 374fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 3801d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca 3901d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc 4001d6b2a4SAdrian Hunter #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 414fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca 424fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc 434fd4c065SAdrian Hunter #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 442d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca 452d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc 462d1956d0SAdrian Hunter #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 47bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 48bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 49bc55dcd8SAdrian Hunter #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 50522624f9SAdam Lee 51c949c907SMatthias Kraemer #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 52c949c907SMatthias Kraemer #define PCI_DEVICE_ID_VIA_95D0 0x95d0 53c949c907SMatthias Kraemer #define PCI_DEVICE_ID_REALTEK_5250 0x5250 54c949c907SMatthias Kraemer 55c949c907SMatthias Kraemer #define PCI_SUBDEVICE_ID_NI_7884 0x7884 56c949c907SMatthias Kraemer 57c949c907SMatthias Kraemer /* 58c949c907SMatthias Kraemer * PCI device class and mask 59c949c907SMatthias Kraemer */ 60c949c907SMatthias Kraemer 61c949c907SMatthias Kraemer #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) 62c949c907SMatthias Kraemer #define PCI_CLASS_MASK 0xFFFF00 63c949c907SMatthias Kraemer 64c949c907SMatthias Kraemer /* 65c949c907SMatthias Kraemer * Macros for PCI device-description 66c949c907SMatthias Kraemer */ 67c949c907SMatthias Kraemer 68c949c907SMatthias Kraemer #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend 69c949c907SMatthias Kraemer #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev 70c949c907SMatthias Kraemer #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev 71c949c907SMatthias Kraemer 72c949c907SMatthias Kraemer #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ 73c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 74c949c907SMatthias Kraemer .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 75c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 76c949c907SMatthias Kraemer } 77c949c907SMatthias Kraemer 78c949c907SMatthias Kraemer #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ 79c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ 80c949c907SMatthias Kraemer .subvendor = _PCI_VEND(subvend), \ 81c949c907SMatthias Kraemer .subdevice = _PCI_SUBDEV(subvend, subdev), \ 82c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 83c949c907SMatthias Kraemer } 84c949c907SMatthias Kraemer 85c949c907SMatthias Kraemer #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ 86c949c907SMatthias Kraemer .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ 87c949c907SMatthias Kraemer .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ 88c949c907SMatthias Kraemer .class = (cl), .class_mask = (cl_msk), \ 89c949c907SMatthias Kraemer .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ 90c949c907SMatthias Kraemer } 91c949c907SMatthias Kraemer 92522624f9SAdam Lee /* 93522624f9SAdam Lee * PCI registers 94522624f9SAdam Lee */ 95522624f9SAdam Lee 96522624f9SAdam Lee #define PCI_SDHCI_IFPIO 0x00 97522624f9SAdam Lee #define PCI_SDHCI_IFDMA 0x01 98522624f9SAdam Lee #define PCI_SDHCI_IFVENDOR 0x02 99522624f9SAdam Lee 100522624f9SAdam Lee #define PCI_SLOT_INFO 0x40 /* 8 bits */ 101522624f9SAdam Lee #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) 102522624f9SAdam Lee #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 103522624f9SAdam Lee 104522624f9SAdam Lee #define MAX_SLOTS 8 105522624f9SAdam Lee 106522624f9SAdam Lee struct sdhci_pci_chip; 107522624f9SAdam Lee struct sdhci_pci_slot; 108522624f9SAdam Lee 109522624f9SAdam Lee struct sdhci_pci_fixes { 110522624f9SAdam Lee unsigned int quirks; 111522624f9SAdam Lee unsigned int quirks2; 112522624f9SAdam Lee bool allow_runtime_pm; 11377a0122eSAdrian Hunter bool own_cd_for_runtime_pm; 114522624f9SAdam Lee 115522624f9SAdam Lee int (*probe) (struct sdhci_pci_chip *); 116522624f9SAdam Lee 117522624f9SAdam Lee int (*probe_slot) (struct sdhci_pci_slot *); 11861c951deSAdrian Hunter int (*add_host) (struct sdhci_pci_slot *); 119522624f9SAdam Lee void (*remove_slot) (struct sdhci_pci_slot *, int); 120522624f9SAdam Lee 121b7813f0fSAdrian Hunter #ifdef CONFIG_PM_SLEEP 122522624f9SAdam Lee int (*suspend) (struct sdhci_pci_chip *); 123522624f9SAdam Lee int (*resume) (struct sdhci_pci_chip *); 124b7813f0fSAdrian Hunter #endif 125966d696aSAdrian Hunter #ifdef CONFIG_PM 126966d696aSAdrian Hunter int (*runtime_suspend) (struct sdhci_pci_chip *); 127966d696aSAdrian Hunter int (*runtime_resume) (struct sdhci_pci_chip *); 128966d696aSAdrian Hunter #endif 1296bc09063SAdrian Hunter 1306bc09063SAdrian Hunter const struct sdhci_ops *ops; 131ac9f67b5SAdrian Hunter size_t priv_size; 132522624f9SAdam Lee }; 133522624f9SAdam Lee 134522624f9SAdam Lee struct sdhci_pci_slot { 135522624f9SAdam Lee struct sdhci_pci_chip *chip; 136522624f9SAdam Lee struct sdhci_host *host; 137522624f9SAdam Lee struct sdhci_pci_data *data; 138522624f9SAdam Lee 139522624f9SAdam Lee int rst_n_gpio; 140522624f9SAdam Lee int cd_gpio; 141522624f9SAdam Lee int cd_irq; 142522624f9SAdam Lee 143ff59c520SAdrian Hunter int cd_idx; 144ff59c520SAdrian Hunter bool cd_override_level; 145ff59c520SAdrian Hunter 146522624f9SAdam Lee void (*hw_reset)(struct sdhci_host *host); 147ac9f67b5SAdrian Hunter unsigned long private[0] ____cacheline_aligned; 148522624f9SAdam Lee }; 149522624f9SAdam Lee 150522624f9SAdam Lee struct sdhci_pci_chip { 151522624f9SAdam Lee struct pci_dev *pdev; 152522624f9SAdam Lee 153522624f9SAdam Lee unsigned int quirks; 154522624f9SAdam Lee unsigned int quirks2; 155522624f9SAdam Lee bool allow_runtime_pm; 156d38dcad4SAdrian Hunter bool pm_retune; 157d38dcad4SAdrian Hunter bool rpm_retune; 158522624f9SAdam Lee const struct sdhci_pci_fixes *fixes; 159522624f9SAdam Lee 160522624f9SAdam Lee int num_slots; /* Slots on controller */ 161522624f9SAdam Lee struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ 162522624f9SAdam Lee }; 163522624f9SAdam Lee 164ac9f67b5SAdrian Hunter static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) 165ac9f67b5SAdrian Hunter { 166ac9f67b5SAdrian Hunter return (void *)slot->private; 167ac9f67b5SAdrian Hunter } 168ac9f67b5SAdrian Hunter 16930cf2803SAdrian Hunter #ifdef CONFIG_PM_SLEEP 17030cf2803SAdrian Hunter int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); 17130cf2803SAdrian Hunter #endif 17230cf2803SAdrian Hunter 173361eeda0SAdrian Hunter int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot); 174361eeda0SAdrian Hunter int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip); 175361eeda0SAdrian Hunter #ifdef CONFIG_PM_SLEEP 176361eeda0SAdrian Hunter int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip); 177361eeda0SAdrian Hunter #endif 178361eeda0SAdrian Hunter 179522624f9SAdam Lee #endif /* __SDHCI_PCI_H */ 180