1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 BayHub Technology Ltd.
4  *
5  * Authors: Peter Guo <peter.guo@bayhubtech.com>
6  *          Adam Lee <adam.lee@canonical.com>
7  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
8  */
9 
10 #include <linux/pci.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/delay.h>
14 #include <linux/iopoll.h>
15 
16 #include "sdhci.h"
17 #include "sdhci-pci.h"
18 
19 /*
20  * O2Micro device registers
21  */
22 
23 #define O2_SD_MISC_REG5		0x64
24 #define O2_SD_LD0_CTRL		0x68
25 #define O2_SD_DEV_CTRL		0x88
26 #define O2_SD_LOCK_WP		0xD3
27 #define O2_SD_TEST_REG		0xD4
28 #define O2_SD_FUNC_REG0		0xDC
29 #define O2_SD_MULTI_VCC3V	0xEE
30 #define O2_SD_CLKREQ		0xEC
31 #define O2_SD_CAPS		0xE0
32 #define O2_SD_ADMA1		0xE2
33 #define O2_SD_ADMA2		0xE7
34 #define O2_SD_INF_MOD		0xF1
35 #define O2_SD_MISC_CTRL4	0xFC
36 #define O2_SD_MISC_CTRL		0x1C0
37 #define O2_SD_PWR_FORCE_L0	0x0002
38 #define O2_SD_TUNING_CTRL	0x300
39 #define O2_SD_PLL_SETTING	0x304
40 #define O2_SD_MISC_SETTING	0x308
41 #define O2_SD_CLK_SETTING	0x328
42 #define O2_SD_CAP_REG2		0x330
43 #define O2_SD_CAP_REG0		0x334
44 #define O2_SD_UHS1_CAP_SETTING	0x33C
45 #define O2_SD_DELAY_CTRL	0x350
46 #define O2_SD_UHS2_L1_CTRL	0x35C
47 #define O2_SD_FUNC_REG3		0x3E0
48 #define O2_SD_FUNC_REG4		0x3E4
49 #define O2_SD_LED_ENABLE	BIT(6)
50 #define O2_SD_FREG0_LEDOFF	BIT(13)
51 #define O2_SD_FREG4_ENABLE_CLK_SET	BIT(22)
52 
53 #define O2_SD_VENDOR_SETTING	0x110
54 #define O2_SD_VENDOR_SETTING2	0x1C8
55 #define O2_SD_HW_TUNING_DISABLE	BIT(4)
56 
57 #define O2_PLL_DLL_WDT_CONTROL1	0x1CC
58 #define  O2_PLL_FORCE_ACTIVE	BIT(18)
59 #define  O2_PLL_LOCK_STATUS	BIT(14)
60 #define  O2_PLL_SOFT_RESET	BIT(12)
61 #define  O2_DLL_LOCK_STATUS	BIT(11)
62 
63 #define O2_SD_DETECT_SETTING 0x324
64 
65 static const u32 dmdn_table[] = {0x2B1C0000,
66 	0x2C1A0000, 0x371B0000, 0x35100000};
67 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
68 
69 struct o2_host {
70 	u8 dll_adjust_count;
71 };
72 
73 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
74 {
75 	ktime_t timeout;
76 	u32 scratch32;
77 
78 	/* Wait max 50 ms */
79 	timeout = ktime_add_ms(ktime_get(), 50);
80 	while (1) {
81 		bool timedout = ktime_after(ktime_get(), timeout);
82 
83 		scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
84 		if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
85 		    == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
86 			break;
87 
88 		if (timedout) {
89 			pr_err("%s: Card Detect debounce never finished.\n",
90 			       mmc_hostname(host->mmc));
91 			sdhci_dumpregs(host);
92 			return;
93 		}
94 		udelay(10);
95 	}
96 }
97 
98 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
99 {
100 	ktime_t timeout;
101 	u16 scratch;
102 	u32 scratch32;
103 
104 	/* PLL software reset */
105 	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
106 	scratch32 |= O2_PLL_SOFT_RESET;
107 	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
108 	udelay(1);
109 	scratch32 &= ~(O2_PLL_SOFT_RESET);
110 	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
111 
112 	/* PLL force active */
113 	scratch32 |= O2_PLL_FORCE_ACTIVE;
114 	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
115 
116 	/* Wait max 20 ms */
117 	timeout = ktime_add_ms(ktime_get(), 20);
118 	while (1) {
119 		bool timedout = ktime_after(ktime_get(), timeout);
120 
121 		scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
122 		if (scratch & O2_PLL_LOCK_STATUS)
123 			break;
124 		if (timedout) {
125 			pr_err("%s: Internal clock never stabilised.\n",
126 			       mmc_hostname(host->mmc));
127 			sdhci_dumpregs(host);
128 			goto out;
129 		}
130 		udelay(10);
131 	}
132 
133 	/* Wait for card detect finish */
134 	udelay(1);
135 	sdhci_o2_wait_card_detect_stable(host);
136 
137 out:
138 	/* Cancel PLL force active */
139 	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
140 	scratch32 &= ~O2_PLL_FORCE_ACTIVE;
141 	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
142 }
143 
144 static int sdhci_o2_get_cd(struct mmc_host *mmc)
145 {
146 	struct sdhci_host *host = mmc_priv(mmc);
147 
148 	if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
149 		sdhci_o2_enable_internal_clock(host);
150 
151 	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
152 }
153 
154 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
155 {
156 	u32 scratch_32;
157 
158 	pci_read_config_dword(chip->pdev,
159 			      O2_SD_PLL_SETTING, &scratch_32);
160 
161 	scratch_32 &= 0x0000FFFF;
162 	scratch_32 |= value;
163 
164 	pci_write_config_dword(chip->pdev,
165 			       O2_SD_PLL_SETTING, scratch_32);
166 }
167 
168 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
169 {
170 	return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
171 }
172 
173 /*
174  * This function is used to detect dll lock status.
175  * Since the dll lock status bit will toggle randomly
176  * with very short interval which needs to be polled
177  * as fast as possible. Set sleep_us as 1 microsecond.
178  */
179 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
180 {
181 	u32	scratch32 = 0;
182 
183 	return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
184 		scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
185 }
186 
187 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
188 {
189 	u16 reg;
190 
191 	/* enable hardware tuning */
192 	reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
193 	reg &= ~O2_SD_HW_TUNING_DISABLE;
194 	sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
195 }
196 
197 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
198 {
199 	int i;
200 
201 	sdhci_send_tuning(host, opcode);
202 
203 	for (i = 0; i < 150; i++) {
204 		u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
205 
206 		if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
207 			if (ctrl & SDHCI_CTRL_TUNED_CLK) {
208 				host->tuning_done = true;
209 				return;
210 			}
211 			pr_warn("%s: HW tuning failed !\n",
212 				mmc_hostname(host->mmc));
213 			break;
214 		}
215 
216 		mdelay(1);
217 	}
218 
219 	pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
220 		mmc_hostname(host->mmc));
221 	sdhci_reset_tuning(host);
222 }
223 
224 /*
225  * This function is used to fix o2 dll shift issue.
226  * It isn't necessary to detect card present before recovery.
227  * Firstly, it is used by bht emmc card, which is embedded.
228  * Second, before call recovery card present will be detected
229  * outside of the execute tuning function.
230  */
231 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
232 {
233 	int ret = 0;
234 	u8 scratch_8 = 0;
235 	u32 scratch_32 = 0;
236 	struct sdhci_pci_slot *slot = sdhci_priv(host);
237 	struct sdhci_pci_chip *chip = slot->chip;
238 	struct o2_host *o2_host = sdhci_pci_priv(slot);
239 
240 	/* UnLock WP */
241 	pci_read_config_byte(chip->pdev,
242 			O2_SD_LOCK_WP, &scratch_8);
243 	scratch_8 &= 0x7f;
244 	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
245 	while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
246 		/* Disable clock */
247 		sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
248 
249 		/* PLL software reset */
250 		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
251 		scratch_32 |= O2_PLL_SOFT_RESET;
252 		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
253 
254 		pci_read_config_dword(chip->pdev,
255 					    O2_SD_FUNC_REG4,
256 					    &scratch_32);
257 		/* Enable Base Clk setting change */
258 		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
259 		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
260 		o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
261 
262 		/* Enable internal clock */
263 		scratch_8 = SDHCI_CLOCK_INT_EN;
264 		sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
265 
266 		if (sdhci_o2_get_cd(host->mmc)) {
267 			/*
268 			 * need wait at least 5ms for dll status stable,
269 			 * after enable internal clock
270 			 */
271 			usleep_range(5000, 6000);
272 			if (sdhci_o2_wait_dll_detect_lock(host)) {
273 				scratch_8 |= SDHCI_CLOCK_CARD_EN;
274 				sdhci_writeb(host, scratch_8,
275 					SDHCI_CLOCK_CONTROL);
276 				ret = 1;
277 			} else {
278 				pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
279 					mmc_hostname(host->mmc),
280 					o2_host->dll_adjust_count);
281 			}
282 		} else {
283 			pr_err("%s: card present detect failed.\n",
284 				mmc_hostname(host->mmc));
285 			break;
286 		}
287 
288 		o2_host->dll_adjust_count++;
289 	}
290 	if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
291 		pr_err("%s: DLL adjust over max times\n",
292 		mmc_hostname(host->mmc));
293 	/* Lock WP */
294 	pci_read_config_byte(chip->pdev,
295 				   O2_SD_LOCK_WP, &scratch_8);
296 	scratch_8 |= 0x80;
297 	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
298 	return ret;
299 }
300 
301 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
302 {
303 	struct sdhci_host *host = mmc_priv(mmc);
304 	int current_bus_width = 0;
305 	u32 scratch32 = 0;
306 	u16 scratch = 0;
307 
308 	/*
309 	 * This handler only implements the eMMC tuning that is specific to
310 	 * this controller.  Fall back to the standard method for other TIMING.
311 	 */
312 	if ((host->timing != MMC_TIMING_MMC_HS200) &&
313 		(host->timing != MMC_TIMING_UHS_SDR104))
314 		return sdhci_execute_tuning(mmc, opcode);
315 
316 	if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
317 			(opcode != MMC_SEND_TUNING_BLOCK)))
318 		return -EINVAL;
319 
320 	/* Force power mode enter L0 */
321 	scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
322 	scratch |= O2_SD_PWR_FORCE_L0;
323 	sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
324 
325 	/* wait DLL lock, timeout value 5ms */
326 	if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
327 		scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
328 		pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
329 				mmc_hostname(host->mmc));
330 	/*
331 	 * Judge the tuning reason, whether caused by dll shift
332 	 * If cause by dll shift, should call sdhci_o2_dll_recovery
333 	 */
334 	if (!sdhci_o2_wait_dll_detect_lock(host))
335 		if (!sdhci_o2_dll_recovery(host)) {
336 			pr_err("%s: o2 dll recovery failed\n",
337 				mmc_hostname(host->mmc));
338 			return -EINVAL;
339 		}
340 	/*
341 	 * o2 sdhci host didn't support 8bit emmc tuning
342 	 */
343 	if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
344 		current_bus_width = mmc->ios.bus_width;
345 		mmc->ios.bus_width = MMC_BUS_WIDTH_4;
346 		sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
347 	}
348 
349 	sdhci_o2_set_tuning_mode(host);
350 
351 	sdhci_start_tuning(host);
352 
353 	__sdhci_o2_execute_tuning(host, opcode);
354 
355 	sdhci_end_tuning(host);
356 
357 	if (current_bus_width == MMC_BUS_WIDTH_8) {
358 		mmc->ios.bus_width = MMC_BUS_WIDTH_8;
359 		sdhci_set_bus_width(host, current_bus_width);
360 	}
361 
362 	/* Cancel force power mode enter L0 */
363 	scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
364 	scratch &= ~(O2_SD_PWR_FORCE_L0);
365 	sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
366 
367 	sdhci_reset(host, SDHCI_RESET_CMD);
368 	sdhci_reset(host, SDHCI_RESET_DATA);
369 
370 	host->flags &= ~SDHCI_HS400_TUNING;
371 	return 0;
372 }
373 
374 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
375 {
376 	int ret;
377 	u32 scratch_32;
378 
379 	/* Set led of SD host function enable */
380 	ret = pci_read_config_dword(chip->pdev,
381 				    O2_SD_FUNC_REG0, &scratch_32);
382 	if (ret)
383 		return;
384 
385 	scratch_32 &= ~O2_SD_FREG0_LEDOFF;
386 	pci_write_config_dword(chip->pdev,
387 			       O2_SD_FUNC_REG0, scratch_32);
388 
389 	ret = pci_read_config_dword(chip->pdev,
390 				    O2_SD_TEST_REG, &scratch_32);
391 	if (ret)
392 		return;
393 
394 	scratch_32 |= O2_SD_LED_ENABLE;
395 	pci_write_config_dword(chip->pdev,
396 			       O2_SD_TEST_REG, scratch_32);
397 }
398 
399 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
400 {
401 	u32 scratch_32;
402 	int ret;
403 	/* Improve write performance for SD3.0 */
404 	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
405 	if (ret)
406 		return;
407 	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
408 	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
409 
410 	/* Enable Link abnormal reset generating Reset */
411 	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
412 	if (ret)
413 		return;
414 	scratch_32 &= ~((1 << 19) | (1 << 11));
415 	scratch_32 |= (1 << 10);
416 	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
417 
418 	/* set card power over current protection */
419 	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
420 	if (ret)
421 		return;
422 	scratch_32 |= (1 << 4);
423 	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
424 
425 	/* adjust the output delay for SD mode */
426 	pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
427 
428 	/* Set the output voltage setting of Aux 1.2v LDO */
429 	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
430 	if (ret)
431 		return;
432 	scratch_32 &= ~(3 << 12);
433 	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
434 
435 	/* Set Max power supply capability of SD host */
436 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
437 	if (ret)
438 		return;
439 	scratch_32 &= ~(0x01FE);
440 	scratch_32 |= 0x00CC;
441 	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
442 	/* Set DLL Tuning Window */
443 	ret = pci_read_config_dword(chip->pdev,
444 				    O2_SD_TUNING_CTRL, &scratch_32);
445 	if (ret)
446 		return;
447 	scratch_32 &= ~(0x000000FF);
448 	scratch_32 |= 0x00000066;
449 	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
450 
451 	/* Set UHS2 T_EIDLE */
452 	ret = pci_read_config_dword(chip->pdev,
453 				    O2_SD_UHS2_L1_CTRL, &scratch_32);
454 	if (ret)
455 		return;
456 	scratch_32 &= ~(0x000000FC);
457 	scratch_32 |= 0x00000084;
458 	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
459 
460 	/* Set UHS2 Termination */
461 	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
462 	if (ret)
463 		return;
464 	scratch_32 &= ~((1 << 21) | (1 << 30));
465 
466 	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
467 
468 	/* Set L1 Entrance Timer */
469 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
470 	if (ret)
471 		return;
472 	scratch_32 &= ~(0xf0000000);
473 	scratch_32 |= 0x30000000;
474 	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
475 
476 	ret = pci_read_config_dword(chip->pdev,
477 				    O2_SD_MISC_CTRL4, &scratch_32);
478 	if (ret)
479 		return;
480 	scratch_32 &= ~(0x000f0000);
481 	scratch_32 |= 0x00080000;
482 	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
483 }
484 
485 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
486 				    struct sdhci_host *host)
487 {
488 	int ret;
489 
490 	ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
491 	if (!ret) {
492 		pr_info("%s: unsupport msi, use INTx irq\n",
493 			mmc_hostname(host->mmc));
494 		return;
495 	}
496 
497 	ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
498 				    PCI_IRQ_MSI | PCI_IRQ_MSIX);
499 	if (ret < 0) {
500 		pr_err("%s: enable PCI MSI failed, err=%d\n",
501 		       mmc_hostname(host->mmc), ret);
502 		return;
503 	}
504 
505 	host->irq = pci_irq_vector(chip->pdev, 0);
506 }
507 
508 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
509 {
510 	/* Enable internal clock */
511 	clk |= SDHCI_CLOCK_INT_EN;
512 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
513 
514 	sdhci_o2_enable_internal_clock(host);
515 	if (sdhci_o2_get_cd(host->mmc)) {
516 		clk |= SDHCI_CLOCK_CARD_EN;
517 		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
518 	}
519 }
520 
521 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
522 {
523 	u16 clk;
524 	u8 scratch;
525 	u32 scratch_32;
526 	struct sdhci_pci_slot *slot = sdhci_priv(host);
527 	struct sdhci_pci_chip *chip = slot->chip;
528 
529 	host->mmc->actual_clock = 0;
530 
531 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
532 
533 	if (clock == 0)
534 		return;
535 
536 	if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
537 		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
538 
539 		scratch &= 0x7f;
540 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
541 
542 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
543 
544 		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
545 			o2_pci_set_baseclk(chip, 0x2c280000);
546 
547 		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
548 
549 		scratch |= 0x80;
550 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
551 	}
552 
553 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
554 	sdhci_o2_enable_clk(host, clk);
555 }
556 
557 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
558 {
559 	struct sdhci_pci_chip *chip;
560 	struct sdhci_host *host;
561 	struct o2_host *o2_host = sdhci_pci_priv(slot);
562 	u32 reg, caps;
563 	int ret;
564 
565 	chip = slot->chip;
566 	host = slot->host;
567 
568 	o2_host->dll_adjust_count = 0;
569 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
570 
571 	/*
572 	 * mmc_select_bus_width() will test the bus to determine the actual bus
573 	 * width.
574 	 */
575 	if (caps & SDHCI_CAN_DO_8BIT)
576 		host->mmc->caps |= MMC_CAP_8_BIT_DATA;
577 
578 	switch (chip->pdev->device) {
579 	case PCI_DEVICE_ID_O2_SDS0:
580 	case PCI_DEVICE_ID_O2_SEABIRD0:
581 	case PCI_DEVICE_ID_O2_SEABIRD1:
582 	case PCI_DEVICE_ID_O2_SDS1:
583 	case PCI_DEVICE_ID_O2_FUJIN2:
584 		reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
585 		if (reg & 0x1)
586 			host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
587 
588 		sdhci_pci_o2_enable_msi(chip, host);
589 
590 		if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
591 			ret = pci_read_config_dword(chip->pdev,
592 						    O2_SD_MISC_SETTING, &reg);
593 			if (ret)
594 				return -EIO;
595 			if (reg & (1 << 4)) {
596 				pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
597 					mmc_hostname(host->mmc));
598 				host->flags &= ~SDHCI_SIGNALING_330;
599 				host->flags |= SDHCI_SIGNALING_180;
600 				host->mmc->caps2 |= MMC_CAP2_NO_SD;
601 				host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
602 				pci_write_config_dword(chip->pdev,
603 						       O2_SD_DETECT_SETTING, 3);
604 			}
605 
606 			slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
607 		}
608 
609 		if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
610 			slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
611 			host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
612 			host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
613 		}
614 
615 		host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
616 
617 		if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
618 			break;
619 		/* set dll watch dog timer */
620 		reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
621 		reg |= (1 << 12);
622 		sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
623 
624 		break;
625 	default:
626 		break;
627 	}
628 
629 	return 0;
630 }
631 
632 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
633 {
634 	int ret;
635 	u8 scratch;
636 	u32 scratch_32;
637 
638 	switch (chip->pdev->device) {
639 	case PCI_DEVICE_ID_O2_8220:
640 	case PCI_DEVICE_ID_O2_8221:
641 	case PCI_DEVICE_ID_O2_8320:
642 	case PCI_DEVICE_ID_O2_8321:
643 		/* This extra setup is required due to broken ADMA. */
644 		ret = pci_read_config_byte(chip->pdev,
645 				O2_SD_LOCK_WP, &scratch);
646 		if (ret)
647 			return ret;
648 		scratch &= 0x7f;
649 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
650 
651 		/* Set Multi 3 to VCC3V# */
652 		pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
653 
654 		/* Disable CLK_REQ# support after media DET */
655 		ret = pci_read_config_byte(chip->pdev,
656 				O2_SD_CLKREQ, &scratch);
657 		if (ret)
658 			return ret;
659 		scratch |= 0x20;
660 		pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
661 
662 		/* Choose capabilities, enable SDMA.  We have to write 0x01
663 		 * to the capabilities register first to unlock it.
664 		 */
665 		ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
666 		if (ret)
667 			return ret;
668 		scratch |= 0x01;
669 		pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
670 		pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
671 
672 		/* Disable ADMA1/2 */
673 		pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
674 		pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
675 
676 		/* Disable the infinite transfer mode */
677 		ret = pci_read_config_byte(chip->pdev,
678 				O2_SD_INF_MOD, &scratch);
679 		if (ret)
680 			return ret;
681 		scratch |= 0x08;
682 		pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
683 
684 		/* Lock WP */
685 		ret = pci_read_config_byte(chip->pdev,
686 				O2_SD_LOCK_WP, &scratch);
687 		if (ret)
688 			return ret;
689 		scratch |= 0x80;
690 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
691 		break;
692 	case PCI_DEVICE_ID_O2_SDS0:
693 	case PCI_DEVICE_ID_O2_SDS1:
694 	case PCI_DEVICE_ID_O2_FUJIN2:
695 		/* UnLock WP */
696 		ret = pci_read_config_byte(chip->pdev,
697 				O2_SD_LOCK_WP, &scratch);
698 		if (ret)
699 			return ret;
700 
701 		scratch &= 0x7f;
702 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
703 
704 		/* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
705 		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
706 			ret = pci_read_config_dword(chip->pdev,
707 						    O2_SD_FUNC_REG0,
708 						    &scratch_32);
709 			if (ret)
710 				return ret;
711 			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
712 
713 			/* Check Whether subId is 0x11 or 0x12 */
714 			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
715 				scratch_32 = 0x25100000;
716 
717 				o2_pci_set_baseclk(chip, scratch_32);
718 				ret = pci_read_config_dword(chip->pdev,
719 							    O2_SD_FUNC_REG4,
720 							    &scratch_32);
721 				if (ret)
722 					return ret;
723 
724 				/* Enable Base Clk setting change */
725 				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
726 				pci_write_config_dword(chip->pdev,
727 						       O2_SD_FUNC_REG4,
728 						       scratch_32);
729 
730 				/* Set Tuning Window to 4 */
731 				pci_write_config_byte(chip->pdev,
732 						      O2_SD_TUNING_CTRL, 0x44);
733 
734 				break;
735 			}
736 		}
737 
738 		/* Enable 8520 led function */
739 		o2_pci_led_enable(chip);
740 
741 		/* Set timeout CLK */
742 		ret = pci_read_config_dword(chip->pdev,
743 					    O2_SD_CLK_SETTING, &scratch_32);
744 		if (ret)
745 			return ret;
746 
747 		scratch_32 &= ~(0xFF00);
748 		scratch_32 |= 0x07E0C800;
749 		pci_write_config_dword(chip->pdev,
750 				       O2_SD_CLK_SETTING, scratch_32);
751 
752 		ret = pci_read_config_dword(chip->pdev,
753 					    O2_SD_CLKREQ, &scratch_32);
754 		if (ret)
755 			return ret;
756 		scratch_32 |= 0x3;
757 		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
758 
759 		ret = pci_read_config_dword(chip->pdev,
760 					    O2_SD_PLL_SETTING, &scratch_32);
761 		if (ret)
762 			return ret;
763 
764 		scratch_32 &= ~(0x1F3F070E);
765 		scratch_32 |= 0x18270106;
766 		pci_write_config_dword(chip->pdev,
767 				       O2_SD_PLL_SETTING, scratch_32);
768 
769 		/* Disable UHS1 funciton */
770 		ret = pci_read_config_dword(chip->pdev,
771 					    O2_SD_CAP_REG2, &scratch_32);
772 		if (ret)
773 			return ret;
774 		scratch_32 &= ~(0xE0);
775 		pci_write_config_dword(chip->pdev,
776 				       O2_SD_CAP_REG2, scratch_32);
777 
778 		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
779 			sdhci_pci_o2_fujin2_pci_init(chip);
780 
781 		/* Lock WP */
782 		ret = pci_read_config_byte(chip->pdev,
783 					   O2_SD_LOCK_WP, &scratch);
784 		if (ret)
785 			return ret;
786 		scratch |= 0x80;
787 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
788 		break;
789 	case PCI_DEVICE_ID_O2_SEABIRD0:
790 	case PCI_DEVICE_ID_O2_SEABIRD1:
791 		/* UnLock WP */
792 		ret = pci_read_config_byte(chip->pdev,
793 				O2_SD_LOCK_WP, &scratch);
794 		if (ret)
795 			return ret;
796 
797 		scratch &= 0x7f;
798 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
799 
800 		ret = pci_read_config_dword(chip->pdev,
801 					    O2_SD_PLL_SETTING, &scratch_32);
802 		if (ret)
803 			return ret;
804 
805 		if ((scratch_32 & 0xff000000) == 0x01000000) {
806 			scratch_32 &= 0x0000FFFF;
807 			scratch_32 |= 0x1F340000;
808 
809 			pci_write_config_dword(chip->pdev,
810 					       O2_SD_PLL_SETTING, scratch_32);
811 		} else {
812 			scratch_32 &= 0x0000FFFF;
813 			scratch_32 |= 0x25100000;
814 
815 			pci_write_config_dword(chip->pdev,
816 					       O2_SD_PLL_SETTING, scratch_32);
817 
818 			ret = pci_read_config_dword(chip->pdev,
819 						    O2_SD_FUNC_REG4,
820 						    &scratch_32);
821 			if (ret)
822 				return ret;
823 			scratch_32 |= (1 << 22);
824 			pci_write_config_dword(chip->pdev,
825 					       O2_SD_FUNC_REG4, scratch_32);
826 		}
827 
828 		/* Set Tuning Windows to 5 */
829 		pci_write_config_byte(chip->pdev,
830 				O2_SD_TUNING_CTRL, 0x55);
831 		/* Lock WP */
832 		ret = pci_read_config_byte(chip->pdev,
833 					   O2_SD_LOCK_WP, &scratch);
834 		if (ret)
835 			return ret;
836 		scratch |= 0x80;
837 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
838 		break;
839 	}
840 
841 	return 0;
842 }
843 
844 #ifdef CONFIG_PM_SLEEP
845 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
846 {
847 	sdhci_pci_o2_probe(chip);
848 	return sdhci_pci_resume_host(chip);
849 }
850 #endif
851 
852 static const struct sdhci_ops sdhci_pci_o2_ops = {
853 	.set_clock = sdhci_pci_o2_set_clock,
854 	.enable_dma = sdhci_pci_enable_dma,
855 	.set_bus_width = sdhci_set_bus_width,
856 	.reset = sdhci_reset,
857 	.set_uhs_signaling = sdhci_set_uhs_signaling,
858 };
859 
860 const struct sdhci_pci_fixes sdhci_o2 = {
861 	.probe = sdhci_pci_o2_probe,
862 	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
863 	.quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
864 	.probe_slot = sdhci_pci_o2_probe_slot,
865 #ifdef CONFIG_PM_SLEEP
866 	.resume = sdhci_pci_o2_resume,
867 #endif
868 	.ops = &sdhci_pci_o2_ops,
869 	.priv_size = sizeof(struct o2_host),
870 };
871