1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 BayHub Technology Ltd. 4 * 5 * Authors: Peter Guo <peter.guo@bayhubtech.com> 6 * Adam Lee <adam.lee@canonical.com> 7 * Ernest Zhang <ernest.zhang@bayhubtech.com> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/delay.h> 14 15 #include "sdhci.h" 16 #include "sdhci-pci.h" 17 18 /* 19 * O2Micro device registers 20 */ 21 22 #define O2_SD_MISC_REG5 0x64 23 #define O2_SD_LD0_CTRL 0x68 24 #define O2_SD_DEV_CTRL 0x88 25 #define O2_SD_LOCK_WP 0xD3 26 #define O2_SD_TEST_REG 0xD4 27 #define O2_SD_FUNC_REG0 0xDC 28 #define O2_SD_MULTI_VCC3V 0xEE 29 #define O2_SD_CLKREQ 0xEC 30 #define O2_SD_CAPS 0xE0 31 #define O2_SD_ADMA1 0xE2 32 #define O2_SD_ADMA2 0xE7 33 #define O2_SD_INF_MOD 0xF1 34 #define O2_SD_MISC_CTRL4 0xFC 35 #define O2_SD_TUNING_CTRL 0x300 36 #define O2_SD_PLL_SETTING 0x304 37 #define O2_SD_MISC_SETTING 0x308 38 #define O2_SD_CLK_SETTING 0x328 39 #define O2_SD_CAP_REG2 0x330 40 #define O2_SD_CAP_REG0 0x334 41 #define O2_SD_UHS1_CAP_SETTING 0x33C 42 #define O2_SD_DELAY_CTRL 0x350 43 #define O2_SD_UHS2_L1_CTRL 0x35C 44 #define O2_SD_FUNC_REG3 0x3E0 45 #define O2_SD_FUNC_REG4 0x3E4 46 #define O2_SD_LED_ENABLE BIT(6) 47 #define O2_SD_FREG0_LEDOFF BIT(13) 48 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 49 50 #define O2_SD_VENDOR_SETTING 0x110 51 #define O2_SD_VENDOR_SETTING2 0x1C8 52 #define O2_SD_HW_TUNING_DISABLE BIT(4) 53 54 #define O2_PLL_WDT_CONTROL1 0x1CC 55 #define O2_PLL_FORCE_ACTIVE BIT(18) 56 #define O2_PLL_LOCK_STATUS BIT(14) 57 #define O2_PLL_SOFT_RESET BIT(12) 58 59 #define O2_SD_DETECT_SETTING 0x324 60 61 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 62 { 63 u16 reg; 64 65 /* enable hardware tuning */ 66 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 67 reg &= ~O2_SD_HW_TUNING_DISABLE; 68 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 69 } 70 71 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 72 { 73 int i; 74 75 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200); 76 77 for (i = 0; i < 150; i++) { 78 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 79 80 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 81 if (ctrl & SDHCI_CTRL_TUNED_CLK) { 82 host->tuning_done = true; 83 return; 84 } 85 pr_warn("%s: HW tuning failed !\n", 86 mmc_hostname(host->mmc)); 87 break; 88 } 89 90 mdelay(1); 91 } 92 93 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 94 mmc_hostname(host->mmc)); 95 sdhci_reset_tuning(host); 96 } 97 98 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 99 { 100 struct sdhci_host *host = mmc_priv(mmc); 101 int current_bus_width = 0; 102 103 /* 104 * This handler only implements the eMMC tuning that is specific to 105 * this controller. Fall back to the standard method for other TIMING. 106 */ 107 if (host->timing != MMC_TIMING_MMC_HS200) 108 return sdhci_execute_tuning(mmc, opcode); 109 110 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) 111 return -EINVAL; 112 113 /* 114 * o2 sdhci host didn't support 8bit emmc tuning 115 */ 116 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 117 current_bus_width = mmc->ios.bus_width; 118 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 119 } 120 121 sdhci_o2_set_tuning_mode(host); 122 123 sdhci_start_tuning(host); 124 125 __sdhci_o2_execute_tuning(host, opcode); 126 127 sdhci_end_tuning(host); 128 129 if (current_bus_width == MMC_BUS_WIDTH_8) 130 sdhci_set_bus_width(host, current_bus_width); 131 132 host->flags &= ~SDHCI_HS400_TUNING; 133 return 0; 134 } 135 136 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 137 { 138 u32 scratch_32; 139 pci_read_config_dword(chip->pdev, 140 O2_SD_PLL_SETTING, &scratch_32); 141 142 scratch_32 &= 0x0000FFFF; 143 scratch_32 |= value; 144 145 pci_write_config_dword(chip->pdev, 146 O2_SD_PLL_SETTING, scratch_32); 147 } 148 149 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 150 { 151 int ret; 152 u32 scratch_32; 153 154 /* Set led of SD host function enable */ 155 ret = pci_read_config_dword(chip->pdev, 156 O2_SD_FUNC_REG0, &scratch_32); 157 if (ret) 158 return; 159 160 scratch_32 &= ~O2_SD_FREG0_LEDOFF; 161 pci_write_config_dword(chip->pdev, 162 O2_SD_FUNC_REG0, scratch_32); 163 164 ret = pci_read_config_dword(chip->pdev, 165 O2_SD_TEST_REG, &scratch_32); 166 if (ret) 167 return; 168 169 scratch_32 |= O2_SD_LED_ENABLE; 170 pci_write_config_dword(chip->pdev, 171 O2_SD_TEST_REG, scratch_32); 172 173 } 174 175 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 176 { 177 u32 scratch_32; 178 int ret; 179 /* Improve write performance for SD3.0 */ 180 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 181 if (ret) 182 return; 183 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 184 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 185 186 /* Enable Link abnormal reset generating Reset */ 187 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 188 if (ret) 189 return; 190 scratch_32 &= ~((1 << 19) | (1 << 11)); 191 scratch_32 |= (1 << 10); 192 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 193 194 /* set card power over current protection */ 195 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 196 if (ret) 197 return; 198 scratch_32 |= (1 << 4); 199 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 200 201 /* adjust the output delay for SD mode */ 202 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 203 204 /* Set the output voltage setting of Aux 1.2v LDO */ 205 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 206 if (ret) 207 return; 208 scratch_32 &= ~(3 << 12); 209 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 210 211 /* Set Max power supply capability of SD host */ 212 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 213 if (ret) 214 return; 215 scratch_32 &= ~(0x01FE); 216 scratch_32 |= 0x00CC; 217 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 218 /* Set DLL Tuning Window */ 219 ret = pci_read_config_dword(chip->pdev, 220 O2_SD_TUNING_CTRL, &scratch_32); 221 if (ret) 222 return; 223 scratch_32 &= ~(0x000000FF); 224 scratch_32 |= 0x00000066; 225 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 226 227 /* Set UHS2 T_EIDLE */ 228 ret = pci_read_config_dword(chip->pdev, 229 O2_SD_UHS2_L1_CTRL, &scratch_32); 230 if (ret) 231 return; 232 scratch_32 &= ~(0x000000FC); 233 scratch_32 |= 0x00000084; 234 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 235 236 /* Set UHS2 Termination */ 237 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 238 if (ret) 239 return; 240 scratch_32 &= ~((1 << 21) | (1 << 30)); 241 242 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 243 244 /* Set L1 Entrance Timer */ 245 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 246 if (ret) 247 return; 248 scratch_32 &= ~(0xf0000000); 249 scratch_32 |= 0x30000000; 250 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 251 252 ret = pci_read_config_dword(chip->pdev, 253 O2_SD_MISC_CTRL4, &scratch_32); 254 if (ret) 255 return; 256 scratch_32 &= ~(0x000f0000); 257 scratch_32 |= 0x00080000; 258 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 259 } 260 261 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 262 struct sdhci_host *host) 263 { 264 int ret; 265 266 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 267 if (!ret) { 268 pr_info("%s: unsupport msi, use INTx irq\n", 269 mmc_hostname(host->mmc)); 270 return; 271 } 272 273 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 274 PCI_IRQ_MSI | PCI_IRQ_MSIX); 275 if (ret < 0) { 276 pr_err("%s: enable PCI MSI failed, err=%d\n", 277 mmc_hostname(host->mmc), ret); 278 return; 279 } 280 281 host->irq = pci_irq_vector(chip->pdev, 0); 282 } 283 284 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 285 { 286 ktime_t timeout; 287 u32 scratch32; 288 289 /* Wait max 50 ms */ 290 timeout = ktime_add_ms(ktime_get(), 50); 291 while (1) { 292 bool timedout = ktime_after(ktime_get(), timeout); 293 294 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 295 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 296 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 297 break; 298 299 if (timedout) { 300 pr_err("%s: Card Detect debounce never finished.\n", 301 mmc_hostname(host->mmc)); 302 sdhci_dumpregs(host); 303 return; 304 } 305 udelay(10); 306 } 307 } 308 309 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 310 { 311 ktime_t timeout; 312 u16 scratch; 313 u32 scratch32; 314 315 /* PLL software reset */ 316 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 317 scratch32 |= O2_PLL_SOFT_RESET; 318 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 319 udelay(1); 320 scratch32 &= ~(O2_PLL_SOFT_RESET); 321 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 322 323 /* PLL force active */ 324 scratch32 |= O2_PLL_FORCE_ACTIVE; 325 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 326 327 /* Wait max 20 ms */ 328 timeout = ktime_add_ms(ktime_get(), 20); 329 while (1) { 330 bool timedout = ktime_after(ktime_get(), timeout); 331 332 scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1); 333 if (scratch & O2_PLL_LOCK_STATUS) 334 break; 335 if (timedout) { 336 pr_err("%s: Internal clock never stabilised.\n", 337 mmc_hostname(host->mmc)); 338 sdhci_dumpregs(host); 339 goto out; 340 } 341 udelay(10); 342 } 343 344 /* Wait for card detect finish */ 345 udelay(1); 346 sdhci_o2_wait_card_detect_stable(host); 347 348 out: 349 /* Cancel PLL force active */ 350 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 351 scratch32 &= ~O2_PLL_FORCE_ACTIVE; 352 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 353 } 354 355 static int sdhci_o2_get_cd(struct mmc_host *mmc) 356 { 357 struct sdhci_host *host = mmc_priv(mmc); 358 359 sdhci_o2_enable_internal_clock(host); 360 361 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 362 } 363 364 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 365 { 366 /* Enable internal clock */ 367 clk |= SDHCI_CLOCK_INT_EN; 368 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 369 370 if (sdhci_o2_get_cd(host->mmc)) { 371 clk |= SDHCI_CLOCK_CARD_EN; 372 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 373 } 374 } 375 376 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 377 { 378 u16 clk; 379 380 host->mmc->actual_clock = 0; 381 382 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 383 384 if (clock == 0) 385 return; 386 387 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 388 sdhci_o2_enable_clk(host, clk); 389 } 390 391 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 392 { 393 struct sdhci_pci_chip *chip; 394 struct sdhci_host *host; 395 u32 reg; 396 int ret; 397 398 chip = slot->chip; 399 host = slot->host; 400 switch (chip->pdev->device) { 401 case PCI_DEVICE_ID_O2_SDS0: 402 case PCI_DEVICE_ID_O2_SEABIRD0: 403 case PCI_DEVICE_ID_O2_SEABIRD1: 404 case PCI_DEVICE_ID_O2_SDS1: 405 case PCI_DEVICE_ID_O2_FUJIN2: 406 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 407 if (reg & 0x1) 408 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 409 410 sdhci_pci_o2_enable_msi(chip, host); 411 412 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 413 ret = pci_read_config_dword(chip->pdev, 414 O2_SD_MISC_SETTING, ®); 415 if (ret) 416 return -EIO; 417 if (reg & (1 << 4)) { 418 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 419 mmc_hostname(host->mmc)); 420 host->flags &= ~SDHCI_SIGNALING_330; 421 host->flags |= SDHCI_SIGNALING_180; 422 host->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 423 host->mmc->caps2 |= MMC_CAP2_NO_SD; 424 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 425 pci_write_config_dword(chip->pdev, 426 O2_SD_DETECT_SETTING, 3); 427 } 428 429 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 430 } 431 432 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 433 434 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 435 break; 436 /* set dll watch dog timer */ 437 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 438 reg |= (1 << 12); 439 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 440 441 break; 442 default: 443 break; 444 } 445 446 return 0; 447 } 448 449 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 450 { 451 int ret; 452 u8 scratch; 453 u32 scratch_32; 454 455 switch (chip->pdev->device) { 456 case PCI_DEVICE_ID_O2_8220: 457 case PCI_DEVICE_ID_O2_8221: 458 case PCI_DEVICE_ID_O2_8320: 459 case PCI_DEVICE_ID_O2_8321: 460 /* This extra setup is required due to broken ADMA. */ 461 ret = pci_read_config_byte(chip->pdev, 462 O2_SD_LOCK_WP, &scratch); 463 if (ret) 464 return ret; 465 scratch &= 0x7f; 466 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 467 468 /* Set Multi 3 to VCC3V# */ 469 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 470 471 /* Disable CLK_REQ# support after media DET */ 472 ret = pci_read_config_byte(chip->pdev, 473 O2_SD_CLKREQ, &scratch); 474 if (ret) 475 return ret; 476 scratch |= 0x20; 477 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 478 479 /* Choose capabilities, enable SDMA. We have to write 0x01 480 * to the capabilities register first to unlock it. 481 */ 482 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 483 if (ret) 484 return ret; 485 scratch |= 0x01; 486 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 487 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 488 489 /* Disable ADMA1/2 */ 490 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 491 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 492 493 /* Disable the infinite transfer mode */ 494 ret = pci_read_config_byte(chip->pdev, 495 O2_SD_INF_MOD, &scratch); 496 if (ret) 497 return ret; 498 scratch |= 0x08; 499 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 500 501 /* Lock WP */ 502 ret = pci_read_config_byte(chip->pdev, 503 O2_SD_LOCK_WP, &scratch); 504 if (ret) 505 return ret; 506 scratch |= 0x80; 507 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 508 break; 509 case PCI_DEVICE_ID_O2_SDS0: 510 case PCI_DEVICE_ID_O2_SDS1: 511 case PCI_DEVICE_ID_O2_FUJIN2: 512 /* UnLock WP */ 513 ret = pci_read_config_byte(chip->pdev, 514 O2_SD_LOCK_WP, &scratch); 515 if (ret) 516 return ret; 517 518 scratch &= 0x7f; 519 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 520 521 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 522 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 523 ret = pci_read_config_dword(chip->pdev, 524 O2_SD_FUNC_REG0, 525 &scratch_32); 526 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 527 528 /* Check Whether subId is 0x11 or 0x12 */ 529 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 530 scratch_32 = 0x25100000; 531 532 o2_pci_set_baseclk(chip, scratch_32); 533 ret = pci_read_config_dword(chip->pdev, 534 O2_SD_FUNC_REG4, 535 &scratch_32); 536 537 /* Enable Base Clk setting change */ 538 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 539 pci_write_config_dword(chip->pdev, 540 O2_SD_FUNC_REG4, 541 scratch_32); 542 543 /* Set Tuning Window to 4 */ 544 pci_write_config_byte(chip->pdev, 545 O2_SD_TUNING_CTRL, 0x44); 546 547 break; 548 } 549 } 550 551 /* Enable 8520 led function */ 552 o2_pci_led_enable(chip); 553 554 /* Set timeout CLK */ 555 ret = pci_read_config_dword(chip->pdev, 556 O2_SD_CLK_SETTING, &scratch_32); 557 if (ret) 558 return ret; 559 560 scratch_32 &= ~(0xFF00); 561 scratch_32 |= 0x07E0C800; 562 pci_write_config_dword(chip->pdev, 563 O2_SD_CLK_SETTING, scratch_32); 564 565 ret = pci_read_config_dword(chip->pdev, 566 O2_SD_CLKREQ, &scratch_32); 567 if (ret) 568 return ret; 569 scratch_32 |= 0x3; 570 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 571 572 ret = pci_read_config_dword(chip->pdev, 573 O2_SD_PLL_SETTING, &scratch_32); 574 if (ret) 575 return ret; 576 577 scratch_32 &= ~(0x1F3F070E); 578 scratch_32 |= 0x18270106; 579 pci_write_config_dword(chip->pdev, 580 O2_SD_PLL_SETTING, scratch_32); 581 582 /* Disable UHS1 funciton */ 583 ret = pci_read_config_dword(chip->pdev, 584 O2_SD_CAP_REG2, &scratch_32); 585 if (ret) 586 return ret; 587 scratch_32 &= ~(0xE0); 588 pci_write_config_dword(chip->pdev, 589 O2_SD_CAP_REG2, scratch_32); 590 591 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 592 sdhci_pci_o2_fujin2_pci_init(chip); 593 594 /* Lock WP */ 595 ret = pci_read_config_byte(chip->pdev, 596 O2_SD_LOCK_WP, &scratch); 597 if (ret) 598 return ret; 599 scratch |= 0x80; 600 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 601 break; 602 case PCI_DEVICE_ID_O2_SEABIRD0: 603 case PCI_DEVICE_ID_O2_SEABIRD1: 604 /* UnLock WP */ 605 ret = pci_read_config_byte(chip->pdev, 606 O2_SD_LOCK_WP, &scratch); 607 if (ret) 608 return ret; 609 610 scratch &= 0x7f; 611 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 612 613 ret = pci_read_config_dword(chip->pdev, 614 O2_SD_PLL_SETTING, &scratch_32); 615 616 if ((scratch_32 & 0xff000000) == 0x01000000) { 617 scratch_32 &= 0x0000FFFF; 618 scratch_32 |= 0x1F340000; 619 620 pci_write_config_dword(chip->pdev, 621 O2_SD_PLL_SETTING, scratch_32); 622 } else { 623 scratch_32 &= 0x0000FFFF; 624 scratch_32 |= 0x25100000; 625 626 pci_write_config_dword(chip->pdev, 627 O2_SD_PLL_SETTING, scratch_32); 628 629 ret = pci_read_config_dword(chip->pdev, 630 O2_SD_FUNC_REG4, 631 &scratch_32); 632 scratch_32 |= (1 << 22); 633 pci_write_config_dword(chip->pdev, 634 O2_SD_FUNC_REG4, scratch_32); 635 } 636 637 /* Set Tuning Windows to 5 */ 638 pci_write_config_byte(chip->pdev, 639 O2_SD_TUNING_CTRL, 0x55); 640 /* Lock WP */ 641 ret = pci_read_config_byte(chip->pdev, 642 O2_SD_LOCK_WP, &scratch); 643 if (ret) 644 return ret; 645 scratch |= 0x80; 646 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 647 break; 648 } 649 650 return 0; 651 } 652 653 #ifdef CONFIG_PM_SLEEP 654 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 655 { 656 sdhci_pci_o2_probe(chip); 657 return sdhci_pci_resume_host(chip); 658 } 659 #endif 660 661 static const struct sdhci_ops sdhci_pci_o2_ops = { 662 .set_clock = sdhci_pci_o2_set_clock, 663 .enable_dma = sdhci_pci_enable_dma, 664 .set_bus_width = sdhci_set_bus_width, 665 .reset = sdhci_reset, 666 .set_uhs_signaling = sdhci_set_uhs_signaling, 667 }; 668 669 const struct sdhci_pci_fixes sdhci_o2 = { 670 .probe = sdhci_pci_o2_probe, 671 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 672 .probe_slot = sdhci_pci_o2_probe_slot, 673 #ifdef CONFIG_PM_SLEEP 674 .resume = sdhci_pci_o2_resume, 675 #endif 676 .ops = &sdhci_pci_o2_ops, 677 }; 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