1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 BayHub Technology Ltd. 4 * 5 * Authors: Peter Guo <peter.guo@bayhubtech.com> 6 * Adam Lee <adam.lee@canonical.com> 7 * Ernest Zhang <ernest.zhang@bayhubtech.com> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/delay.h> 14 15 #include "sdhci.h" 16 #include "sdhci-pci.h" 17 18 /* 19 * O2Micro device registers 20 */ 21 22 #define O2_SD_MISC_REG5 0x64 23 #define O2_SD_LD0_CTRL 0x68 24 #define O2_SD_DEV_CTRL 0x88 25 #define O2_SD_LOCK_WP 0xD3 26 #define O2_SD_TEST_REG 0xD4 27 #define O2_SD_FUNC_REG0 0xDC 28 #define O2_SD_MULTI_VCC3V 0xEE 29 #define O2_SD_CLKREQ 0xEC 30 #define O2_SD_CAPS 0xE0 31 #define O2_SD_ADMA1 0xE2 32 #define O2_SD_ADMA2 0xE7 33 #define O2_SD_INF_MOD 0xF1 34 #define O2_SD_MISC_CTRL4 0xFC 35 #define O2_SD_TUNING_CTRL 0x300 36 #define O2_SD_PLL_SETTING 0x304 37 #define O2_SD_MISC_SETTING 0x308 38 #define O2_SD_CLK_SETTING 0x328 39 #define O2_SD_CAP_REG2 0x330 40 #define O2_SD_CAP_REG0 0x334 41 #define O2_SD_UHS1_CAP_SETTING 0x33C 42 #define O2_SD_DELAY_CTRL 0x350 43 #define O2_SD_UHS2_L1_CTRL 0x35C 44 #define O2_SD_FUNC_REG3 0x3E0 45 #define O2_SD_FUNC_REG4 0x3E4 46 #define O2_SD_LED_ENABLE BIT(6) 47 #define O2_SD_FREG0_LEDOFF BIT(13) 48 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 49 50 #define O2_SD_VENDOR_SETTING 0x110 51 #define O2_SD_VENDOR_SETTING2 0x1C8 52 #define O2_SD_HW_TUNING_DISABLE BIT(4) 53 54 #define O2_PLL_WDT_CONTROL1 0x1CC 55 #define O2_PLL_FORCE_ACTIVE BIT(18) 56 #define O2_PLL_LOCK_STATUS BIT(14) 57 #define O2_PLL_SOFT_RESET BIT(12) 58 59 #define O2_SD_DETECT_SETTING 0x324 60 61 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 62 { 63 u16 reg; 64 65 /* enable hardware tuning */ 66 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 67 reg &= ~O2_SD_HW_TUNING_DISABLE; 68 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 69 } 70 71 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 72 { 73 int i; 74 75 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200); 76 77 for (i = 0; i < 150; i++) { 78 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 79 80 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 81 if (ctrl & SDHCI_CTRL_TUNED_CLK) { 82 host->tuning_done = true; 83 return; 84 } 85 pr_warn("%s: HW tuning failed !\n", 86 mmc_hostname(host->mmc)); 87 break; 88 } 89 90 mdelay(1); 91 } 92 93 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 94 mmc_hostname(host->mmc)); 95 sdhci_reset_tuning(host); 96 } 97 98 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 99 { 100 struct sdhci_host *host = mmc_priv(mmc); 101 int current_bus_width = 0; 102 103 /* 104 * This handler only implements the eMMC tuning that is specific to 105 * this controller. Fall back to the standard method for other TIMING. 106 */ 107 if (host->timing != MMC_TIMING_MMC_HS200) 108 return sdhci_execute_tuning(mmc, opcode); 109 110 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) 111 return -EINVAL; 112 113 /* 114 * o2 sdhci host didn't support 8bit emmc tuning 115 */ 116 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 117 current_bus_width = mmc->ios.bus_width; 118 mmc->ios.bus_width = MMC_BUS_WIDTH_4; 119 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 120 } 121 122 sdhci_o2_set_tuning_mode(host); 123 124 sdhci_start_tuning(host); 125 126 __sdhci_o2_execute_tuning(host, opcode); 127 128 sdhci_end_tuning(host); 129 130 if (current_bus_width == MMC_BUS_WIDTH_8) { 131 mmc->ios.bus_width = MMC_BUS_WIDTH_8; 132 sdhci_set_bus_width(host, current_bus_width); 133 } 134 135 host->flags &= ~SDHCI_HS400_TUNING; 136 return 0; 137 } 138 139 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 140 { 141 u32 scratch_32; 142 pci_read_config_dword(chip->pdev, 143 O2_SD_PLL_SETTING, &scratch_32); 144 145 scratch_32 &= 0x0000FFFF; 146 scratch_32 |= value; 147 148 pci_write_config_dword(chip->pdev, 149 O2_SD_PLL_SETTING, scratch_32); 150 } 151 152 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 153 { 154 int ret; 155 u32 scratch_32; 156 157 /* Set led of SD host function enable */ 158 ret = pci_read_config_dword(chip->pdev, 159 O2_SD_FUNC_REG0, &scratch_32); 160 if (ret) 161 return; 162 163 scratch_32 &= ~O2_SD_FREG0_LEDOFF; 164 pci_write_config_dword(chip->pdev, 165 O2_SD_FUNC_REG0, scratch_32); 166 167 ret = pci_read_config_dword(chip->pdev, 168 O2_SD_TEST_REG, &scratch_32); 169 if (ret) 170 return; 171 172 scratch_32 |= O2_SD_LED_ENABLE; 173 pci_write_config_dword(chip->pdev, 174 O2_SD_TEST_REG, scratch_32); 175 176 } 177 178 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 179 { 180 u32 scratch_32; 181 int ret; 182 /* Improve write performance for SD3.0 */ 183 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 184 if (ret) 185 return; 186 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 187 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 188 189 /* Enable Link abnormal reset generating Reset */ 190 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 191 if (ret) 192 return; 193 scratch_32 &= ~((1 << 19) | (1 << 11)); 194 scratch_32 |= (1 << 10); 195 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 196 197 /* set card power over current protection */ 198 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 199 if (ret) 200 return; 201 scratch_32 |= (1 << 4); 202 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 203 204 /* adjust the output delay for SD mode */ 205 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 206 207 /* Set the output voltage setting of Aux 1.2v LDO */ 208 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 209 if (ret) 210 return; 211 scratch_32 &= ~(3 << 12); 212 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 213 214 /* Set Max power supply capability of SD host */ 215 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 216 if (ret) 217 return; 218 scratch_32 &= ~(0x01FE); 219 scratch_32 |= 0x00CC; 220 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 221 /* Set DLL Tuning Window */ 222 ret = pci_read_config_dword(chip->pdev, 223 O2_SD_TUNING_CTRL, &scratch_32); 224 if (ret) 225 return; 226 scratch_32 &= ~(0x000000FF); 227 scratch_32 |= 0x00000066; 228 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 229 230 /* Set UHS2 T_EIDLE */ 231 ret = pci_read_config_dword(chip->pdev, 232 O2_SD_UHS2_L1_CTRL, &scratch_32); 233 if (ret) 234 return; 235 scratch_32 &= ~(0x000000FC); 236 scratch_32 |= 0x00000084; 237 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 238 239 /* Set UHS2 Termination */ 240 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 241 if (ret) 242 return; 243 scratch_32 &= ~((1 << 21) | (1 << 30)); 244 245 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 246 247 /* Set L1 Entrance Timer */ 248 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 249 if (ret) 250 return; 251 scratch_32 &= ~(0xf0000000); 252 scratch_32 |= 0x30000000; 253 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 254 255 ret = pci_read_config_dword(chip->pdev, 256 O2_SD_MISC_CTRL4, &scratch_32); 257 if (ret) 258 return; 259 scratch_32 &= ~(0x000f0000); 260 scratch_32 |= 0x00080000; 261 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 262 } 263 264 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 265 struct sdhci_host *host) 266 { 267 int ret; 268 269 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 270 if (!ret) { 271 pr_info("%s: unsupport msi, use INTx irq\n", 272 mmc_hostname(host->mmc)); 273 return; 274 } 275 276 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 277 PCI_IRQ_MSI | PCI_IRQ_MSIX); 278 if (ret < 0) { 279 pr_err("%s: enable PCI MSI failed, err=%d\n", 280 mmc_hostname(host->mmc), ret); 281 return; 282 } 283 284 host->irq = pci_irq_vector(chip->pdev, 0); 285 } 286 287 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 288 { 289 ktime_t timeout; 290 u32 scratch32; 291 292 /* Wait max 50 ms */ 293 timeout = ktime_add_ms(ktime_get(), 50); 294 while (1) { 295 bool timedout = ktime_after(ktime_get(), timeout); 296 297 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 298 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 299 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 300 break; 301 302 if (timedout) { 303 pr_err("%s: Card Detect debounce never finished.\n", 304 mmc_hostname(host->mmc)); 305 sdhci_dumpregs(host); 306 return; 307 } 308 udelay(10); 309 } 310 } 311 312 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 313 { 314 ktime_t timeout; 315 u16 scratch; 316 u32 scratch32; 317 318 /* PLL software reset */ 319 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 320 scratch32 |= O2_PLL_SOFT_RESET; 321 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 322 udelay(1); 323 scratch32 &= ~(O2_PLL_SOFT_RESET); 324 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 325 326 /* PLL force active */ 327 scratch32 |= O2_PLL_FORCE_ACTIVE; 328 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 329 330 /* Wait max 20 ms */ 331 timeout = ktime_add_ms(ktime_get(), 20); 332 while (1) { 333 bool timedout = ktime_after(ktime_get(), timeout); 334 335 scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1); 336 if (scratch & O2_PLL_LOCK_STATUS) 337 break; 338 if (timedout) { 339 pr_err("%s: Internal clock never stabilised.\n", 340 mmc_hostname(host->mmc)); 341 sdhci_dumpregs(host); 342 goto out; 343 } 344 udelay(10); 345 } 346 347 /* Wait for card detect finish */ 348 udelay(1); 349 sdhci_o2_wait_card_detect_stable(host); 350 351 out: 352 /* Cancel PLL force active */ 353 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 354 scratch32 &= ~O2_PLL_FORCE_ACTIVE; 355 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 356 } 357 358 static int sdhci_o2_get_cd(struct mmc_host *mmc) 359 { 360 struct sdhci_host *host = mmc_priv(mmc); 361 362 sdhci_o2_enable_internal_clock(host); 363 364 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 365 } 366 367 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 368 { 369 /* Enable internal clock */ 370 clk |= SDHCI_CLOCK_INT_EN; 371 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 372 373 if (sdhci_o2_get_cd(host->mmc)) { 374 clk |= SDHCI_CLOCK_CARD_EN; 375 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 376 } 377 } 378 379 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 380 { 381 u16 clk; 382 383 host->mmc->actual_clock = 0; 384 385 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 386 387 if (clock == 0) 388 return; 389 390 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 391 sdhci_o2_enable_clk(host, clk); 392 } 393 394 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 395 { 396 struct sdhci_pci_chip *chip; 397 struct sdhci_host *host; 398 u32 reg; 399 int ret; 400 401 chip = slot->chip; 402 host = slot->host; 403 switch (chip->pdev->device) { 404 case PCI_DEVICE_ID_O2_SDS0: 405 case PCI_DEVICE_ID_O2_SEABIRD0: 406 case PCI_DEVICE_ID_O2_SEABIRD1: 407 case PCI_DEVICE_ID_O2_SDS1: 408 case PCI_DEVICE_ID_O2_FUJIN2: 409 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 410 if (reg & 0x1) 411 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 412 413 sdhci_pci_o2_enable_msi(chip, host); 414 415 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 416 ret = pci_read_config_dword(chip->pdev, 417 O2_SD_MISC_SETTING, ®); 418 if (ret) 419 return -EIO; 420 if (reg & (1 << 4)) { 421 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 422 mmc_hostname(host->mmc)); 423 host->flags &= ~SDHCI_SIGNALING_330; 424 host->flags |= SDHCI_SIGNALING_180; 425 host->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 426 host->mmc->caps2 |= MMC_CAP2_NO_SD; 427 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 428 pci_write_config_dword(chip->pdev, 429 O2_SD_DETECT_SETTING, 3); 430 } 431 432 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 433 } 434 435 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 436 437 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 438 break; 439 /* set dll watch dog timer */ 440 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 441 reg |= (1 << 12); 442 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 443 444 break; 445 default: 446 break; 447 } 448 449 return 0; 450 } 451 452 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 453 { 454 int ret; 455 u8 scratch; 456 u32 scratch_32; 457 458 switch (chip->pdev->device) { 459 case PCI_DEVICE_ID_O2_8220: 460 case PCI_DEVICE_ID_O2_8221: 461 case PCI_DEVICE_ID_O2_8320: 462 case PCI_DEVICE_ID_O2_8321: 463 /* This extra setup is required due to broken ADMA. */ 464 ret = pci_read_config_byte(chip->pdev, 465 O2_SD_LOCK_WP, &scratch); 466 if (ret) 467 return ret; 468 scratch &= 0x7f; 469 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 470 471 /* Set Multi 3 to VCC3V# */ 472 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 473 474 /* Disable CLK_REQ# support after media DET */ 475 ret = pci_read_config_byte(chip->pdev, 476 O2_SD_CLKREQ, &scratch); 477 if (ret) 478 return ret; 479 scratch |= 0x20; 480 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 481 482 /* Choose capabilities, enable SDMA. We have to write 0x01 483 * to the capabilities register first to unlock it. 484 */ 485 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 486 if (ret) 487 return ret; 488 scratch |= 0x01; 489 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 490 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 491 492 /* Disable ADMA1/2 */ 493 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 494 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 495 496 /* Disable the infinite transfer mode */ 497 ret = pci_read_config_byte(chip->pdev, 498 O2_SD_INF_MOD, &scratch); 499 if (ret) 500 return ret; 501 scratch |= 0x08; 502 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 503 504 /* Lock WP */ 505 ret = pci_read_config_byte(chip->pdev, 506 O2_SD_LOCK_WP, &scratch); 507 if (ret) 508 return ret; 509 scratch |= 0x80; 510 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 511 break; 512 case PCI_DEVICE_ID_O2_SDS0: 513 case PCI_DEVICE_ID_O2_SDS1: 514 case PCI_DEVICE_ID_O2_FUJIN2: 515 /* UnLock WP */ 516 ret = pci_read_config_byte(chip->pdev, 517 O2_SD_LOCK_WP, &scratch); 518 if (ret) 519 return ret; 520 521 scratch &= 0x7f; 522 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 523 524 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 525 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 526 ret = pci_read_config_dword(chip->pdev, 527 O2_SD_FUNC_REG0, 528 &scratch_32); 529 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 530 531 /* Check Whether subId is 0x11 or 0x12 */ 532 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 533 scratch_32 = 0x25100000; 534 535 o2_pci_set_baseclk(chip, scratch_32); 536 ret = pci_read_config_dword(chip->pdev, 537 O2_SD_FUNC_REG4, 538 &scratch_32); 539 540 /* Enable Base Clk setting change */ 541 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 542 pci_write_config_dword(chip->pdev, 543 O2_SD_FUNC_REG4, 544 scratch_32); 545 546 /* Set Tuning Window to 4 */ 547 pci_write_config_byte(chip->pdev, 548 O2_SD_TUNING_CTRL, 0x44); 549 550 break; 551 } 552 } 553 554 /* Enable 8520 led function */ 555 o2_pci_led_enable(chip); 556 557 /* Set timeout CLK */ 558 ret = pci_read_config_dword(chip->pdev, 559 O2_SD_CLK_SETTING, &scratch_32); 560 if (ret) 561 return ret; 562 563 scratch_32 &= ~(0xFF00); 564 scratch_32 |= 0x07E0C800; 565 pci_write_config_dword(chip->pdev, 566 O2_SD_CLK_SETTING, scratch_32); 567 568 ret = pci_read_config_dword(chip->pdev, 569 O2_SD_CLKREQ, &scratch_32); 570 if (ret) 571 return ret; 572 scratch_32 |= 0x3; 573 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 574 575 ret = pci_read_config_dword(chip->pdev, 576 O2_SD_PLL_SETTING, &scratch_32); 577 if (ret) 578 return ret; 579 580 scratch_32 &= ~(0x1F3F070E); 581 scratch_32 |= 0x18270106; 582 pci_write_config_dword(chip->pdev, 583 O2_SD_PLL_SETTING, scratch_32); 584 585 /* Disable UHS1 funciton */ 586 ret = pci_read_config_dword(chip->pdev, 587 O2_SD_CAP_REG2, &scratch_32); 588 if (ret) 589 return ret; 590 scratch_32 &= ~(0xE0); 591 pci_write_config_dword(chip->pdev, 592 O2_SD_CAP_REG2, scratch_32); 593 594 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 595 sdhci_pci_o2_fujin2_pci_init(chip); 596 597 /* Lock WP */ 598 ret = pci_read_config_byte(chip->pdev, 599 O2_SD_LOCK_WP, &scratch); 600 if (ret) 601 return ret; 602 scratch |= 0x80; 603 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 604 break; 605 case PCI_DEVICE_ID_O2_SEABIRD0: 606 case PCI_DEVICE_ID_O2_SEABIRD1: 607 /* UnLock WP */ 608 ret = pci_read_config_byte(chip->pdev, 609 O2_SD_LOCK_WP, &scratch); 610 if (ret) 611 return ret; 612 613 scratch &= 0x7f; 614 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 615 616 ret = pci_read_config_dword(chip->pdev, 617 O2_SD_PLL_SETTING, &scratch_32); 618 619 if ((scratch_32 & 0xff000000) == 0x01000000) { 620 scratch_32 &= 0x0000FFFF; 621 scratch_32 |= 0x1F340000; 622 623 pci_write_config_dword(chip->pdev, 624 O2_SD_PLL_SETTING, scratch_32); 625 } else { 626 scratch_32 &= 0x0000FFFF; 627 scratch_32 |= 0x25100000; 628 629 pci_write_config_dword(chip->pdev, 630 O2_SD_PLL_SETTING, scratch_32); 631 632 ret = pci_read_config_dword(chip->pdev, 633 O2_SD_FUNC_REG4, 634 &scratch_32); 635 scratch_32 |= (1 << 22); 636 pci_write_config_dword(chip->pdev, 637 O2_SD_FUNC_REG4, scratch_32); 638 } 639 640 /* Set Tuning Windows to 5 */ 641 pci_write_config_byte(chip->pdev, 642 O2_SD_TUNING_CTRL, 0x55); 643 /* Lock WP */ 644 ret = pci_read_config_byte(chip->pdev, 645 O2_SD_LOCK_WP, &scratch); 646 if (ret) 647 return ret; 648 scratch |= 0x80; 649 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 650 break; 651 } 652 653 return 0; 654 } 655 656 #ifdef CONFIG_PM_SLEEP 657 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 658 { 659 sdhci_pci_o2_probe(chip); 660 return sdhci_pci_resume_host(chip); 661 } 662 #endif 663 664 static const struct sdhci_ops sdhci_pci_o2_ops = { 665 .set_clock = sdhci_pci_o2_set_clock, 666 .enable_dma = sdhci_pci_enable_dma, 667 .set_bus_width = sdhci_set_bus_width, 668 .reset = sdhci_reset, 669 .set_uhs_signaling = sdhci_set_uhs_signaling, 670 }; 671 672 const struct sdhci_pci_fixes sdhci_o2 = { 673 .probe = sdhci_pci_o2_probe, 674 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 675 .probe_slot = sdhci_pci_o2_probe_slot, 676 #ifdef CONFIG_PM_SLEEP 677 .resume = sdhci_pci_o2_resume, 678 #endif 679 .ops = &sdhci_pci_o2_ops, 680 }; 681