1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 BayHub Technology Ltd. 4 * 5 * Authors: Peter Guo <peter.guo@bayhubtech.com> 6 * Adam Lee <adam.lee@canonical.com> 7 * Ernest Zhang <ernest.zhang@bayhubtech.com> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/delay.h> 14 #include <linux/iopoll.h> 15 #include <linux/bitfield.h> 16 17 #include "sdhci.h" 18 #include "sdhci-pci.h" 19 20 /* 21 * O2Micro device registers 22 */ 23 24 #define O2_SD_MISC_REG5 0x64 25 #define O2_SD_LD0_CTRL 0x68 26 #define O2_SD_DEV_CTRL 0x88 27 #define O2_SD_LOCK_WP 0xD3 28 #define O2_SD_TEST_REG 0xD4 29 #define O2_SD_FUNC_REG0 0xDC 30 #define O2_SD_MULTI_VCC3V 0xEE 31 #define O2_SD_CLKREQ 0xEC 32 #define O2_SD_CAPS 0xE0 33 #define O2_SD_ADMA1 0xE2 34 #define O2_SD_ADMA2 0xE7 35 #define O2_SD_INF_MOD 0xF1 36 #define O2_SD_MISC_CTRL4 0xFC 37 #define O2_SD_MISC_CTRL 0x1C0 38 #define O2_SD_PWR_FORCE_L0 0x0002 39 #define O2_SD_TUNING_CTRL 0x300 40 #define O2_SD_PLL_SETTING 0x304 41 #define O2_SD_MISC_SETTING 0x308 42 #define O2_SD_CLK_SETTING 0x328 43 #define O2_SD_CAP_REG2 0x330 44 #define O2_SD_CAP_REG0 0x334 45 #define O2_SD_UHS1_CAP_SETTING 0x33C 46 #define O2_SD_DELAY_CTRL 0x350 47 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 48 #define O2_SD_UHS2_L1_CTRL 0x35C 49 #define O2_SD_FUNC_REG3 0x3E0 50 #define O2_SD_FUNC_REG4 0x3E4 51 #define O2_SD_LED_ENABLE BIT(6) 52 #define O2_SD_FREG0_LEDOFF BIT(13) 53 #define O2_SD_SEL_DLL BIT(16) 54 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 55 #define O2_SD_PHASE_MASK GENMASK(23, 20) 56 #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) 57 58 #define O2_SD_VENDOR_SETTING 0x110 59 #define O2_SD_VENDOR_SETTING2 0x1C8 60 #define O2_SD_HW_TUNING_DISABLE BIT(4) 61 62 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 63 #define O2_PLL_FORCE_ACTIVE BIT(18) 64 #define O2_PLL_LOCK_STATUS BIT(14) 65 #define O2_PLL_SOFT_RESET BIT(12) 66 #define O2_DLL_LOCK_STATUS BIT(11) 67 68 #define O2_SD_DETECT_SETTING 0x324 69 70 static const u32 dmdn_table[] = {0x2B1C0000, 71 0x2C1A0000, 0x371B0000, 0x35100000}; 72 #define DMDN_SZ ARRAY_SIZE(dmdn_table) 73 74 struct o2_host { 75 u8 dll_adjust_count; 76 }; 77 78 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 79 { 80 ktime_t timeout; 81 u32 scratch32; 82 83 /* Wait max 50 ms */ 84 timeout = ktime_add_ms(ktime_get(), 50); 85 while (1) { 86 bool timedout = ktime_after(ktime_get(), timeout); 87 88 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 89 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 90 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 91 break; 92 93 if (timedout) { 94 pr_err("%s: Card Detect debounce never finished.\n", 95 mmc_hostname(host->mmc)); 96 sdhci_dumpregs(host); 97 return; 98 } 99 udelay(10); 100 } 101 } 102 103 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 104 { 105 ktime_t timeout; 106 u16 scratch; 107 u32 scratch32; 108 109 /* PLL software reset */ 110 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 111 scratch32 |= O2_PLL_SOFT_RESET; 112 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 113 udelay(1); 114 scratch32 &= ~(O2_PLL_SOFT_RESET); 115 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 116 117 /* PLL force active */ 118 scratch32 |= O2_PLL_FORCE_ACTIVE; 119 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 120 121 /* Wait max 20 ms */ 122 timeout = ktime_add_ms(ktime_get(), 20); 123 while (1) { 124 bool timedout = ktime_after(ktime_get(), timeout); 125 126 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 127 if (scratch & O2_PLL_LOCK_STATUS) 128 break; 129 if (timedout) { 130 pr_err("%s: Internal clock never stabilised.\n", 131 mmc_hostname(host->mmc)); 132 sdhci_dumpregs(host); 133 goto out; 134 } 135 udelay(10); 136 } 137 138 /* Wait for card detect finish */ 139 udelay(1); 140 sdhci_o2_wait_card_detect_stable(host); 141 142 out: 143 /* Cancel PLL force active */ 144 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 145 scratch32 &= ~O2_PLL_FORCE_ACTIVE; 146 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 147 } 148 149 static int sdhci_o2_get_cd(struct mmc_host *mmc) 150 { 151 struct sdhci_host *host = mmc_priv(mmc); 152 153 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 154 sdhci_o2_enable_internal_clock(host); 155 156 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 157 } 158 159 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 160 { 161 u32 scratch_32; 162 163 pci_read_config_dword(chip->pdev, 164 O2_SD_PLL_SETTING, &scratch_32); 165 166 scratch_32 &= 0x0000FFFF; 167 scratch_32 |= value; 168 169 pci_write_config_dword(chip->pdev, 170 O2_SD_PLL_SETTING, scratch_32); 171 } 172 173 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 174 { 175 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 176 } 177 178 /* 179 * This function is used to detect dll lock status. 180 * Since the dll lock status bit will toggle randomly 181 * with very short interval which needs to be polled 182 * as fast as possible. Set sleep_us as 1 microsecond. 183 */ 184 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 185 { 186 u32 scratch32 = 0; 187 188 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 189 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 190 } 191 192 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 193 { 194 u16 reg; 195 196 /* enable hardware tuning */ 197 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 198 reg &= ~O2_SD_HW_TUNING_DISABLE; 199 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 200 } 201 202 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 203 { 204 int i; 205 206 sdhci_send_tuning(host, opcode); 207 208 for (i = 0; i < 150; i++) { 209 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 210 211 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 212 if (ctrl & SDHCI_CTRL_TUNED_CLK) { 213 host->tuning_done = true; 214 return; 215 } 216 pr_warn("%s: HW tuning failed !\n", 217 mmc_hostname(host->mmc)); 218 break; 219 } 220 221 mdelay(1); 222 } 223 224 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 225 mmc_hostname(host->mmc)); 226 sdhci_reset_tuning(host); 227 } 228 229 /* 230 * This function is used to fix o2 dll shift issue. 231 * It isn't necessary to detect card present before recovery. 232 * Firstly, it is used by bht emmc card, which is embedded. 233 * Second, before call recovery card present will be detected 234 * outside of the execute tuning function. 235 */ 236 static int sdhci_o2_dll_recovery(struct sdhci_host *host) 237 { 238 int ret = 0; 239 u8 scratch_8 = 0; 240 u32 scratch_32 = 0; 241 struct sdhci_pci_slot *slot = sdhci_priv(host); 242 struct sdhci_pci_chip *chip = slot->chip; 243 struct o2_host *o2_host = sdhci_pci_priv(slot); 244 245 /* UnLock WP */ 246 pci_read_config_byte(chip->pdev, 247 O2_SD_LOCK_WP, &scratch_8); 248 scratch_8 &= 0x7f; 249 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 250 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 251 /* Disable clock */ 252 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 253 254 /* PLL software reset */ 255 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 256 scratch_32 |= O2_PLL_SOFT_RESET; 257 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 258 259 pci_read_config_dword(chip->pdev, 260 O2_SD_FUNC_REG4, 261 &scratch_32); 262 /* Enable Base Clk setting change */ 263 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 264 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 265 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 266 267 /* Enable internal clock */ 268 scratch_8 = SDHCI_CLOCK_INT_EN; 269 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 270 271 if (sdhci_o2_get_cd(host->mmc)) { 272 /* 273 * need wait at least 5ms for dll status stable, 274 * after enable internal clock 275 */ 276 usleep_range(5000, 6000); 277 if (sdhci_o2_wait_dll_detect_lock(host)) { 278 scratch_8 |= SDHCI_CLOCK_CARD_EN; 279 sdhci_writeb(host, scratch_8, 280 SDHCI_CLOCK_CONTROL); 281 ret = 1; 282 } else { 283 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 284 mmc_hostname(host->mmc), 285 o2_host->dll_adjust_count); 286 } 287 } else { 288 pr_err("%s: card present detect failed.\n", 289 mmc_hostname(host->mmc)); 290 break; 291 } 292 293 o2_host->dll_adjust_count++; 294 } 295 if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 296 pr_err("%s: DLL adjust over max times\n", 297 mmc_hostname(host->mmc)); 298 /* Lock WP */ 299 pci_read_config_byte(chip->pdev, 300 O2_SD_LOCK_WP, &scratch_8); 301 scratch_8 |= 0x80; 302 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 303 return ret; 304 } 305 306 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 307 { 308 struct sdhci_host *host = mmc_priv(mmc); 309 struct sdhci_pci_slot *slot = sdhci_priv(host); 310 struct sdhci_pci_chip *chip = slot->chip; 311 int current_bus_width = 0; 312 u32 scratch32 = 0; 313 u16 scratch = 0; 314 u8 scratch_8 = 0; 315 u32 reg_val; 316 317 /* 318 * This handler only implements the eMMC tuning that is specific to 319 * this controller. Fall back to the standard method for other TIMING. 320 */ 321 if ((host->timing != MMC_TIMING_MMC_HS200) && 322 (host->timing != MMC_TIMING_UHS_SDR104)) 323 return sdhci_execute_tuning(mmc, opcode); 324 325 if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && 326 (opcode != MMC_SEND_TUNING_BLOCK))) 327 return -EINVAL; 328 329 /* Force power mode enter L0 */ 330 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 331 scratch |= O2_SD_PWR_FORCE_L0; 332 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 333 334 /* Stop clk */ 335 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 336 reg_val &= ~SDHCI_CLOCK_CARD_EN; 337 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 338 339 /* UnLock WP */ 340 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 341 scratch_8 &= 0x7f; 342 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 343 344 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ 345 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); 346 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 347 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); 348 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); 349 350 /* Lock WP */ 351 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 352 scratch_8 |= 0x80; 353 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 354 355 /* Start clk */ 356 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 357 reg_val |= SDHCI_CLOCK_CARD_EN; 358 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 359 360 /* wait DLL lock, timeout value 5ms */ 361 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 362 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) 363 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", 364 mmc_hostname(host->mmc)); 365 /* 366 * Judge the tuning reason, whether caused by dll shift 367 * If cause by dll shift, should call sdhci_o2_dll_recovery 368 */ 369 if (!sdhci_o2_wait_dll_detect_lock(host)) 370 if (!sdhci_o2_dll_recovery(host)) { 371 pr_err("%s: o2 dll recovery failed\n", 372 mmc_hostname(host->mmc)); 373 return -EINVAL; 374 } 375 /* 376 * o2 sdhci host didn't support 8bit emmc tuning 377 */ 378 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 379 current_bus_width = mmc->ios.bus_width; 380 mmc->ios.bus_width = MMC_BUS_WIDTH_4; 381 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 382 } 383 384 sdhci_o2_set_tuning_mode(host); 385 386 sdhci_start_tuning(host); 387 388 __sdhci_o2_execute_tuning(host, opcode); 389 390 sdhci_end_tuning(host); 391 392 if (current_bus_width == MMC_BUS_WIDTH_8) { 393 mmc->ios.bus_width = MMC_BUS_WIDTH_8; 394 sdhci_set_bus_width(host, current_bus_width); 395 } 396 397 /* Cancel force power mode enter L0 */ 398 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 399 scratch &= ~(O2_SD_PWR_FORCE_L0); 400 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 401 402 sdhci_reset(host, SDHCI_RESET_CMD); 403 sdhci_reset(host, SDHCI_RESET_DATA); 404 405 host->flags &= ~SDHCI_HS400_TUNING; 406 return 0; 407 } 408 409 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 410 { 411 int ret; 412 u32 scratch_32; 413 414 /* Set led of SD host function enable */ 415 ret = pci_read_config_dword(chip->pdev, 416 O2_SD_FUNC_REG0, &scratch_32); 417 if (ret) 418 return; 419 420 scratch_32 &= ~O2_SD_FREG0_LEDOFF; 421 pci_write_config_dword(chip->pdev, 422 O2_SD_FUNC_REG0, scratch_32); 423 424 ret = pci_read_config_dword(chip->pdev, 425 O2_SD_TEST_REG, &scratch_32); 426 if (ret) 427 return; 428 429 scratch_32 |= O2_SD_LED_ENABLE; 430 pci_write_config_dword(chip->pdev, 431 O2_SD_TEST_REG, scratch_32); 432 } 433 434 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 435 { 436 u32 scratch_32; 437 int ret; 438 /* Improve write performance for SD3.0 */ 439 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 440 if (ret) 441 return; 442 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 443 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 444 445 /* Enable Link abnormal reset generating Reset */ 446 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 447 if (ret) 448 return; 449 scratch_32 &= ~((1 << 19) | (1 << 11)); 450 scratch_32 |= (1 << 10); 451 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 452 453 /* set card power over current protection */ 454 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 455 if (ret) 456 return; 457 scratch_32 |= (1 << 4); 458 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 459 460 /* adjust the output delay for SD mode */ 461 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 462 463 /* Set the output voltage setting of Aux 1.2v LDO */ 464 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 465 if (ret) 466 return; 467 scratch_32 &= ~(3 << 12); 468 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 469 470 /* Set Max power supply capability of SD host */ 471 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 472 if (ret) 473 return; 474 scratch_32 &= ~(0x01FE); 475 scratch_32 |= 0x00CC; 476 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 477 /* Set DLL Tuning Window */ 478 ret = pci_read_config_dword(chip->pdev, 479 O2_SD_TUNING_CTRL, &scratch_32); 480 if (ret) 481 return; 482 scratch_32 &= ~(0x000000FF); 483 scratch_32 |= 0x00000066; 484 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 485 486 /* Set UHS2 T_EIDLE */ 487 ret = pci_read_config_dword(chip->pdev, 488 O2_SD_UHS2_L1_CTRL, &scratch_32); 489 if (ret) 490 return; 491 scratch_32 &= ~(0x000000FC); 492 scratch_32 |= 0x00000084; 493 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 494 495 /* Set UHS2 Termination */ 496 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 497 if (ret) 498 return; 499 scratch_32 &= ~((1 << 21) | (1 << 30)); 500 501 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 502 503 /* Set L1 Entrance Timer */ 504 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 505 if (ret) 506 return; 507 scratch_32 &= ~(0xf0000000); 508 scratch_32 |= 0x30000000; 509 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 510 511 ret = pci_read_config_dword(chip->pdev, 512 O2_SD_MISC_CTRL4, &scratch_32); 513 if (ret) 514 return; 515 scratch_32 &= ~(0x000f0000); 516 scratch_32 |= 0x00080000; 517 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 518 } 519 520 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 521 struct sdhci_host *host) 522 { 523 int ret; 524 525 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 526 if (!ret) { 527 pr_info("%s: unsupported MSI, use INTx irq\n", 528 mmc_hostname(host->mmc)); 529 return; 530 } 531 532 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 533 PCI_IRQ_MSI | PCI_IRQ_MSIX); 534 if (ret < 0) { 535 pr_err("%s: enable PCI MSI failed, err=%d\n", 536 mmc_hostname(host->mmc), ret); 537 return; 538 } 539 540 host->irq = pci_irq_vector(chip->pdev, 0); 541 } 542 543 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 544 { 545 /* Enable internal clock */ 546 clk |= SDHCI_CLOCK_INT_EN; 547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 548 549 sdhci_o2_enable_internal_clock(host); 550 if (sdhci_o2_get_cd(host->mmc)) { 551 clk |= SDHCI_CLOCK_CARD_EN; 552 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 553 } 554 } 555 556 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 557 { 558 u16 clk; 559 u8 scratch; 560 u32 scratch_32; 561 struct sdhci_pci_slot *slot = sdhci_priv(host); 562 struct sdhci_pci_chip *chip = slot->chip; 563 564 host->mmc->actual_clock = 0; 565 566 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 567 568 if (clock == 0) 569 return; 570 571 /* UnLock WP */ 572 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 573 scratch &= 0x7f; 574 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 575 576 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { 577 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 578 579 if ((scratch_32 & 0xFFFF0000) != 0x2c280000) 580 o2_pci_set_baseclk(chip, 0x2c280000); 581 } else { 582 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 583 584 if ((scratch_32 & 0xFFFF0000) != 0x25100000) 585 o2_pci_set_baseclk(chip, 0x25100000); 586 } 587 588 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); 589 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 590 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); 591 592 /* Lock WP */ 593 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 594 scratch |= 0x80; 595 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 596 597 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 598 sdhci_o2_enable_clk(host, clk); 599 } 600 601 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 602 { 603 struct sdhci_pci_chip *chip; 604 struct sdhci_host *host; 605 struct o2_host *o2_host = sdhci_pci_priv(slot); 606 u32 reg, caps; 607 int ret; 608 609 chip = slot->chip; 610 host = slot->host; 611 612 o2_host->dll_adjust_count = 0; 613 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 614 615 /* 616 * mmc_select_bus_width() will test the bus to determine the actual bus 617 * width. 618 */ 619 if (caps & SDHCI_CAN_DO_8BIT) 620 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 621 622 switch (chip->pdev->device) { 623 case PCI_DEVICE_ID_O2_SDS0: 624 case PCI_DEVICE_ID_O2_SEABIRD0: 625 case PCI_DEVICE_ID_O2_SEABIRD1: 626 case PCI_DEVICE_ID_O2_SDS1: 627 case PCI_DEVICE_ID_O2_FUJIN2: 628 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 629 if (reg & 0x1) 630 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 631 632 sdhci_pci_o2_enable_msi(chip, host); 633 634 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 635 ret = pci_read_config_dword(chip->pdev, 636 O2_SD_MISC_SETTING, ®); 637 if (ret) 638 return -EIO; 639 if (reg & (1 << 4)) { 640 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 641 mmc_hostname(host->mmc)); 642 host->flags &= ~SDHCI_SIGNALING_330; 643 host->flags |= SDHCI_SIGNALING_180; 644 host->mmc->caps2 |= MMC_CAP2_NO_SD; 645 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 646 pci_write_config_dword(chip->pdev, 647 O2_SD_DETECT_SETTING, 3); 648 } 649 650 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 651 } 652 653 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { 654 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 655 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 656 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 657 } 658 659 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 660 661 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 662 break; 663 /* set dll watch dog timer */ 664 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 665 reg |= (1 << 12); 666 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 667 668 break; 669 default: 670 break; 671 } 672 673 return 0; 674 } 675 676 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 677 { 678 int ret; 679 u8 scratch; 680 u32 scratch_32; 681 682 switch (chip->pdev->device) { 683 case PCI_DEVICE_ID_O2_8220: 684 case PCI_DEVICE_ID_O2_8221: 685 case PCI_DEVICE_ID_O2_8320: 686 case PCI_DEVICE_ID_O2_8321: 687 /* This extra setup is required due to broken ADMA. */ 688 ret = pci_read_config_byte(chip->pdev, 689 O2_SD_LOCK_WP, &scratch); 690 if (ret) 691 return ret; 692 scratch &= 0x7f; 693 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 694 695 /* Set Multi 3 to VCC3V# */ 696 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 697 698 /* Disable CLK_REQ# support after media DET */ 699 ret = pci_read_config_byte(chip->pdev, 700 O2_SD_CLKREQ, &scratch); 701 if (ret) 702 return ret; 703 scratch |= 0x20; 704 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 705 706 /* Choose capabilities, enable SDMA. We have to write 0x01 707 * to the capabilities register first to unlock it. 708 */ 709 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 710 if (ret) 711 return ret; 712 scratch |= 0x01; 713 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 714 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 715 716 /* Disable ADMA1/2 */ 717 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 718 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 719 720 /* Disable the infinite transfer mode */ 721 ret = pci_read_config_byte(chip->pdev, 722 O2_SD_INF_MOD, &scratch); 723 if (ret) 724 return ret; 725 scratch |= 0x08; 726 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 727 728 /* Lock WP */ 729 ret = pci_read_config_byte(chip->pdev, 730 O2_SD_LOCK_WP, &scratch); 731 if (ret) 732 return ret; 733 scratch |= 0x80; 734 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 735 break; 736 case PCI_DEVICE_ID_O2_SDS0: 737 case PCI_DEVICE_ID_O2_SDS1: 738 case PCI_DEVICE_ID_O2_FUJIN2: 739 /* UnLock WP */ 740 ret = pci_read_config_byte(chip->pdev, 741 O2_SD_LOCK_WP, &scratch); 742 if (ret) 743 return ret; 744 745 scratch &= 0x7f; 746 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 747 748 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 749 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 750 ret = pci_read_config_dword(chip->pdev, 751 O2_SD_FUNC_REG0, 752 &scratch_32); 753 if (ret) 754 return ret; 755 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 756 757 /* Check Whether subId is 0x11 or 0x12 */ 758 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 759 scratch_32 = 0x25100000; 760 761 o2_pci_set_baseclk(chip, scratch_32); 762 ret = pci_read_config_dword(chip->pdev, 763 O2_SD_FUNC_REG4, 764 &scratch_32); 765 if (ret) 766 return ret; 767 768 /* Enable Base Clk setting change */ 769 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 770 pci_write_config_dword(chip->pdev, 771 O2_SD_FUNC_REG4, 772 scratch_32); 773 774 /* Set Tuning Window to 4 */ 775 pci_write_config_byte(chip->pdev, 776 O2_SD_TUNING_CTRL, 0x44); 777 778 break; 779 } 780 } 781 782 /* Enable 8520 led function */ 783 o2_pci_led_enable(chip); 784 785 /* Set timeout CLK */ 786 ret = pci_read_config_dword(chip->pdev, 787 O2_SD_CLK_SETTING, &scratch_32); 788 if (ret) 789 return ret; 790 791 scratch_32 &= ~(0xFF00); 792 scratch_32 |= 0x07E0C800; 793 pci_write_config_dword(chip->pdev, 794 O2_SD_CLK_SETTING, scratch_32); 795 796 ret = pci_read_config_dword(chip->pdev, 797 O2_SD_CLKREQ, &scratch_32); 798 if (ret) 799 return ret; 800 scratch_32 |= 0x3; 801 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 802 803 ret = pci_read_config_dword(chip->pdev, 804 O2_SD_PLL_SETTING, &scratch_32); 805 if (ret) 806 return ret; 807 808 scratch_32 &= ~(0x1F3F070E); 809 scratch_32 |= 0x18270106; 810 pci_write_config_dword(chip->pdev, 811 O2_SD_PLL_SETTING, scratch_32); 812 813 /* Disable UHS1 funciton */ 814 ret = pci_read_config_dword(chip->pdev, 815 O2_SD_CAP_REG2, &scratch_32); 816 if (ret) 817 return ret; 818 scratch_32 &= ~(0xE0); 819 pci_write_config_dword(chip->pdev, 820 O2_SD_CAP_REG2, scratch_32); 821 822 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 823 sdhci_pci_o2_fujin2_pci_init(chip); 824 825 /* Lock WP */ 826 ret = pci_read_config_byte(chip->pdev, 827 O2_SD_LOCK_WP, &scratch); 828 if (ret) 829 return ret; 830 scratch |= 0x80; 831 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 832 break; 833 case PCI_DEVICE_ID_O2_SEABIRD0: 834 case PCI_DEVICE_ID_O2_SEABIRD1: 835 /* UnLock WP */ 836 ret = pci_read_config_byte(chip->pdev, 837 O2_SD_LOCK_WP, &scratch); 838 if (ret) 839 return ret; 840 841 scratch &= 0x7f; 842 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 843 844 ret = pci_read_config_dword(chip->pdev, 845 O2_SD_PLL_SETTING, &scratch_32); 846 if (ret) 847 return ret; 848 849 if ((scratch_32 & 0xff000000) == 0x01000000) { 850 scratch_32 &= 0x0000FFFF; 851 scratch_32 |= 0x1F340000; 852 853 pci_write_config_dword(chip->pdev, 854 O2_SD_PLL_SETTING, scratch_32); 855 } else { 856 scratch_32 &= 0x0000FFFF; 857 scratch_32 |= 0x25100000; 858 859 pci_write_config_dword(chip->pdev, 860 O2_SD_PLL_SETTING, scratch_32); 861 862 ret = pci_read_config_dword(chip->pdev, 863 O2_SD_FUNC_REG4, 864 &scratch_32); 865 if (ret) 866 return ret; 867 scratch_32 |= (1 << 22); 868 pci_write_config_dword(chip->pdev, 869 O2_SD_FUNC_REG4, scratch_32); 870 } 871 872 /* Set Tuning Windows to 5 */ 873 pci_write_config_byte(chip->pdev, 874 O2_SD_TUNING_CTRL, 0x55); 875 /* Lock WP */ 876 ret = pci_read_config_byte(chip->pdev, 877 O2_SD_LOCK_WP, &scratch); 878 if (ret) 879 return ret; 880 scratch |= 0x80; 881 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 882 break; 883 } 884 885 return 0; 886 } 887 888 #ifdef CONFIG_PM_SLEEP 889 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 890 { 891 sdhci_pci_o2_probe(chip); 892 return sdhci_pci_resume_host(chip); 893 } 894 #endif 895 896 static const struct sdhci_ops sdhci_pci_o2_ops = { 897 .set_clock = sdhci_pci_o2_set_clock, 898 .enable_dma = sdhci_pci_enable_dma, 899 .set_bus_width = sdhci_set_bus_width, 900 .reset = sdhci_reset, 901 .set_uhs_signaling = sdhci_set_uhs_signaling, 902 }; 903 904 const struct sdhci_pci_fixes sdhci_o2 = { 905 .probe = sdhci_pci_o2_probe, 906 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 907 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 908 .probe_slot = sdhci_pci_o2_probe_slot, 909 #ifdef CONFIG_PM_SLEEP 910 .resume = sdhci_pci_o2_resume, 911 #endif 912 .ops = &sdhci_pci_o2_ops, 913 .priv_size = sizeof(struct o2_host), 914 }; 915