1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 BayHub Technology Ltd. 4 * 5 * Authors: Peter Guo <peter.guo@bayhubtech.com> 6 * Adam Lee <adam.lee@canonical.com> 7 * Ernest Zhang <ernest.zhang@bayhubtech.com> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/delay.h> 14 #include <linux/iopoll.h> 15 #include <linux/bitfield.h> 16 17 #include "sdhci.h" 18 #include "sdhci-pci.h" 19 20 /* 21 * O2Micro device registers 22 */ 23 24 #define O2_SD_MISC_REG5 0x64 25 #define O2_SD_LD0_CTRL 0x68 26 #define O2_SD_DEV_CTRL 0x88 27 #define O2_SD_LOCK_WP 0xD3 28 #define O2_SD_TEST_REG 0xD4 29 #define O2_SD_FUNC_REG0 0xDC 30 #define O2_SD_MULTI_VCC3V 0xEE 31 #define O2_SD_CLKREQ 0xEC 32 #define O2_SD_CAPS 0xE0 33 #define O2_SD_ADMA1 0xE2 34 #define O2_SD_ADMA2 0xE7 35 #define O2_SD_INF_MOD 0xF1 36 #define O2_SD_MISC_CTRL4 0xFC 37 #define O2_SD_MISC_CTRL 0x1C0 38 #define O2_SD_PWR_FORCE_L0 0x0002 39 #define O2_SD_TUNING_CTRL 0x300 40 #define O2_SD_PLL_SETTING 0x304 41 #define O2_SD_MISC_SETTING 0x308 42 #define O2_SD_CLK_SETTING 0x328 43 #define O2_SD_CAP_REG2 0x330 44 #define O2_SD_CAP_REG0 0x334 45 #define O2_SD_UHS1_CAP_SETTING 0x33C 46 #define O2_SD_DELAY_CTRL 0x350 47 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 48 #define O2_SD_UHS2_L1_CTRL 0x35C 49 #define O2_SD_FUNC_REG3 0x3E0 50 #define O2_SD_FUNC_REG4 0x3E4 51 #define O2_SD_LED_ENABLE BIT(6) 52 #define O2_SD_FREG0_LEDOFF BIT(13) 53 #define O2_SD_SEL_DLL BIT(16) 54 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 55 #define O2_SD_PHASE_MASK GENMASK(23, 20) 56 #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) 57 58 #define O2_SD_VENDOR_SETTING 0x110 59 #define O2_SD_VENDOR_SETTING2 0x1C8 60 #define O2_SD_HW_TUNING_DISABLE BIT(4) 61 62 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 63 #define O2_PLL_FORCE_ACTIVE BIT(18) 64 #define O2_PLL_LOCK_STATUS BIT(14) 65 #define O2_PLL_SOFT_RESET BIT(12) 66 #define O2_DLL_LOCK_STATUS BIT(11) 67 68 #define O2_SD_DETECT_SETTING 0x324 69 70 static const u32 dmdn_table[] = {0x2B1C0000, 71 0x2C1A0000, 0x371B0000, 0x35100000}; 72 #define DMDN_SZ ARRAY_SIZE(dmdn_table) 73 74 struct o2_host { 75 u8 dll_adjust_count; 76 }; 77 78 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 79 { 80 ktime_t timeout; 81 u32 scratch32; 82 83 /* Wait max 50 ms */ 84 timeout = ktime_add_ms(ktime_get(), 50); 85 while (1) { 86 bool timedout = ktime_after(ktime_get(), timeout); 87 88 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 89 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 90 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 91 break; 92 93 if (timedout) { 94 pr_err("%s: Card Detect debounce never finished.\n", 95 mmc_hostname(host->mmc)); 96 sdhci_dumpregs(host); 97 return; 98 } 99 udelay(10); 100 } 101 } 102 103 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 104 { 105 ktime_t timeout; 106 u16 scratch; 107 u32 scratch32; 108 109 /* PLL software reset */ 110 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 111 scratch32 |= O2_PLL_SOFT_RESET; 112 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 113 udelay(1); 114 scratch32 &= ~(O2_PLL_SOFT_RESET); 115 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 116 117 /* PLL force active */ 118 scratch32 |= O2_PLL_FORCE_ACTIVE; 119 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 120 121 /* Wait max 20 ms */ 122 timeout = ktime_add_ms(ktime_get(), 20); 123 while (1) { 124 bool timedout = ktime_after(ktime_get(), timeout); 125 126 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 127 if (scratch & O2_PLL_LOCK_STATUS) 128 break; 129 if (timedout) { 130 pr_err("%s: Internal clock never stabilised.\n", 131 mmc_hostname(host->mmc)); 132 sdhci_dumpregs(host); 133 goto out; 134 } 135 udelay(10); 136 } 137 138 /* Wait for card detect finish */ 139 udelay(1); 140 sdhci_o2_wait_card_detect_stable(host); 141 142 out: 143 /* Cancel PLL force active */ 144 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 145 scratch32 &= ~O2_PLL_FORCE_ACTIVE; 146 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 147 } 148 149 static int sdhci_o2_get_cd(struct mmc_host *mmc) 150 { 151 struct sdhci_host *host = mmc_priv(mmc); 152 153 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 154 sdhci_o2_enable_internal_clock(host); 155 else 156 sdhci_o2_wait_card_detect_stable(host); 157 158 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 159 } 160 161 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 162 { 163 u32 scratch_32; 164 165 pci_read_config_dword(chip->pdev, 166 O2_SD_PLL_SETTING, &scratch_32); 167 168 scratch_32 &= 0x0000FFFF; 169 scratch_32 |= value; 170 171 pci_write_config_dword(chip->pdev, 172 O2_SD_PLL_SETTING, scratch_32); 173 } 174 175 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 176 { 177 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 178 } 179 180 /* 181 * This function is used to detect dll lock status. 182 * Since the dll lock status bit will toggle randomly 183 * with very short interval which needs to be polled 184 * as fast as possible. Set sleep_us as 1 microsecond. 185 */ 186 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 187 { 188 u32 scratch32 = 0; 189 190 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 191 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 192 } 193 194 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 195 { 196 u16 reg; 197 198 /* enable hardware tuning */ 199 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 200 reg &= ~O2_SD_HW_TUNING_DISABLE; 201 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 202 } 203 204 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 205 { 206 int i; 207 208 sdhci_send_tuning(host, opcode); 209 210 for (i = 0; i < 150; i++) { 211 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 212 213 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 214 if (ctrl & SDHCI_CTRL_TUNED_CLK) { 215 host->tuning_done = true; 216 return; 217 } 218 pr_warn("%s: HW tuning failed !\n", 219 mmc_hostname(host->mmc)); 220 break; 221 } 222 223 mdelay(1); 224 } 225 226 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 227 mmc_hostname(host->mmc)); 228 sdhci_reset_tuning(host); 229 } 230 231 /* 232 * This function is used to fix o2 dll shift issue. 233 * It isn't necessary to detect card present before recovery. 234 * Firstly, it is used by bht emmc card, which is embedded. 235 * Second, before call recovery card present will be detected 236 * outside of the execute tuning function. 237 */ 238 static int sdhci_o2_dll_recovery(struct sdhci_host *host) 239 { 240 int ret = 0; 241 u8 scratch_8 = 0; 242 u32 scratch_32 = 0; 243 struct sdhci_pci_slot *slot = sdhci_priv(host); 244 struct sdhci_pci_chip *chip = slot->chip; 245 struct o2_host *o2_host = sdhci_pci_priv(slot); 246 247 /* UnLock WP */ 248 pci_read_config_byte(chip->pdev, 249 O2_SD_LOCK_WP, &scratch_8); 250 scratch_8 &= 0x7f; 251 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 252 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 253 /* Disable clock */ 254 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 255 256 /* PLL software reset */ 257 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 258 scratch_32 |= O2_PLL_SOFT_RESET; 259 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 260 261 pci_read_config_dword(chip->pdev, 262 O2_SD_FUNC_REG4, 263 &scratch_32); 264 /* Enable Base Clk setting change */ 265 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 266 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 267 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 268 269 /* Enable internal clock */ 270 scratch_8 = SDHCI_CLOCK_INT_EN; 271 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 272 273 if (sdhci_o2_get_cd(host->mmc)) { 274 /* 275 * need wait at least 5ms for dll status stable, 276 * after enable internal clock 277 */ 278 usleep_range(5000, 6000); 279 if (sdhci_o2_wait_dll_detect_lock(host)) { 280 scratch_8 |= SDHCI_CLOCK_CARD_EN; 281 sdhci_writeb(host, scratch_8, 282 SDHCI_CLOCK_CONTROL); 283 ret = 1; 284 } else { 285 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 286 mmc_hostname(host->mmc), 287 o2_host->dll_adjust_count); 288 } 289 } else { 290 pr_err("%s: card present detect failed.\n", 291 mmc_hostname(host->mmc)); 292 break; 293 } 294 295 o2_host->dll_adjust_count++; 296 } 297 if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 298 pr_err("%s: DLL adjust over max times\n", 299 mmc_hostname(host->mmc)); 300 /* Lock WP */ 301 pci_read_config_byte(chip->pdev, 302 O2_SD_LOCK_WP, &scratch_8); 303 scratch_8 |= 0x80; 304 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 305 return ret; 306 } 307 308 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 309 { 310 struct sdhci_host *host = mmc_priv(mmc); 311 struct sdhci_pci_slot *slot = sdhci_priv(host); 312 struct sdhci_pci_chip *chip = slot->chip; 313 int current_bus_width = 0; 314 u32 scratch32 = 0; 315 u16 scratch = 0; 316 u8 scratch_8 = 0; 317 u32 reg_val; 318 319 /* 320 * This handler only implements the eMMC tuning that is specific to 321 * this controller. Fall back to the standard method for other TIMING. 322 */ 323 if ((host->timing != MMC_TIMING_MMC_HS200) && 324 (host->timing != MMC_TIMING_UHS_SDR104)) 325 return sdhci_execute_tuning(mmc, opcode); 326 327 if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && 328 (opcode != MMC_SEND_TUNING_BLOCK))) 329 return -EINVAL; 330 331 /* Force power mode enter L0 */ 332 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 333 scratch |= O2_SD_PWR_FORCE_L0; 334 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 335 336 /* Stop clk */ 337 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 338 reg_val &= ~SDHCI_CLOCK_CARD_EN; 339 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 340 341 /* UnLock WP */ 342 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 343 scratch_8 &= 0x7f; 344 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 345 346 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ 347 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); 348 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 349 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); 350 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); 351 352 /* Lock WP */ 353 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 354 scratch_8 |= 0x80; 355 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 356 357 /* Start clk */ 358 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 359 reg_val |= SDHCI_CLOCK_CARD_EN; 360 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 361 362 /* wait DLL lock, timeout value 5ms */ 363 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 364 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) 365 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", 366 mmc_hostname(host->mmc)); 367 /* 368 * Judge the tuning reason, whether caused by dll shift 369 * If cause by dll shift, should call sdhci_o2_dll_recovery 370 */ 371 if (!sdhci_o2_wait_dll_detect_lock(host)) 372 if (!sdhci_o2_dll_recovery(host)) { 373 pr_err("%s: o2 dll recovery failed\n", 374 mmc_hostname(host->mmc)); 375 return -EINVAL; 376 } 377 /* 378 * o2 sdhci host didn't support 8bit emmc tuning 379 */ 380 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 381 current_bus_width = mmc->ios.bus_width; 382 mmc->ios.bus_width = MMC_BUS_WIDTH_4; 383 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 384 } 385 386 sdhci_o2_set_tuning_mode(host); 387 388 sdhci_start_tuning(host); 389 390 __sdhci_o2_execute_tuning(host, opcode); 391 392 sdhci_end_tuning(host); 393 394 if (current_bus_width == MMC_BUS_WIDTH_8) { 395 mmc->ios.bus_width = MMC_BUS_WIDTH_8; 396 sdhci_set_bus_width(host, current_bus_width); 397 } 398 399 /* Cancel force power mode enter L0 */ 400 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 401 scratch &= ~(O2_SD_PWR_FORCE_L0); 402 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 403 404 sdhci_reset(host, SDHCI_RESET_CMD); 405 sdhci_reset(host, SDHCI_RESET_DATA); 406 407 host->flags &= ~SDHCI_HS400_TUNING; 408 return 0; 409 } 410 411 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 412 { 413 int ret; 414 u32 scratch_32; 415 416 /* Set led of SD host function enable */ 417 ret = pci_read_config_dword(chip->pdev, 418 O2_SD_FUNC_REG0, &scratch_32); 419 if (ret) 420 return; 421 422 scratch_32 &= ~O2_SD_FREG0_LEDOFF; 423 pci_write_config_dword(chip->pdev, 424 O2_SD_FUNC_REG0, scratch_32); 425 426 ret = pci_read_config_dword(chip->pdev, 427 O2_SD_TEST_REG, &scratch_32); 428 if (ret) 429 return; 430 431 scratch_32 |= O2_SD_LED_ENABLE; 432 pci_write_config_dword(chip->pdev, 433 O2_SD_TEST_REG, scratch_32); 434 } 435 436 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 437 { 438 u32 scratch_32; 439 int ret; 440 /* Improve write performance for SD3.0 */ 441 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 442 if (ret) 443 return; 444 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 445 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 446 447 /* Enable Link abnormal reset generating Reset */ 448 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 449 if (ret) 450 return; 451 scratch_32 &= ~((1 << 19) | (1 << 11)); 452 scratch_32 |= (1 << 10); 453 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 454 455 /* set card power over current protection */ 456 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 457 if (ret) 458 return; 459 scratch_32 |= (1 << 4); 460 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 461 462 /* adjust the output delay for SD mode */ 463 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 464 465 /* Set the output voltage setting of Aux 1.2v LDO */ 466 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 467 if (ret) 468 return; 469 scratch_32 &= ~(3 << 12); 470 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 471 472 /* Set Max power supply capability of SD host */ 473 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 474 if (ret) 475 return; 476 scratch_32 &= ~(0x01FE); 477 scratch_32 |= 0x00CC; 478 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 479 /* Set DLL Tuning Window */ 480 ret = pci_read_config_dword(chip->pdev, 481 O2_SD_TUNING_CTRL, &scratch_32); 482 if (ret) 483 return; 484 scratch_32 &= ~(0x000000FF); 485 scratch_32 |= 0x00000066; 486 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 487 488 /* Set UHS2 T_EIDLE */ 489 ret = pci_read_config_dword(chip->pdev, 490 O2_SD_UHS2_L1_CTRL, &scratch_32); 491 if (ret) 492 return; 493 scratch_32 &= ~(0x000000FC); 494 scratch_32 |= 0x00000084; 495 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 496 497 /* Set UHS2 Termination */ 498 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 499 if (ret) 500 return; 501 scratch_32 &= ~((1 << 21) | (1 << 30)); 502 503 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 504 505 /* Set L1 Entrance Timer */ 506 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 507 if (ret) 508 return; 509 scratch_32 &= ~(0xf0000000); 510 scratch_32 |= 0x30000000; 511 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 512 513 ret = pci_read_config_dword(chip->pdev, 514 O2_SD_MISC_CTRL4, &scratch_32); 515 if (ret) 516 return; 517 scratch_32 &= ~(0x000f0000); 518 scratch_32 |= 0x00080000; 519 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 520 } 521 522 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 523 struct sdhci_host *host) 524 { 525 int ret; 526 527 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 528 if (!ret) { 529 pr_info("%s: unsupported MSI, use INTx irq\n", 530 mmc_hostname(host->mmc)); 531 return; 532 } 533 534 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 535 PCI_IRQ_MSI | PCI_IRQ_MSIX); 536 if (ret < 0) { 537 pr_err("%s: enable PCI MSI failed, err=%d\n", 538 mmc_hostname(host->mmc), ret); 539 return; 540 } 541 542 host->irq = pci_irq_vector(chip->pdev, 0); 543 } 544 545 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 546 { 547 /* Enable internal clock */ 548 clk |= SDHCI_CLOCK_INT_EN; 549 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 550 551 sdhci_o2_enable_internal_clock(host); 552 if (sdhci_o2_get_cd(host->mmc)) { 553 clk |= SDHCI_CLOCK_CARD_EN; 554 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 555 } 556 } 557 558 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 559 { 560 u16 clk; 561 u8 scratch; 562 u32 scratch_32; 563 struct sdhci_pci_slot *slot = sdhci_priv(host); 564 struct sdhci_pci_chip *chip = slot->chip; 565 566 host->mmc->actual_clock = 0; 567 568 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 569 570 if (clock == 0) 571 return; 572 573 /* UnLock WP */ 574 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 575 scratch &= 0x7f; 576 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 577 578 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { 579 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 580 581 if ((scratch_32 & 0xFFFF0000) != 0x2c280000) 582 o2_pci_set_baseclk(chip, 0x2c280000); 583 } else { 584 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 585 586 if ((scratch_32 & 0xFFFF0000) != 0x25100000) 587 o2_pci_set_baseclk(chip, 0x25100000); 588 } 589 590 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); 591 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 592 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); 593 594 /* Lock WP */ 595 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 596 scratch |= 0x80; 597 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 598 599 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 600 sdhci_o2_enable_clk(host, clk); 601 } 602 603 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 604 { 605 struct sdhci_pci_chip *chip; 606 struct sdhci_host *host; 607 struct o2_host *o2_host = sdhci_pci_priv(slot); 608 u32 reg, caps; 609 int ret; 610 611 chip = slot->chip; 612 host = slot->host; 613 614 o2_host->dll_adjust_count = 0; 615 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 616 617 /* 618 * mmc_select_bus_width() will test the bus to determine the actual bus 619 * width. 620 */ 621 if (caps & SDHCI_CAN_DO_8BIT) 622 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 623 624 switch (chip->pdev->device) { 625 case PCI_DEVICE_ID_O2_SDS0: 626 case PCI_DEVICE_ID_O2_SEABIRD0: 627 case PCI_DEVICE_ID_O2_SEABIRD1: 628 case PCI_DEVICE_ID_O2_SDS1: 629 case PCI_DEVICE_ID_O2_FUJIN2: 630 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 631 if (reg & 0x1) 632 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 633 634 sdhci_pci_o2_enable_msi(chip, host); 635 636 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 637 ret = pci_read_config_dword(chip->pdev, 638 O2_SD_MISC_SETTING, ®); 639 if (ret) 640 return -EIO; 641 if (reg & (1 << 4)) { 642 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 643 mmc_hostname(host->mmc)); 644 host->flags &= ~SDHCI_SIGNALING_330; 645 host->flags |= SDHCI_SIGNALING_180; 646 host->mmc->caps2 |= MMC_CAP2_NO_SD; 647 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 648 pci_write_config_dword(chip->pdev, 649 O2_SD_DETECT_SETTING, 3); 650 } 651 652 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 653 } 654 655 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { 656 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 657 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 658 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 659 } 660 661 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 662 663 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 664 break; 665 /* set dll watch dog timer */ 666 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 667 reg |= (1 << 12); 668 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 669 670 break; 671 default: 672 break; 673 } 674 675 return 0; 676 } 677 678 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 679 { 680 int ret; 681 u8 scratch; 682 u32 scratch_32; 683 684 switch (chip->pdev->device) { 685 case PCI_DEVICE_ID_O2_8220: 686 case PCI_DEVICE_ID_O2_8221: 687 case PCI_DEVICE_ID_O2_8320: 688 case PCI_DEVICE_ID_O2_8321: 689 /* This extra setup is required due to broken ADMA. */ 690 ret = pci_read_config_byte(chip->pdev, 691 O2_SD_LOCK_WP, &scratch); 692 if (ret) 693 return ret; 694 scratch &= 0x7f; 695 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 696 697 /* Set Multi 3 to VCC3V# */ 698 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 699 700 /* Disable CLK_REQ# support after media DET */ 701 ret = pci_read_config_byte(chip->pdev, 702 O2_SD_CLKREQ, &scratch); 703 if (ret) 704 return ret; 705 scratch |= 0x20; 706 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 707 708 /* Choose capabilities, enable SDMA. We have to write 0x01 709 * to the capabilities register first to unlock it. 710 */ 711 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 712 if (ret) 713 return ret; 714 scratch |= 0x01; 715 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 716 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 717 718 /* Disable ADMA1/2 */ 719 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 720 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 721 722 /* Disable the infinite transfer mode */ 723 ret = pci_read_config_byte(chip->pdev, 724 O2_SD_INF_MOD, &scratch); 725 if (ret) 726 return ret; 727 scratch |= 0x08; 728 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 729 730 /* Lock WP */ 731 ret = pci_read_config_byte(chip->pdev, 732 O2_SD_LOCK_WP, &scratch); 733 if (ret) 734 return ret; 735 scratch |= 0x80; 736 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 737 break; 738 case PCI_DEVICE_ID_O2_SDS0: 739 case PCI_DEVICE_ID_O2_SDS1: 740 case PCI_DEVICE_ID_O2_FUJIN2: 741 /* UnLock WP */ 742 ret = pci_read_config_byte(chip->pdev, 743 O2_SD_LOCK_WP, &scratch); 744 if (ret) 745 return ret; 746 747 scratch &= 0x7f; 748 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 749 750 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 751 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 752 ret = pci_read_config_dword(chip->pdev, 753 O2_SD_FUNC_REG0, 754 &scratch_32); 755 if (ret) 756 return ret; 757 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 758 759 /* Check Whether subId is 0x11 or 0x12 */ 760 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 761 scratch_32 = 0x25100000; 762 763 o2_pci_set_baseclk(chip, scratch_32); 764 ret = pci_read_config_dword(chip->pdev, 765 O2_SD_FUNC_REG4, 766 &scratch_32); 767 if (ret) 768 return ret; 769 770 /* Enable Base Clk setting change */ 771 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 772 pci_write_config_dword(chip->pdev, 773 O2_SD_FUNC_REG4, 774 scratch_32); 775 776 /* Set Tuning Window to 4 */ 777 pci_write_config_byte(chip->pdev, 778 O2_SD_TUNING_CTRL, 0x44); 779 780 break; 781 } 782 } 783 784 /* Enable 8520 led function */ 785 o2_pci_led_enable(chip); 786 787 /* Set timeout CLK */ 788 ret = pci_read_config_dword(chip->pdev, 789 O2_SD_CLK_SETTING, &scratch_32); 790 if (ret) 791 return ret; 792 793 scratch_32 &= ~(0xFF00); 794 scratch_32 |= 0x07E0C800; 795 pci_write_config_dword(chip->pdev, 796 O2_SD_CLK_SETTING, scratch_32); 797 798 ret = pci_read_config_dword(chip->pdev, 799 O2_SD_CLKREQ, &scratch_32); 800 if (ret) 801 return ret; 802 scratch_32 |= 0x3; 803 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 804 805 ret = pci_read_config_dword(chip->pdev, 806 O2_SD_PLL_SETTING, &scratch_32); 807 if (ret) 808 return ret; 809 810 scratch_32 &= ~(0x1F3F070E); 811 scratch_32 |= 0x18270106; 812 pci_write_config_dword(chip->pdev, 813 O2_SD_PLL_SETTING, scratch_32); 814 815 /* Disable UHS1 funciton */ 816 ret = pci_read_config_dword(chip->pdev, 817 O2_SD_CAP_REG2, &scratch_32); 818 if (ret) 819 return ret; 820 scratch_32 &= ~(0xE0); 821 pci_write_config_dword(chip->pdev, 822 O2_SD_CAP_REG2, scratch_32); 823 824 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 825 sdhci_pci_o2_fujin2_pci_init(chip); 826 827 /* Lock WP */ 828 ret = pci_read_config_byte(chip->pdev, 829 O2_SD_LOCK_WP, &scratch); 830 if (ret) 831 return ret; 832 scratch |= 0x80; 833 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 834 break; 835 case PCI_DEVICE_ID_O2_SEABIRD0: 836 case PCI_DEVICE_ID_O2_SEABIRD1: 837 /* UnLock WP */ 838 ret = pci_read_config_byte(chip->pdev, 839 O2_SD_LOCK_WP, &scratch); 840 if (ret) 841 return ret; 842 843 scratch &= 0x7f; 844 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 845 846 ret = pci_read_config_dword(chip->pdev, 847 O2_SD_PLL_SETTING, &scratch_32); 848 if (ret) 849 return ret; 850 851 if ((scratch_32 & 0xff000000) == 0x01000000) { 852 scratch_32 &= 0x0000FFFF; 853 scratch_32 |= 0x1F340000; 854 855 pci_write_config_dword(chip->pdev, 856 O2_SD_PLL_SETTING, scratch_32); 857 } else { 858 scratch_32 &= 0x0000FFFF; 859 scratch_32 |= 0x25100000; 860 861 pci_write_config_dword(chip->pdev, 862 O2_SD_PLL_SETTING, scratch_32); 863 864 ret = pci_read_config_dword(chip->pdev, 865 O2_SD_FUNC_REG4, 866 &scratch_32); 867 if (ret) 868 return ret; 869 scratch_32 |= (1 << 22); 870 pci_write_config_dword(chip->pdev, 871 O2_SD_FUNC_REG4, scratch_32); 872 } 873 874 /* Set Tuning Windows to 5 */ 875 pci_write_config_byte(chip->pdev, 876 O2_SD_TUNING_CTRL, 0x55); 877 /* Lock WP */ 878 ret = pci_read_config_byte(chip->pdev, 879 O2_SD_LOCK_WP, &scratch); 880 if (ret) 881 return ret; 882 scratch |= 0x80; 883 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 884 break; 885 } 886 887 return 0; 888 } 889 890 #ifdef CONFIG_PM_SLEEP 891 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 892 { 893 sdhci_pci_o2_probe(chip); 894 return sdhci_pci_resume_host(chip); 895 } 896 #endif 897 898 static const struct sdhci_ops sdhci_pci_o2_ops = { 899 .set_clock = sdhci_pci_o2_set_clock, 900 .enable_dma = sdhci_pci_enable_dma, 901 .set_bus_width = sdhci_set_bus_width, 902 .reset = sdhci_reset, 903 .set_uhs_signaling = sdhci_set_uhs_signaling, 904 }; 905 906 const struct sdhci_pci_fixes sdhci_o2 = { 907 .probe = sdhci_pci_o2_probe, 908 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 909 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 910 .probe_slot = sdhci_pci_o2_probe_slot, 911 #ifdef CONFIG_PM_SLEEP 912 .resume = sdhci_pci_o2_resume, 913 #endif 914 .ops = &sdhci_pci_o2_ops, 915 .priv_size = sizeof(struct o2_host), 916 }; 917