1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 BayHub Technology Ltd. 4 * 5 * Authors: Peter Guo <peter.guo@bayhubtech.com> 6 * Adam Lee <adam.lee@canonical.com> 7 * Ernest Zhang <ernest.zhang@bayhubtech.com> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/mmc.h> 13 #include <linux/delay.h> 14 #include <linux/iopoll.h> 15 #include <linux/bitfield.h> 16 17 #include "sdhci.h" 18 #include "sdhci-pci.h" 19 20 /* 21 * O2Micro device registers 22 */ 23 24 #define O2_SD_MISC_REG5 0x64 25 #define O2_SD_LD0_CTRL 0x68 26 #define O2_SD_DEV_CTRL 0x88 27 #define O2_SD_LOCK_WP 0xD3 28 #define O2_SD_TEST_REG 0xD4 29 #define O2_SD_FUNC_REG0 0xDC 30 #define O2_SD_MULTI_VCC3V 0xEE 31 #define O2_SD_CLKREQ 0xEC 32 #define O2_SD_CAPS 0xE0 33 #define O2_SD_ADMA1 0xE2 34 #define O2_SD_ADMA2 0xE7 35 #define O2_SD_MISC_CTRL2 0xF0 36 #define O2_SD_INF_MOD 0xF1 37 #define O2_SD_MISC_CTRL4 0xFC 38 #define O2_SD_MISC_CTRL 0x1C0 39 #define O2_SD_PWR_FORCE_L0 0x0002 40 #define O2_SD_TUNING_CTRL 0x300 41 #define O2_SD_PLL_SETTING 0x304 42 #define O2_SD_MISC_SETTING 0x308 43 #define O2_SD_CLK_SETTING 0x328 44 #define O2_SD_CAP_REG2 0x330 45 #define O2_SD_CAP_REG0 0x334 46 #define O2_SD_UHS1_CAP_SETTING 0x33C 47 #define O2_SD_DELAY_CTRL 0x350 48 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 49 #define O2_SD_UHS2_L1_CTRL 0x35C 50 #define O2_SD_FUNC_REG3 0x3E0 51 #define O2_SD_FUNC_REG4 0x3E4 52 #define O2_SD_LED_ENABLE BIT(6) 53 #define O2_SD_FREG0_LEDOFF BIT(13) 54 #define O2_SD_SEL_DLL BIT(16) 55 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 56 #define O2_SD_PHASE_MASK GENMASK(23, 20) 57 #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) 58 59 #define O2_SD_VENDOR_SETTING 0x110 60 #define O2_SD_VENDOR_SETTING2 0x1C8 61 #define O2_SD_HW_TUNING_DISABLE BIT(4) 62 63 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 64 #define O2_PLL_FORCE_ACTIVE BIT(18) 65 #define O2_PLL_LOCK_STATUS BIT(14) 66 #define O2_PLL_SOFT_RESET BIT(12) 67 #define O2_DLL_LOCK_STATUS BIT(11) 68 69 #define O2_SD_DETECT_SETTING 0x324 70 71 static const u32 dmdn_table[] = {0x2B1C0000, 72 0x2C1A0000, 0x371B0000, 0x35100000}; 73 #define DMDN_SZ ARRAY_SIZE(dmdn_table) 74 75 struct o2_host { 76 u8 dll_adjust_count; 77 }; 78 79 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 80 { 81 ktime_t timeout; 82 u32 scratch32; 83 84 /* Wait max 50 ms */ 85 timeout = ktime_add_ms(ktime_get(), 50); 86 while (1) { 87 bool timedout = ktime_after(ktime_get(), timeout); 88 89 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 90 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 91 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 92 break; 93 94 if (timedout) { 95 pr_err("%s: Card Detect debounce never finished.\n", 96 mmc_hostname(host->mmc)); 97 sdhci_dumpregs(host); 98 return; 99 } 100 udelay(10); 101 } 102 } 103 104 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 105 { 106 ktime_t timeout; 107 u16 scratch; 108 u32 scratch32; 109 110 /* PLL software reset */ 111 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 112 scratch32 |= O2_PLL_SOFT_RESET; 113 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 114 udelay(1); 115 scratch32 &= ~(O2_PLL_SOFT_RESET); 116 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 117 118 /* PLL force active */ 119 scratch32 |= O2_PLL_FORCE_ACTIVE; 120 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 121 122 /* Wait max 20 ms */ 123 timeout = ktime_add_ms(ktime_get(), 20); 124 while (1) { 125 bool timedout = ktime_after(ktime_get(), timeout); 126 127 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 128 if (scratch & O2_PLL_LOCK_STATUS) 129 break; 130 if (timedout) { 131 pr_err("%s: Internal clock never stabilised.\n", 132 mmc_hostname(host->mmc)); 133 sdhci_dumpregs(host); 134 goto out; 135 } 136 udelay(10); 137 } 138 139 /* Wait for card detect finish */ 140 udelay(1); 141 sdhci_o2_wait_card_detect_stable(host); 142 143 out: 144 /* Cancel PLL force active */ 145 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 146 scratch32 &= ~O2_PLL_FORCE_ACTIVE; 147 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 148 } 149 150 static int sdhci_o2_get_cd(struct mmc_host *mmc) 151 { 152 struct sdhci_host *host = mmc_priv(mmc); 153 154 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 155 sdhci_o2_enable_internal_clock(host); 156 else 157 sdhci_o2_wait_card_detect_stable(host); 158 159 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 160 } 161 162 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 163 { 164 u32 scratch_32; 165 166 pci_read_config_dword(chip->pdev, 167 O2_SD_PLL_SETTING, &scratch_32); 168 169 scratch_32 &= 0x0000FFFF; 170 scratch_32 |= value; 171 172 pci_write_config_dword(chip->pdev, 173 O2_SD_PLL_SETTING, scratch_32); 174 } 175 176 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 177 { 178 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 179 } 180 181 /* 182 * This function is used to detect dll lock status. 183 * Since the dll lock status bit will toggle randomly 184 * with very short interval which needs to be polled 185 * as fast as possible. Set sleep_us as 1 microsecond. 186 */ 187 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 188 { 189 u32 scratch32 = 0; 190 191 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 192 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 193 } 194 195 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 196 { 197 u16 reg; 198 199 /* enable hardware tuning */ 200 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 201 reg &= ~O2_SD_HW_TUNING_DISABLE; 202 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 203 } 204 205 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 206 { 207 int i; 208 209 sdhci_send_tuning(host, opcode); 210 211 for (i = 0; i < 150; i++) { 212 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 213 214 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 215 if (ctrl & SDHCI_CTRL_TUNED_CLK) { 216 host->tuning_done = true; 217 return; 218 } 219 pr_warn("%s: HW tuning failed !\n", 220 mmc_hostname(host->mmc)); 221 break; 222 } 223 224 mdelay(1); 225 } 226 227 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 228 mmc_hostname(host->mmc)); 229 sdhci_reset_tuning(host); 230 } 231 232 /* 233 * This function is used to fix o2 dll shift issue. 234 * It isn't necessary to detect card present before recovery. 235 * Firstly, it is used by bht emmc card, which is embedded. 236 * Second, before call recovery card present will be detected 237 * outside of the execute tuning function. 238 */ 239 static int sdhci_o2_dll_recovery(struct sdhci_host *host) 240 { 241 int ret = 0; 242 u8 scratch_8 = 0; 243 u32 scratch_32 = 0; 244 struct sdhci_pci_slot *slot = sdhci_priv(host); 245 struct sdhci_pci_chip *chip = slot->chip; 246 struct o2_host *o2_host = sdhci_pci_priv(slot); 247 248 /* UnLock WP */ 249 pci_read_config_byte(chip->pdev, 250 O2_SD_LOCK_WP, &scratch_8); 251 scratch_8 &= 0x7f; 252 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 253 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 254 /* Disable clock */ 255 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 256 257 /* PLL software reset */ 258 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 259 scratch_32 |= O2_PLL_SOFT_RESET; 260 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 261 262 pci_read_config_dword(chip->pdev, 263 O2_SD_FUNC_REG4, 264 &scratch_32); 265 /* Enable Base Clk setting change */ 266 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 267 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 268 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 269 270 /* Enable internal clock */ 271 scratch_8 = SDHCI_CLOCK_INT_EN; 272 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 273 274 if (sdhci_o2_get_cd(host->mmc)) { 275 /* 276 * need wait at least 5ms for dll status stable, 277 * after enable internal clock 278 */ 279 usleep_range(5000, 6000); 280 if (sdhci_o2_wait_dll_detect_lock(host)) { 281 scratch_8 |= SDHCI_CLOCK_CARD_EN; 282 sdhci_writeb(host, scratch_8, 283 SDHCI_CLOCK_CONTROL); 284 ret = 1; 285 } else { 286 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 287 mmc_hostname(host->mmc), 288 o2_host->dll_adjust_count); 289 } 290 } else { 291 pr_err("%s: card present detect failed.\n", 292 mmc_hostname(host->mmc)); 293 break; 294 } 295 296 o2_host->dll_adjust_count++; 297 } 298 if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 299 pr_err("%s: DLL adjust over max times\n", 300 mmc_hostname(host->mmc)); 301 /* Lock WP */ 302 pci_read_config_byte(chip->pdev, 303 O2_SD_LOCK_WP, &scratch_8); 304 scratch_8 |= 0x80; 305 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 306 return ret; 307 } 308 309 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 310 { 311 struct sdhci_host *host = mmc_priv(mmc); 312 struct sdhci_pci_slot *slot = sdhci_priv(host); 313 struct sdhci_pci_chip *chip = slot->chip; 314 int current_bus_width = 0; 315 u32 scratch32 = 0; 316 u16 scratch = 0; 317 u8 scratch_8 = 0; 318 u32 reg_val; 319 320 /* 321 * This handler implements the hardware tuning that is specific to 322 * this controller. Fall back to the standard method for other TIMING. 323 */ 324 if ((host->timing != MMC_TIMING_MMC_HS200) && 325 (host->timing != MMC_TIMING_UHS_SDR104) && 326 (host->timing != MMC_TIMING_UHS_SDR50)) 327 return sdhci_execute_tuning(mmc, opcode); 328 329 if (WARN_ON(!mmc_op_tuning(opcode))) 330 return -EINVAL; 331 332 /* Force power mode enter L0 */ 333 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 334 scratch |= O2_SD_PWR_FORCE_L0; 335 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 336 337 /* Stop clk */ 338 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 339 reg_val &= ~SDHCI_CLOCK_CARD_EN; 340 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 341 342 if ((host->timing == MMC_TIMING_MMC_HS200) || 343 (host->timing == MMC_TIMING_UHS_SDR104)) { 344 /* UnLock WP */ 345 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 346 scratch_8 &= 0x7f; 347 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 348 349 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ 350 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); 351 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 352 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); 353 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); 354 355 /* Lock WP */ 356 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 357 scratch_8 |= 0x80; 358 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 359 } 360 /* Start clk */ 361 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 362 reg_val |= SDHCI_CLOCK_CARD_EN; 363 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 364 365 /* wait DLL lock, timeout value 5ms */ 366 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 367 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) 368 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", 369 mmc_hostname(host->mmc)); 370 /* 371 * Judge the tuning reason, whether caused by dll shift 372 * If cause by dll shift, should call sdhci_o2_dll_recovery 373 */ 374 if (!sdhci_o2_wait_dll_detect_lock(host)) 375 if (!sdhci_o2_dll_recovery(host)) { 376 pr_err("%s: o2 dll recovery failed\n", 377 mmc_hostname(host->mmc)); 378 return -EINVAL; 379 } 380 /* 381 * o2 sdhci host didn't support 8bit emmc tuning 382 */ 383 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 384 current_bus_width = mmc->ios.bus_width; 385 mmc->ios.bus_width = MMC_BUS_WIDTH_4; 386 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 387 } 388 389 sdhci_o2_set_tuning_mode(host); 390 391 sdhci_start_tuning(host); 392 393 __sdhci_o2_execute_tuning(host, opcode); 394 395 sdhci_end_tuning(host); 396 397 if (current_bus_width == MMC_BUS_WIDTH_8) { 398 mmc->ios.bus_width = MMC_BUS_WIDTH_8; 399 sdhci_set_bus_width(host, current_bus_width); 400 } 401 402 /* Cancel force power mode enter L0 */ 403 scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 404 scratch &= ~(O2_SD_PWR_FORCE_L0); 405 sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 406 407 sdhci_reset(host, SDHCI_RESET_CMD); 408 sdhci_reset(host, SDHCI_RESET_DATA); 409 410 host->flags &= ~SDHCI_HS400_TUNING; 411 return 0; 412 } 413 414 static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 415 { 416 int ret; 417 u32 scratch_32; 418 419 /* Set led of SD host function enable */ 420 ret = pci_read_config_dword(chip->pdev, 421 O2_SD_FUNC_REG0, &scratch_32); 422 if (ret) 423 return; 424 425 scratch_32 &= ~O2_SD_FREG0_LEDOFF; 426 pci_write_config_dword(chip->pdev, 427 O2_SD_FUNC_REG0, scratch_32); 428 429 ret = pci_read_config_dword(chip->pdev, 430 O2_SD_TEST_REG, &scratch_32); 431 if (ret) 432 return; 433 434 scratch_32 |= O2_SD_LED_ENABLE; 435 pci_write_config_dword(chip->pdev, 436 O2_SD_TEST_REG, scratch_32); 437 } 438 439 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 440 { 441 u32 scratch_32; 442 int ret; 443 /* Improve write performance for SD3.0 */ 444 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 445 if (ret) 446 return; 447 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 448 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 449 450 /* Enable Link abnormal reset generating Reset */ 451 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 452 if (ret) 453 return; 454 scratch_32 &= ~((1 << 19) | (1 << 11)); 455 scratch_32 |= (1 << 10); 456 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 457 458 /* set card power over current protection */ 459 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 460 if (ret) 461 return; 462 scratch_32 |= (1 << 4); 463 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 464 465 /* adjust the output delay for SD mode */ 466 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 467 468 /* Set the output voltage setting of Aux 1.2v LDO */ 469 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 470 if (ret) 471 return; 472 scratch_32 &= ~(3 << 12); 473 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 474 475 /* Set Max power supply capability of SD host */ 476 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 477 if (ret) 478 return; 479 scratch_32 &= ~(0x01FE); 480 scratch_32 |= 0x00CC; 481 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 482 /* Set DLL Tuning Window */ 483 ret = pci_read_config_dword(chip->pdev, 484 O2_SD_TUNING_CTRL, &scratch_32); 485 if (ret) 486 return; 487 scratch_32 &= ~(0x000000FF); 488 scratch_32 |= 0x00000066; 489 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 490 491 /* Set UHS2 T_EIDLE */ 492 ret = pci_read_config_dword(chip->pdev, 493 O2_SD_UHS2_L1_CTRL, &scratch_32); 494 if (ret) 495 return; 496 scratch_32 &= ~(0x000000FC); 497 scratch_32 |= 0x00000084; 498 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 499 500 /* Set UHS2 Termination */ 501 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 502 if (ret) 503 return; 504 scratch_32 &= ~((1 << 21) | (1 << 30)); 505 506 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 507 508 /* Set L1 Entrance Timer */ 509 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 510 if (ret) 511 return; 512 scratch_32 &= ~(0xf0000000); 513 scratch_32 |= 0x30000000; 514 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 515 516 ret = pci_read_config_dword(chip->pdev, 517 O2_SD_MISC_CTRL4, &scratch_32); 518 if (ret) 519 return; 520 scratch_32 &= ~(0x000f0000); 521 scratch_32 |= 0x00080000; 522 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 523 } 524 525 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 526 struct sdhci_host *host) 527 { 528 int ret; 529 530 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 531 if (!ret) { 532 pr_info("%s: unsupported MSI, use INTx irq\n", 533 mmc_hostname(host->mmc)); 534 return; 535 } 536 537 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 538 PCI_IRQ_MSI | PCI_IRQ_MSIX); 539 if (ret < 0) { 540 pr_err("%s: enable PCI MSI failed, err=%d\n", 541 mmc_hostname(host->mmc), ret); 542 return; 543 } 544 545 host->irq = pci_irq_vector(chip->pdev, 0); 546 } 547 548 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 549 { 550 /* Enable internal clock */ 551 clk |= SDHCI_CLOCK_INT_EN; 552 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 553 554 sdhci_o2_enable_internal_clock(host); 555 if (sdhci_o2_get_cd(host->mmc)) { 556 clk |= SDHCI_CLOCK_CARD_EN; 557 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 558 } 559 } 560 561 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 562 { 563 u16 clk; 564 u8 scratch; 565 u32 scratch_32; 566 struct sdhci_pci_slot *slot = sdhci_priv(host); 567 struct sdhci_pci_chip *chip = slot->chip; 568 569 host->mmc->actual_clock = 0; 570 571 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 572 573 if (clock == 0) 574 return; 575 576 /* UnLock WP */ 577 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 578 scratch &= 0x7f; 579 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 580 581 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { 582 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 583 584 if ((scratch_32 & 0xFFFF0000) != 0x2c280000) 585 o2_pci_set_baseclk(chip, 0x2c280000); 586 } else { 587 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 588 589 if ((scratch_32 & 0xFFFF0000) != 0x25100000) 590 o2_pci_set_baseclk(chip, 0x25100000); 591 } 592 593 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); 594 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 595 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); 596 597 /* Lock WP */ 598 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 599 scratch |= 0x80; 600 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 601 602 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 603 sdhci_o2_enable_clk(host, clk); 604 } 605 606 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 607 { 608 struct sdhci_pci_chip *chip; 609 struct sdhci_host *host; 610 struct o2_host *o2_host = sdhci_pci_priv(slot); 611 u32 reg, caps; 612 int ret; 613 614 chip = slot->chip; 615 host = slot->host; 616 617 o2_host->dll_adjust_count = 0; 618 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 619 620 /* 621 * mmc_select_bus_width() will test the bus to determine the actual bus 622 * width. 623 */ 624 if (caps & SDHCI_CAN_DO_8BIT) 625 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 626 627 switch (chip->pdev->device) { 628 case PCI_DEVICE_ID_O2_SDS0: 629 case PCI_DEVICE_ID_O2_SEABIRD0: 630 case PCI_DEVICE_ID_O2_SEABIRD1: 631 case PCI_DEVICE_ID_O2_SDS1: 632 case PCI_DEVICE_ID_O2_FUJIN2: 633 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 634 if (reg & 0x1) 635 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 636 637 host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50; 638 639 sdhci_pci_o2_enable_msi(chip, host); 640 641 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 642 ret = pci_read_config_dword(chip->pdev, 643 O2_SD_MISC_SETTING, ®); 644 if (ret) 645 return -EIO; 646 if (reg & (1 << 4)) { 647 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 648 mmc_hostname(host->mmc)); 649 host->flags &= ~SDHCI_SIGNALING_330; 650 host->flags |= SDHCI_SIGNALING_180; 651 host->mmc->caps2 |= MMC_CAP2_NO_SD; 652 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 653 pci_write_config_dword(chip->pdev, 654 O2_SD_DETECT_SETTING, 3); 655 } 656 657 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 658 } 659 660 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { 661 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 662 host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 663 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 664 } 665 666 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 667 668 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 669 break; 670 /* set dll watch dog timer */ 671 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 672 reg |= (1 << 12); 673 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 674 675 break; 676 default: 677 break; 678 } 679 680 return 0; 681 } 682 683 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 684 { 685 int ret; 686 u8 scratch; 687 u32 scratch_32; 688 689 switch (chip->pdev->device) { 690 case PCI_DEVICE_ID_O2_8220: 691 case PCI_DEVICE_ID_O2_8221: 692 case PCI_DEVICE_ID_O2_8320: 693 case PCI_DEVICE_ID_O2_8321: 694 /* This extra setup is required due to broken ADMA. */ 695 ret = pci_read_config_byte(chip->pdev, 696 O2_SD_LOCK_WP, &scratch); 697 if (ret) 698 return ret; 699 scratch &= 0x7f; 700 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 701 702 /* Set Multi 3 to VCC3V# */ 703 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 704 705 /* Disable CLK_REQ# support after media DET */ 706 ret = pci_read_config_byte(chip->pdev, 707 O2_SD_CLKREQ, &scratch); 708 if (ret) 709 return ret; 710 scratch |= 0x20; 711 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 712 713 /* Choose capabilities, enable SDMA. We have to write 0x01 714 * to the capabilities register first to unlock it. 715 */ 716 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 717 if (ret) 718 return ret; 719 scratch |= 0x01; 720 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 721 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 722 723 /* Disable ADMA1/2 */ 724 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 725 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 726 727 /* Disable the infinite transfer mode */ 728 ret = pci_read_config_byte(chip->pdev, 729 O2_SD_INF_MOD, &scratch); 730 if (ret) 731 return ret; 732 scratch |= 0x08; 733 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 734 735 /* Lock WP */ 736 ret = pci_read_config_byte(chip->pdev, 737 O2_SD_LOCK_WP, &scratch); 738 if (ret) 739 return ret; 740 scratch |= 0x80; 741 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 742 break; 743 case PCI_DEVICE_ID_O2_SDS0: 744 case PCI_DEVICE_ID_O2_SDS1: 745 case PCI_DEVICE_ID_O2_FUJIN2: 746 /* UnLock WP */ 747 ret = pci_read_config_byte(chip->pdev, 748 O2_SD_LOCK_WP, &scratch); 749 if (ret) 750 return ret; 751 752 scratch &= 0x7f; 753 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 754 755 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 756 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 757 ret = pci_read_config_dword(chip->pdev, 758 O2_SD_FUNC_REG0, 759 &scratch_32); 760 if (ret) 761 return ret; 762 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 763 764 /* Check Whether subId is 0x11 or 0x12 */ 765 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 766 scratch_32 = 0x25100000; 767 768 o2_pci_set_baseclk(chip, scratch_32); 769 ret = pci_read_config_dword(chip->pdev, 770 O2_SD_FUNC_REG4, 771 &scratch_32); 772 if (ret) 773 return ret; 774 775 /* Enable Base Clk setting change */ 776 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 777 pci_write_config_dword(chip->pdev, 778 O2_SD_FUNC_REG4, 779 scratch_32); 780 781 /* Set Tuning Window to 4 */ 782 pci_write_config_byte(chip->pdev, 783 O2_SD_TUNING_CTRL, 0x44); 784 785 break; 786 } 787 } 788 789 /* Enable 8520 led function */ 790 o2_pci_led_enable(chip); 791 792 /* Set timeout CLK */ 793 ret = pci_read_config_dword(chip->pdev, 794 O2_SD_CLK_SETTING, &scratch_32); 795 if (ret) 796 return ret; 797 798 scratch_32 &= ~(0xFF00); 799 scratch_32 |= 0x07E0C800; 800 pci_write_config_dword(chip->pdev, 801 O2_SD_CLK_SETTING, scratch_32); 802 803 ret = pci_read_config_dword(chip->pdev, 804 O2_SD_CLKREQ, &scratch_32); 805 if (ret) 806 return ret; 807 scratch_32 |= 0x3; 808 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 809 810 ret = pci_read_config_dword(chip->pdev, 811 O2_SD_PLL_SETTING, &scratch_32); 812 if (ret) 813 return ret; 814 815 scratch_32 &= ~(0x1F3F070E); 816 scratch_32 |= 0x18270106; 817 pci_write_config_dword(chip->pdev, 818 O2_SD_PLL_SETTING, scratch_32); 819 820 /* Disable UHS1 funciton */ 821 ret = pci_read_config_dword(chip->pdev, 822 O2_SD_CAP_REG2, &scratch_32); 823 if (ret) 824 return ret; 825 scratch_32 &= ~(0xE0); 826 pci_write_config_dword(chip->pdev, 827 O2_SD_CAP_REG2, scratch_32); 828 829 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 830 sdhci_pci_o2_fujin2_pci_init(chip); 831 832 /* Lock WP */ 833 ret = pci_read_config_byte(chip->pdev, 834 O2_SD_LOCK_WP, &scratch); 835 if (ret) 836 return ret; 837 scratch |= 0x80; 838 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 839 break; 840 case PCI_DEVICE_ID_O2_SEABIRD0: 841 case PCI_DEVICE_ID_O2_SEABIRD1: 842 /* UnLock WP */ 843 ret = pci_read_config_byte(chip->pdev, 844 O2_SD_LOCK_WP, &scratch); 845 if (ret) 846 return ret; 847 848 scratch &= 0x7f; 849 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 850 851 ret = pci_read_config_dword(chip->pdev, 852 O2_SD_PLL_SETTING, &scratch_32); 853 if (ret) 854 return ret; 855 856 if ((scratch_32 & 0xff000000) == 0x01000000) { 857 scratch_32 &= 0x0000FFFF; 858 scratch_32 |= 0x1F340000; 859 860 pci_write_config_dword(chip->pdev, 861 O2_SD_PLL_SETTING, scratch_32); 862 } else { 863 scratch_32 &= 0x0000FFFF; 864 scratch_32 |= 0x25100000; 865 866 pci_write_config_dword(chip->pdev, 867 O2_SD_PLL_SETTING, scratch_32); 868 869 ret = pci_read_config_dword(chip->pdev, 870 O2_SD_FUNC_REG4, 871 &scratch_32); 872 if (ret) 873 return ret; 874 scratch_32 |= (1 << 22); 875 pci_write_config_dword(chip->pdev, 876 O2_SD_FUNC_REG4, scratch_32); 877 } 878 879 /* Set Tuning Windows to 5 */ 880 pci_write_config_byte(chip->pdev, 881 O2_SD_TUNING_CTRL, 0x55); 882 //Adjust 1st and 2nd CD debounce time 883 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); 884 scratch_32 &= 0xFFE7FFFF; 885 scratch_32 |= 0x00180000; 886 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); 887 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1); 888 /* Lock WP */ 889 ret = pci_read_config_byte(chip->pdev, 890 O2_SD_LOCK_WP, &scratch); 891 if (ret) 892 return ret; 893 scratch |= 0x80; 894 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 895 break; 896 } 897 898 return 0; 899 } 900 901 #ifdef CONFIG_PM_SLEEP 902 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 903 { 904 sdhci_pci_o2_probe(chip); 905 return sdhci_pci_resume_host(chip); 906 } 907 #endif 908 909 static const struct sdhci_ops sdhci_pci_o2_ops = { 910 .set_clock = sdhci_pci_o2_set_clock, 911 .enable_dma = sdhci_pci_enable_dma, 912 .set_bus_width = sdhci_set_bus_width, 913 .reset = sdhci_reset, 914 .set_uhs_signaling = sdhci_set_uhs_signaling, 915 }; 916 917 const struct sdhci_pci_fixes sdhci_o2 = { 918 .probe = sdhci_pci_o2_probe, 919 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 920 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 921 .probe_slot = sdhci_pci_o2_probe_slot, 922 #ifdef CONFIG_PM_SLEEP 923 .resume = sdhci_pci_o2_resume, 924 #endif 925 .ops = &sdhci_pci_o2_ops, 926 .priv_size = sizeof(struct o2_host), 927 }; 928