1*9c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 201acf691SAdam Lee /* 301acf691SAdam Lee * Copyright (C) 2013 BayHub Technology Ltd. 401acf691SAdam Lee * 501acf691SAdam Lee * Authors: Peter Guo <peter.guo@bayhubtech.com> 601acf691SAdam Lee * Adam Lee <adam.lee@canonical.com> 757322d54Sernest.zhang * Ernest Zhang <ernest.zhang@bayhubtech.com> 801acf691SAdam Lee */ 901acf691SAdam Lee 1001acf691SAdam Lee #include <linux/pci.h> 110086fc21Sernest.zhang #include <linux/mmc/host.h> 120086fc21Sernest.zhang #include <linux/mmc/mmc.h> 130086fc21Sernest.zhang #include <linux/delay.h> 1401acf691SAdam Lee 1501acf691SAdam Lee #include "sdhci.h" 1601acf691SAdam Lee #include "sdhci-pci.h" 17361eeda0SAdrian Hunter 18361eeda0SAdrian Hunter /* 19361eeda0SAdrian Hunter * O2Micro device registers 20361eeda0SAdrian Hunter */ 21361eeda0SAdrian Hunter 22361eeda0SAdrian Hunter #define O2_SD_MISC_REG5 0x64 23361eeda0SAdrian Hunter #define O2_SD_LD0_CTRL 0x68 24361eeda0SAdrian Hunter #define O2_SD_DEV_CTRL 0x88 25361eeda0SAdrian Hunter #define O2_SD_LOCK_WP 0xD3 26361eeda0SAdrian Hunter #define O2_SD_TEST_REG 0xD4 27361eeda0SAdrian Hunter #define O2_SD_FUNC_REG0 0xDC 28361eeda0SAdrian Hunter #define O2_SD_MULTI_VCC3V 0xEE 29361eeda0SAdrian Hunter #define O2_SD_CLKREQ 0xEC 30361eeda0SAdrian Hunter #define O2_SD_CAPS 0xE0 31361eeda0SAdrian Hunter #define O2_SD_ADMA1 0xE2 32361eeda0SAdrian Hunter #define O2_SD_ADMA2 0xE7 33361eeda0SAdrian Hunter #define O2_SD_INF_MOD 0xF1 34361eeda0SAdrian Hunter #define O2_SD_MISC_CTRL4 0xFC 35361eeda0SAdrian Hunter #define O2_SD_TUNING_CTRL 0x300 36361eeda0SAdrian Hunter #define O2_SD_PLL_SETTING 0x304 3757322d54Sernest.zhang #define O2_SD_MISC_SETTING 0x308 38361eeda0SAdrian Hunter #define O2_SD_CLK_SETTING 0x328 39361eeda0SAdrian Hunter #define O2_SD_CAP_REG2 0x330 40361eeda0SAdrian Hunter #define O2_SD_CAP_REG0 0x334 41361eeda0SAdrian Hunter #define O2_SD_UHS1_CAP_SETTING 0x33C 42361eeda0SAdrian Hunter #define O2_SD_DELAY_CTRL 0x350 43361eeda0SAdrian Hunter #define O2_SD_UHS2_L1_CTRL 0x35C 44361eeda0SAdrian Hunter #define O2_SD_FUNC_REG3 0x3E0 45361eeda0SAdrian Hunter #define O2_SD_FUNC_REG4 0x3E4 46361eeda0SAdrian Hunter #define O2_SD_LED_ENABLE BIT(6) 47361eeda0SAdrian Hunter #define O2_SD_FREG0_LEDOFF BIT(13) 48361eeda0SAdrian Hunter #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 49361eeda0SAdrian Hunter 50361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING 0x110 51361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING2 0x1C8 520086fc21Sernest.zhang #define O2_SD_HW_TUNING_DISABLE BIT(4) 530086fc21Sernest.zhang 5469d91ed1SErnest Zhang(WH) #define O2_PLL_WDT_CONTROL1 0x1CC 5569d91ed1SErnest Zhang(WH) #define O2_PLL_FORCE_ACTIVE BIT(18) 5669d91ed1SErnest Zhang(WH) #define O2_PLL_LOCK_STATUS BIT(14) 5769d91ed1SErnest Zhang(WH) #define O2_PLL_SOFT_RESET BIT(12) 5869d91ed1SErnest Zhang(WH) 5969d91ed1SErnest Zhang(WH) #define O2_SD_DETECT_SETTING 0x324 6069d91ed1SErnest Zhang(WH) 610086fc21Sernest.zhang static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 620086fc21Sernest.zhang { 630086fc21Sernest.zhang u16 reg; 640086fc21Sernest.zhang 650086fc21Sernest.zhang /* enable hardware tuning */ 660086fc21Sernest.zhang reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 670086fc21Sernest.zhang reg &= ~O2_SD_HW_TUNING_DISABLE; 680086fc21Sernest.zhang sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 690086fc21Sernest.zhang } 700086fc21Sernest.zhang 710086fc21Sernest.zhang static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 720086fc21Sernest.zhang { 730086fc21Sernest.zhang int i; 740086fc21Sernest.zhang 750086fc21Sernest.zhang sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200); 760086fc21Sernest.zhang 770086fc21Sernest.zhang for (i = 0; i < 150; i++) { 780086fc21Sernest.zhang u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 790086fc21Sernest.zhang 800086fc21Sernest.zhang if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 810086fc21Sernest.zhang if (ctrl & SDHCI_CTRL_TUNED_CLK) { 820086fc21Sernest.zhang host->tuning_done = true; 830086fc21Sernest.zhang return; 840086fc21Sernest.zhang } 850086fc21Sernest.zhang pr_warn("%s: HW tuning failed !\n", 860086fc21Sernest.zhang mmc_hostname(host->mmc)); 870086fc21Sernest.zhang break; 880086fc21Sernest.zhang } 890086fc21Sernest.zhang 900086fc21Sernest.zhang mdelay(1); 910086fc21Sernest.zhang } 920086fc21Sernest.zhang 930086fc21Sernest.zhang pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 940086fc21Sernest.zhang mmc_hostname(host->mmc)); 950086fc21Sernest.zhang sdhci_reset_tuning(host); 960086fc21Sernest.zhang } 970086fc21Sernest.zhang 980086fc21Sernest.zhang static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 990086fc21Sernest.zhang { 1000086fc21Sernest.zhang struct sdhci_host *host = mmc_priv(mmc); 1010086fc21Sernest.zhang int current_bus_width = 0; 1020086fc21Sernest.zhang 1030086fc21Sernest.zhang /* 1040086fc21Sernest.zhang * This handler only implements the eMMC tuning that is specific to 1050086fc21Sernest.zhang * this controller. Fall back to the standard method for other TIMING. 1060086fc21Sernest.zhang */ 1070086fc21Sernest.zhang if (host->timing != MMC_TIMING_MMC_HS200) 1080086fc21Sernest.zhang return sdhci_execute_tuning(mmc, opcode); 1090086fc21Sernest.zhang 1100086fc21Sernest.zhang if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1110086fc21Sernest.zhang return -EINVAL; 1120086fc21Sernest.zhang 1130086fc21Sernest.zhang /* 1140086fc21Sernest.zhang * o2 sdhci host didn't support 8bit emmc tuning 1150086fc21Sernest.zhang */ 1160086fc21Sernest.zhang if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 1170086fc21Sernest.zhang current_bus_width = mmc->ios.bus_width; 1180086fc21Sernest.zhang sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 1190086fc21Sernest.zhang } 1200086fc21Sernest.zhang 1210086fc21Sernest.zhang sdhci_o2_set_tuning_mode(host); 1220086fc21Sernest.zhang 1230086fc21Sernest.zhang sdhci_start_tuning(host); 1240086fc21Sernest.zhang 1250086fc21Sernest.zhang __sdhci_o2_execute_tuning(host, opcode); 1260086fc21Sernest.zhang 1270086fc21Sernest.zhang sdhci_end_tuning(host); 1280086fc21Sernest.zhang 1290086fc21Sernest.zhang if (current_bus_width == MMC_BUS_WIDTH_8) 1300086fc21Sernest.zhang sdhci_set_bus_width(host, current_bus_width); 1310086fc21Sernest.zhang 1320086fc21Sernest.zhang host->flags &= ~SDHCI_HS400_TUNING; 1330086fc21Sernest.zhang return 0; 1340086fc21Sernest.zhang } 13501acf691SAdam Lee 136706adf6bSPeter Guo static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 137706adf6bSPeter Guo { 138706adf6bSPeter Guo u32 scratch_32; 139706adf6bSPeter Guo pci_read_config_dword(chip->pdev, 140706adf6bSPeter Guo O2_SD_PLL_SETTING, &scratch_32); 141706adf6bSPeter Guo 142706adf6bSPeter Guo scratch_32 &= 0x0000FFFF; 143706adf6bSPeter Guo scratch_32 |= value; 144706adf6bSPeter Guo 145706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 146706adf6bSPeter Guo O2_SD_PLL_SETTING, scratch_32); 147706adf6bSPeter Guo } 148706adf6bSPeter Guo 149706adf6bSPeter Guo static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 150706adf6bSPeter Guo { 151706adf6bSPeter Guo int ret; 152706adf6bSPeter Guo u32 scratch_32; 153706adf6bSPeter Guo 154706adf6bSPeter Guo /* Set led of SD host function enable */ 155706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 156706adf6bSPeter Guo O2_SD_FUNC_REG0, &scratch_32); 157706adf6bSPeter Guo if (ret) 158706adf6bSPeter Guo return; 159706adf6bSPeter Guo 160706adf6bSPeter Guo scratch_32 &= ~O2_SD_FREG0_LEDOFF; 161706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 162706adf6bSPeter Guo O2_SD_FUNC_REG0, scratch_32); 163706adf6bSPeter Guo 164706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 165706adf6bSPeter Guo O2_SD_TEST_REG, &scratch_32); 166706adf6bSPeter Guo if (ret) 167706adf6bSPeter Guo return; 168706adf6bSPeter Guo 169706adf6bSPeter Guo scratch_32 |= O2_SD_LED_ENABLE; 170706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 171706adf6bSPeter Guo O2_SD_TEST_REG, scratch_32); 172706adf6bSPeter Guo 173706adf6bSPeter Guo } 174706adf6bSPeter Guo 175f0cbd780SBen Hutchings static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 17601acf691SAdam Lee { 17701acf691SAdam Lee u32 scratch_32; 17801acf691SAdam Lee int ret; 17901acf691SAdam Lee /* Improve write performance for SD3.0 */ 18001acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 18101acf691SAdam Lee if (ret) 18201acf691SAdam Lee return; 18301acf691SAdam Lee scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 18401acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 18501acf691SAdam Lee 18601acf691SAdam Lee /* Enable Link abnormal reset generating Reset */ 18701acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 18801acf691SAdam Lee if (ret) 18901acf691SAdam Lee return; 19001acf691SAdam Lee scratch_32 &= ~((1 << 19) | (1 << 11)); 19101acf691SAdam Lee scratch_32 |= (1 << 10); 19201acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 19301acf691SAdam Lee 19401acf691SAdam Lee /* set card power over current protection */ 19501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 19601acf691SAdam Lee if (ret) 19701acf691SAdam Lee return; 19801acf691SAdam Lee scratch_32 |= (1 << 4); 19901acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 20001acf691SAdam Lee 20101acf691SAdam Lee /* adjust the output delay for SD mode */ 20201acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 20301acf691SAdam Lee 20401acf691SAdam Lee /* Set the output voltage setting of Aux 1.2v LDO */ 20501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 20601acf691SAdam Lee if (ret) 20701acf691SAdam Lee return; 20801acf691SAdam Lee scratch_32 &= ~(3 << 12); 20901acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 21001acf691SAdam Lee 21101acf691SAdam Lee /* Set Max power supply capability of SD host */ 21201acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 21301acf691SAdam Lee if (ret) 21401acf691SAdam Lee return; 21501acf691SAdam Lee scratch_32 &= ~(0x01FE); 21601acf691SAdam Lee scratch_32 |= 0x00CC; 21701acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 21801acf691SAdam Lee /* Set DLL Tuning Window */ 21901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 22001acf691SAdam Lee O2_SD_TUNING_CTRL, &scratch_32); 22101acf691SAdam Lee if (ret) 22201acf691SAdam Lee return; 22301acf691SAdam Lee scratch_32 &= ~(0x000000FF); 22401acf691SAdam Lee scratch_32 |= 0x00000066; 22501acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 22601acf691SAdam Lee 22701acf691SAdam Lee /* Set UHS2 T_EIDLE */ 22801acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 22901acf691SAdam Lee O2_SD_UHS2_L1_CTRL, &scratch_32); 23001acf691SAdam Lee if (ret) 23101acf691SAdam Lee return; 23201acf691SAdam Lee scratch_32 &= ~(0x000000FC); 23301acf691SAdam Lee scratch_32 |= 0x00000084; 23401acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 23501acf691SAdam Lee 23601acf691SAdam Lee /* Set UHS2 Termination */ 23701acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 23801acf691SAdam Lee if (ret) 23901acf691SAdam Lee return; 24001acf691SAdam Lee scratch_32 &= ~((1 << 21) | (1 << 30)); 24101acf691SAdam Lee 24201acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 24301acf691SAdam Lee 24401acf691SAdam Lee /* Set L1 Entrance Timer */ 24501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 24601acf691SAdam Lee if (ret) 24701acf691SAdam Lee return; 24801acf691SAdam Lee scratch_32 &= ~(0xf0000000); 24901acf691SAdam Lee scratch_32 |= 0x30000000; 25001acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 25101acf691SAdam Lee 25201acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 25301acf691SAdam Lee O2_SD_MISC_CTRL4, &scratch_32); 25401acf691SAdam Lee if (ret) 25501acf691SAdam Lee return; 25601acf691SAdam Lee scratch_32 &= ~(0x000f0000); 25701acf691SAdam Lee scratch_32 |= 0x00080000; 25801acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 25901acf691SAdam Lee } 26001acf691SAdam Lee 26102a3c0bdSernest.zhang static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 26202a3c0bdSernest.zhang struct sdhci_host *host) 26302a3c0bdSernest.zhang { 26402a3c0bdSernest.zhang int ret; 26502a3c0bdSernest.zhang 26602a3c0bdSernest.zhang ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 26702a3c0bdSernest.zhang if (!ret) { 26802a3c0bdSernest.zhang pr_info("%s: unsupport msi, use INTx irq\n", 26902a3c0bdSernest.zhang mmc_hostname(host->mmc)); 27002a3c0bdSernest.zhang return; 27102a3c0bdSernest.zhang } 27202a3c0bdSernest.zhang 27302a3c0bdSernest.zhang ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 27402a3c0bdSernest.zhang PCI_IRQ_MSI | PCI_IRQ_MSIX); 27502a3c0bdSernest.zhang if (ret < 0) { 27602a3c0bdSernest.zhang pr_err("%s: enable PCI MSI failed, err=%d\n", 27702a3c0bdSernest.zhang mmc_hostname(host->mmc), ret); 27802a3c0bdSernest.zhang return; 27902a3c0bdSernest.zhang } 28002a3c0bdSernest.zhang 28102a3c0bdSernest.zhang host->irq = pci_irq_vector(chip->pdev, 0); 28202a3c0bdSernest.zhang } 28302a3c0bdSernest.zhang 28469d91ed1SErnest Zhang(WH) static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 28569d91ed1SErnest Zhang(WH) { 28669d91ed1SErnest Zhang(WH) ktime_t timeout; 28769d91ed1SErnest Zhang(WH) u32 scratch32; 28869d91ed1SErnest Zhang(WH) 28969d91ed1SErnest Zhang(WH) /* Wait max 50 ms */ 29069d91ed1SErnest Zhang(WH) timeout = ktime_add_ms(ktime_get(), 50); 29169d91ed1SErnest Zhang(WH) while (1) { 29269d91ed1SErnest Zhang(WH) bool timedout = ktime_after(ktime_get(), timeout); 29369d91ed1SErnest Zhang(WH) 29469d91ed1SErnest Zhang(WH) scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 29569d91ed1SErnest Zhang(WH) if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 29669d91ed1SErnest Zhang(WH) == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 29769d91ed1SErnest Zhang(WH) break; 29869d91ed1SErnest Zhang(WH) 29969d91ed1SErnest Zhang(WH) if (timedout) { 30069d91ed1SErnest Zhang(WH) pr_err("%s: Card Detect debounce never finished.\n", 30169d91ed1SErnest Zhang(WH) mmc_hostname(host->mmc)); 30269d91ed1SErnest Zhang(WH) sdhci_dumpregs(host); 30369d91ed1SErnest Zhang(WH) return; 30469d91ed1SErnest Zhang(WH) } 30569d91ed1SErnest Zhang(WH) udelay(10); 30669d91ed1SErnest Zhang(WH) } 30769d91ed1SErnest Zhang(WH) } 30869d91ed1SErnest Zhang(WH) 30969d91ed1SErnest Zhang(WH) static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 31069d91ed1SErnest Zhang(WH) { 31169d91ed1SErnest Zhang(WH) ktime_t timeout; 31269d91ed1SErnest Zhang(WH) u16 scratch; 31369d91ed1SErnest Zhang(WH) u32 scratch32; 31469d91ed1SErnest Zhang(WH) 31569d91ed1SErnest Zhang(WH) /* PLL software reset */ 31669d91ed1SErnest Zhang(WH) scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 31769d91ed1SErnest Zhang(WH) scratch32 |= O2_PLL_SOFT_RESET; 31869d91ed1SErnest Zhang(WH) sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 31969d91ed1SErnest Zhang(WH) udelay(1); 32069d91ed1SErnest Zhang(WH) scratch32 &= ~(O2_PLL_SOFT_RESET); 32169d91ed1SErnest Zhang(WH) sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 32269d91ed1SErnest Zhang(WH) 32369d91ed1SErnest Zhang(WH) /* PLL force active */ 32469d91ed1SErnest Zhang(WH) scratch32 |= O2_PLL_FORCE_ACTIVE; 32569d91ed1SErnest Zhang(WH) sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 32669d91ed1SErnest Zhang(WH) 32769d91ed1SErnest Zhang(WH) /* Wait max 20 ms */ 32869d91ed1SErnest Zhang(WH) timeout = ktime_add_ms(ktime_get(), 20); 32969d91ed1SErnest Zhang(WH) while (1) { 33069d91ed1SErnest Zhang(WH) bool timedout = ktime_after(ktime_get(), timeout); 33169d91ed1SErnest Zhang(WH) 33269d91ed1SErnest Zhang(WH) scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1); 33369d91ed1SErnest Zhang(WH) if (scratch & O2_PLL_LOCK_STATUS) 33469d91ed1SErnest Zhang(WH) break; 33569d91ed1SErnest Zhang(WH) if (timedout) { 33669d91ed1SErnest Zhang(WH) pr_err("%s: Internal clock never stabilised.\n", 33769d91ed1SErnest Zhang(WH) mmc_hostname(host->mmc)); 33869d91ed1SErnest Zhang(WH) sdhci_dumpregs(host); 33969d91ed1SErnest Zhang(WH) goto out; 34069d91ed1SErnest Zhang(WH) } 34169d91ed1SErnest Zhang(WH) udelay(10); 34269d91ed1SErnest Zhang(WH) } 34369d91ed1SErnest Zhang(WH) 34469d91ed1SErnest Zhang(WH) /* Wait for card detect finish */ 34569d91ed1SErnest Zhang(WH) udelay(1); 34669d91ed1SErnest Zhang(WH) sdhci_o2_wait_card_detect_stable(host); 34769d91ed1SErnest Zhang(WH) 34869d91ed1SErnest Zhang(WH) out: 34969d91ed1SErnest Zhang(WH) /* Cancel PLL force active */ 35069d91ed1SErnest Zhang(WH) scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); 35169d91ed1SErnest Zhang(WH) scratch32 &= ~O2_PLL_FORCE_ACTIVE; 35269d91ed1SErnest Zhang(WH) sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); 35369d91ed1SErnest Zhang(WH) } 35469d91ed1SErnest Zhang(WH) 35569d91ed1SErnest Zhang(WH) static int sdhci_o2_get_cd(struct mmc_host *mmc) 35669d91ed1SErnest Zhang(WH) { 35769d91ed1SErnest Zhang(WH) struct sdhci_host *host = mmc_priv(mmc); 35869d91ed1SErnest Zhang(WH) 35969d91ed1SErnest Zhang(WH) sdhci_o2_enable_internal_clock(host); 36069d91ed1SErnest Zhang(WH) 36169d91ed1SErnest Zhang(WH) return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 36269d91ed1SErnest Zhang(WH) } 36369d91ed1SErnest Zhang(WH) 36469d91ed1SErnest Zhang(WH) static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 36569d91ed1SErnest Zhang(WH) { 36669d91ed1SErnest Zhang(WH) /* Enable internal clock */ 36769d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_INT_EN; 36869d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 36969d91ed1SErnest Zhang(WH) 37069d91ed1SErnest Zhang(WH) if (sdhci_o2_get_cd(host->mmc)) { 37169d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_CARD_EN; 37269d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 37369d91ed1SErnest Zhang(WH) } 37469d91ed1SErnest Zhang(WH) } 37569d91ed1SErnest Zhang(WH) 37669d91ed1SErnest Zhang(WH) void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 37769d91ed1SErnest Zhang(WH) { 37869d91ed1SErnest Zhang(WH) u16 clk; 37969d91ed1SErnest Zhang(WH) 38069d91ed1SErnest Zhang(WH) host->mmc->actual_clock = 0; 38169d91ed1SErnest Zhang(WH) 38269d91ed1SErnest Zhang(WH) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 38369d91ed1SErnest Zhang(WH) 38469d91ed1SErnest Zhang(WH) if (clock == 0) 38569d91ed1SErnest Zhang(WH) return; 38669d91ed1SErnest Zhang(WH) 38769d91ed1SErnest Zhang(WH) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 38869d91ed1SErnest Zhang(WH) sdhci_o2_enable_clk(host, clk); 38969d91ed1SErnest Zhang(WH) } 39069d91ed1SErnest Zhang(WH) 39101acf691SAdam Lee int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 39201acf691SAdam Lee { 39301acf691SAdam Lee struct sdhci_pci_chip *chip; 39401acf691SAdam Lee struct sdhci_host *host; 39501acf691SAdam Lee u32 reg; 39657322d54Sernest.zhang int ret; 39701acf691SAdam Lee 39801acf691SAdam Lee chip = slot->chip; 39901acf691SAdam Lee host = slot->host; 40001acf691SAdam Lee switch (chip->pdev->device) { 40101acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 40201acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 40301acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 40401acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 40501acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 40601acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 40701acf691SAdam Lee if (reg & 0x1) 40801acf691SAdam Lee host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 40901acf691SAdam Lee 41002a3c0bdSernest.zhang sdhci_pci_o2_enable_msi(chip, host); 41102a3c0bdSernest.zhang 41257322d54Sernest.zhang if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 41357322d54Sernest.zhang ret = pci_read_config_dword(chip->pdev, 41457322d54Sernest.zhang O2_SD_MISC_SETTING, ®); 41557322d54Sernest.zhang if (ret) 41657322d54Sernest.zhang return -EIO; 41757322d54Sernest.zhang if (reg & (1 << 4)) { 41857322d54Sernest.zhang pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 41957322d54Sernest.zhang mmc_hostname(host->mmc)); 42057322d54Sernest.zhang host->flags &= ~SDHCI_SIGNALING_330; 42157322d54Sernest.zhang host->flags |= SDHCI_SIGNALING_180; 422414126f9SErnest Zhang(WH) host->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 42357322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SD; 42457322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 42569d91ed1SErnest Zhang(WH) pci_write_config_dword(chip->pdev, 42669d91ed1SErnest Zhang(WH) O2_SD_DETECT_SETTING, 3); 42757322d54Sernest.zhang } 42869d91ed1SErnest Zhang(WH) 42969d91ed1SErnest Zhang(WH) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 43057322d54Sernest.zhang } 43157322d54Sernest.zhang 4320086fc21Sernest.zhang host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 4330086fc21Sernest.zhang 43401acf691SAdam Lee if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 43501acf691SAdam Lee break; 43601acf691SAdam Lee /* set dll watch dog timer */ 43701acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 43801acf691SAdam Lee reg |= (1 << 12); 43901acf691SAdam Lee sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 44001acf691SAdam Lee 44101acf691SAdam Lee break; 44201acf691SAdam Lee default: 44301acf691SAdam Lee break; 44401acf691SAdam Lee } 44501acf691SAdam Lee 44601acf691SAdam Lee return 0; 44701acf691SAdam Lee } 44801acf691SAdam Lee 44901acf691SAdam Lee int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 45001acf691SAdam Lee { 45101acf691SAdam Lee int ret; 45201acf691SAdam Lee u8 scratch; 45301acf691SAdam Lee u32 scratch_32; 45401acf691SAdam Lee 45501acf691SAdam Lee switch (chip->pdev->device) { 45601acf691SAdam Lee case PCI_DEVICE_ID_O2_8220: 45701acf691SAdam Lee case PCI_DEVICE_ID_O2_8221: 45801acf691SAdam Lee case PCI_DEVICE_ID_O2_8320: 45901acf691SAdam Lee case PCI_DEVICE_ID_O2_8321: 46001acf691SAdam Lee /* This extra setup is required due to broken ADMA. */ 46101acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 46201acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 46301acf691SAdam Lee if (ret) 46401acf691SAdam Lee return ret; 46501acf691SAdam Lee scratch &= 0x7f; 46601acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 46701acf691SAdam Lee 46801acf691SAdam Lee /* Set Multi 3 to VCC3V# */ 46901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 47001acf691SAdam Lee 47101acf691SAdam Lee /* Disable CLK_REQ# support after media DET */ 47201acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 47301acf691SAdam Lee O2_SD_CLKREQ, &scratch); 47401acf691SAdam Lee if (ret) 47501acf691SAdam Lee return ret; 47601acf691SAdam Lee scratch |= 0x20; 47701acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 47801acf691SAdam Lee 47901acf691SAdam Lee /* Choose capabilities, enable SDMA. We have to write 0x01 48001acf691SAdam Lee * to the capabilities register first to unlock it. 48101acf691SAdam Lee */ 48201acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 48301acf691SAdam Lee if (ret) 48401acf691SAdam Lee return ret; 48501acf691SAdam Lee scratch |= 0x01; 48601acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 48701acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 48801acf691SAdam Lee 48901acf691SAdam Lee /* Disable ADMA1/2 */ 49001acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 49101acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 49201acf691SAdam Lee 49301acf691SAdam Lee /* Disable the infinite transfer mode */ 49401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 49501acf691SAdam Lee O2_SD_INF_MOD, &scratch); 49601acf691SAdam Lee if (ret) 49701acf691SAdam Lee return ret; 49801acf691SAdam Lee scratch |= 0x08; 49901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 50001acf691SAdam Lee 50101acf691SAdam Lee /* Lock WP */ 50201acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 50301acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 50401acf691SAdam Lee if (ret) 50501acf691SAdam Lee return ret; 50601acf691SAdam Lee scratch |= 0x80; 50701acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 50801acf691SAdam Lee break; 50901acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 51001acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 51101acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 51201acf691SAdam Lee /* UnLock WP */ 51301acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 51401acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 51501acf691SAdam Lee if (ret) 51601acf691SAdam Lee return ret; 51701acf691SAdam Lee 51801acf691SAdam Lee scratch &= 0x7f; 51901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 52001acf691SAdam Lee 521706adf6bSPeter Guo /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 522706adf6bSPeter Guo if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 523706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 524706adf6bSPeter Guo O2_SD_FUNC_REG0, 525706adf6bSPeter Guo &scratch_32); 526706adf6bSPeter Guo scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 527706adf6bSPeter Guo 528706adf6bSPeter Guo /* Check Whether subId is 0x11 or 0x12 */ 529706adf6bSPeter Guo if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 5303665ff03Sernest.zhang scratch_32 = 0x25100000; 531706adf6bSPeter Guo 532706adf6bSPeter Guo o2_pci_set_baseclk(chip, scratch_32); 533706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 534706adf6bSPeter Guo O2_SD_FUNC_REG4, 535706adf6bSPeter Guo &scratch_32); 536706adf6bSPeter Guo 537706adf6bSPeter Guo /* Enable Base Clk setting change */ 538706adf6bSPeter Guo scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 539706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 540706adf6bSPeter Guo O2_SD_FUNC_REG4, 541706adf6bSPeter Guo scratch_32); 542706adf6bSPeter Guo 543706adf6bSPeter Guo /* Set Tuning Window to 4 */ 544706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 545706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x44); 546706adf6bSPeter Guo 547706adf6bSPeter Guo break; 548706adf6bSPeter Guo } 549706adf6bSPeter Guo } 550706adf6bSPeter Guo 551706adf6bSPeter Guo /* Enable 8520 led function */ 552706adf6bSPeter Guo o2_pci_led_enable(chip); 553706adf6bSPeter Guo 55401acf691SAdam Lee /* Set timeout CLK */ 55501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 55601acf691SAdam Lee O2_SD_CLK_SETTING, &scratch_32); 55701acf691SAdam Lee if (ret) 55801acf691SAdam Lee return ret; 55901acf691SAdam Lee 56001acf691SAdam Lee scratch_32 &= ~(0xFF00); 56101acf691SAdam Lee scratch_32 |= 0x07E0C800; 56201acf691SAdam Lee pci_write_config_dword(chip->pdev, 56301acf691SAdam Lee O2_SD_CLK_SETTING, scratch_32); 56401acf691SAdam Lee 56501acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 56601acf691SAdam Lee O2_SD_CLKREQ, &scratch_32); 56701acf691SAdam Lee if (ret) 56801acf691SAdam Lee return ret; 56901acf691SAdam Lee scratch_32 |= 0x3; 57001acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 57101acf691SAdam Lee 57201acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 57301acf691SAdam Lee O2_SD_PLL_SETTING, &scratch_32); 57401acf691SAdam Lee if (ret) 57501acf691SAdam Lee return ret; 57601acf691SAdam Lee 57701acf691SAdam Lee scratch_32 &= ~(0x1F3F070E); 57801acf691SAdam Lee scratch_32 |= 0x18270106; 57901acf691SAdam Lee pci_write_config_dword(chip->pdev, 58001acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 58101acf691SAdam Lee 58201acf691SAdam Lee /* Disable UHS1 funciton */ 58301acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 58401acf691SAdam Lee O2_SD_CAP_REG2, &scratch_32); 58501acf691SAdam Lee if (ret) 58601acf691SAdam Lee return ret; 58701acf691SAdam Lee scratch_32 &= ~(0xE0); 58801acf691SAdam Lee pci_write_config_dword(chip->pdev, 58901acf691SAdam Lee O2_SD_CAP_REG2, scratch_32); 59001acf691SAdam Lee 59101acf691SAdam Lee if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 59201acf691SAdam Lee sdhci_pci_o2_fujin2_pci_init(chip); 59301acf691SAdam Lee 59401acf691SAdam Lee /* Lock WP */ 59501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 59601acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 59701acf691SAdam Lee if (ret) 59801acf691SAdam Lee return ret; 59901acf691SAdam Lee scratch |= 0x80; 60001acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 60101acf691SAdam Lee break; 60201acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 60301acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 60401acf691SAdam Lee /* UnLock WP */ 60501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 60601acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 60701acf691SAdam Lee if (ret) 60801acf691SAdam Lee return ret; 60901acf691SAdam Lee 61001acf691SAdam Lee scratch &= 0x7f; 61101acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 61201acf691SAdam Lee 61301acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 614706adf6bSPeter Guo O2_SD_PLL_SETTING, &scratch_32); 61501acf691SAdam Lee 61601acf691SAdam Lee if ((scratch_32 & 0xff000000) == 0x01000000) { 61701acf691SAdam Lee scratch_32 &= 0x0000FFFF; 61801acf691SAdam Lee scratch_32 |= 0x1F340000; 61901acf691SAdam Lee 62001acf691SAdam Lee pci_write_config_dword(chip->pdev, 62101acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 62201acf691SAdam Lee } else { 62301acf691SAdam Lee scratch_32 &= 0x0000FFFF; 6243665ff03Sernest.zhang scratch_32 |= 0x25100000; 62501acf691SAdam Lee 62601acf691SAdam Lee pci_write_config_dword(chip->pdev, 62701acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 62801acf691SAdam Lee 62901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 63001acf691SAdam Lee O2_SD_FUNC_REG4, 63101acf691SAdam Lee &scratch_32); 63201acf691SAdam Lee scratch_32 |= (1 << 22); 63301acf691SAdam Lee pci_write_config_dword(chip->pdev, 63401acf691SAdam Lee O2_SD_FUNC_REG4, scratch_32); 63501acf691SAdam Lee } 63601acf691SAdam Lee 637706adf6bSPeter Guo /* Set Tuning Windows to 5 */ 638706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 639706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x55); 64001acf691SAdam Lee /* Lock WP */ 64101acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 64201acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 64301acf691SAdam Lee if (ret) 64401acf691SAdam Lee return ret; 64501acf691SAdam Lee scratch |= 0x80; 64601acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 64701acf691SAdam Lee break; 64801acf691SAdam Lee } 64901acf691SAdam Lee 65001acf691SAdam Lee return 0; 65101acf691SAdam Lee } 65201acf691SAdam Lee 653b7813f0fSAdrian Hunter #ifdef CONFIG_PM_SLEEP 65401acf691SAdam Lee int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 65501acf691SAdam Lee { 65601acf691SAdam Lee sdhci_pci_o2_probe(chip); 65730cf2803SAdrian Hunter return sdhci_pci_resume_host(chip); 65801acf691SAdam Lee } 659b7813f0fSAdrian Hunter #endif 660328be8beSErnest Zhang(WH) 66169d91ed1SErnest Zhang(WH) static const struct sdhci_ops sdhci_pci_o2_ops = { 66269d91ed1SErnest Zhang(WH) .set_clock = sdhci_pci_o2_set_clock, 66369d91ed1SErnest Zhang(WH) .enable_dma = sdhci_pci_enable_dma, 66469d91ed1SErnest Zhang(WH) .set_bus_width = sdhci_set_bus_width, 66569d91ed1SErnest Zhang(WH) .reset = sdhci_reset, 66669d91ed1SErnest Zhang(WH) .set_uhs_signaling = sdhci_set_uhs_signaling, 66769d91ed1SErnest Zhang(WH) }; 66869d91ed1SErnest Zhang(WH) 669328be8beSErnest Zhang(WH) const struct sdhci_pci_fixes sdhci_o2 = { 670328be8beSErnest Zhang(WH) .probe = sdhci_pci_o2_probe, 671328be8beSErnest Zhang(WH) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 672328be8beSErnest Zhang(WH) .probe_slot = sdhci_pci_o2_probe_slot, 673328be8beSErnest Zhang(WH) #ifdef CONFIG_PM_SLEEP 674328be8beSErnest Zhang(WH) .resume = sdhci_pci_o2_resume, 675328be8beSErnest Zhang(WH) #endif 67669d91ed1SErnest Zhang(WH) .ops = &sdhci_pci_o2_ops, 677328be8beSErnest Zhang(WH) }; 678