19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 201acf691SAdam Lee /* 301acf691SAdam Lee * Copyright (C) 2013 BayHub Technology Ltd. 401acf691SAdam Lee * 501acf691SAdam Lee * Authors: Peter Guo <peter.guo@bayhubtech.com> 601acf691SAdam Lee * Adam Lee <adam.lee@canonical.com> 757322d54Sernest.zhang * Ernest Zhang <ernest.zhang@bayhubtech.com> 801acf691SAdam Lee */ 901acf691SAdam Lee 1001acf691SAdam Lee #include <linux/pci.h> 110086fc21Sernest.zhang #include <linux/mmc/host.h> 120086fc21Sernest.zhang #include <linux/mmc/mmc.h> 130086fc21Sernest.zhang #include <linux/delay.h> 147d440617SShirley Her (SC) #include <linux/iopoll.h> 15*4be33cf1SFred Ai #include <linux/bitfield.h> 1601acf691SAdam Lee 1701acf691SAdam Lee #include "sdhci.h" 1801acf691SAdam Lee #include "sdhci-pci.h" 19361eeda0SAdrian Hunter 20361eeda0SAdrian Hunter /* 21361eeda0SAdrian Hunter * O2Micro device registers 22361eeda0SAdrian Hunter */ 23361eeda0SAdrian Hunter 24361eeda0SAdrian Hunter #define O2_SD_MISC_REG5 0x64 25361eeda0SAdrian Hunter #define O2_SD_LD0_CTRL 0x68 26361eeda0SAdrian Hunter #define O2_SD_DEV_CTRL 0x88 27361eeda0SAdrian Hunter #define O2_SD_LOCK_WP 0xD3 28361eeda0SAdrian Hunter #define O2_SD_TEST_REG 0xD4 29361eeda0SAdrian Hunter #define O2_SD_FUNC_REG0 0xDC 30361eeda0SAdrian Hunter #define O2_SD_MULTI_VCC3V 0xEE 31361eeda0SAdrian Hunter #define O2_SD_CLKREQ 0xEC 32361eeda0SAdrian Hunter #define O2_SD_CAPS 0xE0 33361eeda0SAdrian Hunter #define O2_SD_ADMA1 0xE2 34361eeda0SAdrian Hunter #define O2_SD_ADMA2 0xE7 35361eeda0SAdrian Hunter #define O2_SD_INF_MOD 0xF1 36361eeda0SAdrian Hunter #define O2_SD_MISC_CTRL4 0xFC 371ad9f880SShirley Her #define O2_SD_MISC_CTRL 0x1C0 381ad9f880SShirley Her #define O2_SD_PWR_FORCE_L0 0x0002 39361eeda0SAdrian Hunter #define O2_SD_TUNING_CTRL 0x300 40361eeda0SAdrian Hunter #define O2_SD_PLL_SETTING 0x304 4157322d54Sernest.zhang #define O2_SD_MISC_SETTING 0x308 42361eeda0SAdrian Hunter #define O2_SD_CLK_SETTING 0x328 43361eeda0SAdrian Hunter #define O2_SD_CAP_REG2 0x330 44361eeda0SAdrian Hunter #define O2_SD_CAP_REG0 0x334 45361eeda0SAdrian Hunter #define O2_SD_UHS1_CAP_SETTING 0x33C 46361eeda0SAdrian Hunter #define O2_SD_DELAY_CTRL 0x350 47*4be33cf1SFred Ai #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 48361eeda0SAdrian Hunter #define O2_SD_UHS2_L1_CTRL 0x35C 49361eeda0SAdrian Hunter #define O2_SD_FUNC_REG3 0x3E0 50361eeda0SAdrian Hunter #define O2_SD_FUNC_REG4 0x3E4 51361eeda0SAdrian Hunter #define O2_SD_LED_ENABLE BIT(6) 52361eeda0SAdrian Hunter #define O2_SD_FREG0_LEDOFF BIT(13) 53*4be33cf1SFred Ai #define O2_SD_SEL_DLL BIT(16) 54361eeda0SAdrian Hunter #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) 55*4be33cf1SFred Ai #define O2_SD_PHASE_MASK GENMASK(23, 20) 56*4be33cf1SFred Ai #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) 57361eeda0SAdrian Hunter 58361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING 0x110 59361eeda0SAdrian Hunter #define O2_SD_VENDOR_SETTING2 0x1C8 600086fc21Sernest.zhang #define O2_SD_HW_TUNING_DISABLE BIT(4) 610086fc21Sernest.zhang 629674bab4SShirley Her (SC) #define O2_PLL_DLL_WDT_CONTROL1 0x1CC 6369d91ed1SErnest Zhang(WH) #define O2_PLL_FORCE_ACTIVE BIT(18) 6469d91ed1SErnest Zhang(WH) #define O2_PLL_LOCK_STATUS BIT(14) 6569d91ed1SErnest Zhang(WH) #define O2_PLL_SOFT_RESET BIT(12) 667d440617SShirley Her (SC) #define O2_DLL_LOCK_STATUS BIT(11) 6769d91ed1SErnest Zhang(WH) 6869d91ed1SErnest Zhang(WH) #define O2_SD_DETECT_SETTING 0x324 6969d91ed1SErnest Zhang(WH) 707d440617SShirley Her (SC) static const u32 dmdn_table[] = {0x2B1C0000, 717d440617SShirley Her (SC) 0x2C1A0000, 0x371B0000, 0x35100000}; 727d440617SShirley Her (SC) #define DMDN_SZ ARRAY_SIZE(dmdn_table) 737d440617SShirley Her (SC) 747d440617SShirley Her (SC) struct o2_host { 757d440617SShirley Her (SC) u8 dll_adjust_count; 767d440617SShirley Her (SC) }; 777d440617SShirley Her (SC) 78908fd508SShirley Her (SC) static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) 79908fd508SShirley Her (SC) { 80908fd508SShirley Her (SC) ktime_t timeout; 81908fd508SShirley Her (SC) u32 scratch32; 82908fd508SShirley Her (SC) 83908fd508SShirley Her (SC) /* Wait max 50 ms */ 84908fd508SShirley Her (SC) timeout = ktime_add_ms(ktime_get(), 50); 85908fd508SShirley Her (SC) while (1) { 86908fd508SShirley Her (SC) bool timedout = ktime_after(ktime_get(), timeout); 87908fd508SShirley Her (SC) 88908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); 89908fd508SShirley Her (SC) if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT 90908fd508SShirley Her (SC) == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) 91908fd508SShirley Her (SC) break; 92908fd508SShirley Her (SC) 93908fd508SShirley Her (SC) if (timedout) { 94908fd508SShirley Her (SC) pr_err("%s: Card Detect debounce never finished.\n", 95908fd508SShirley Her (SC) mmc_hostname(host->mmc)); 96908fd508SShirley Her (SC) sdhci_dumpregs(host); 97908fd508SShirley Her (SC) return; 98908fd508SShirley Her (SC) } 99908fd508SShirley Her (SC) udelay(10); 100908fd508SShirley Her (SC) } 101908fd508SShirley Her (SC) } 102908fd508SShirley Her (SC) 103908fd508SShirley Her (SC) static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) 104908fd508SShirley Her (SC) { 105908fd508SShirley Her (SC) ktime_t timeout; 106908fd508SShirley Her (SC) u16 scratch; 107908fd508SShirley Her (SC) u32 scratch32; 108908fd508SShirley Her (SC) 109908fd508SShirley Her (SC) /* PLL software reset */ 110908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 111908fd508SShirley Her (SC) scratch32 |= O2_PLL_SOFT_RESET; 112908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 113908fd508SShirley Her (SC) udelay(1); 114908fd508SShirley Her (SC) scratch32 &= ~(O2_PLL_SOFT_RESET); 115908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 116908fd508SShirley Her (SC) 117908fd508SShirley Her (SC) /* PLL force active */ 118908fd508SShirley Her (SC) scratch32 |= O2_PLL_FORCE_ACTIVE; 119908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 120908fd508SShirley Her (SC) 121908fd508SShirley Her (SC) /* Wait max 20 ms */ 122908fd508SShirley Her (SC) timeout = ktime_add_ms(ktime_get(), 20); 123908fd508SShirley Her (SC) while (1) { 124908fd508SShirley Her (SC) bool timedout = ktime_after(ktime_get(), timeout); 125908fd508SShirley Her (SC) 126908fd508SShirley Her (SC) scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); 127908fd508SShirley Her (SC) if (scratch & O2_PLL_LOCK_STATUS) 128908fd508SShirley Her (SC) break; 129908fd508SShirley Her (SC) if (timedout) { 130908fd508SShirley Her (SC) pr_err("%s: Internal clock never stabilised.\n", 131908fd508SShirley Her (SC) mmc_hostname(host->mmc)); 132908fd508SShirley Her (SC) sdhci_dumpregs(host); 133908fd508SShirley Her (SC) goto out; 134908fd508SShirley Her (SC) } 135908fd508SShirley Her (SC) udelay(10); 136908fd508SShirley Her (SC) } 137908fd508SShirley Her (SC) 138908fd508SShirley Her (SC) /* Wait for card detect finish */ 139908fd508SShirley Her (SC) udelay(1); 140908fd508SShirley Her (SC) sdhci_o2_wait_card_detect_stable(host); 141908fd508SShirley Her (SC) 142908fd508SShirley Her (SC) out: 143908fd508SShirley Her (SC) /* Cancel PLL force active */ 144908fd508SShirley Her (SC) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 145908fd508SShirley Her (SC) scratch32 &= ~O2_PLL_FORCE_ACTIVE; 146908fd508SShirley Her (SC) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); 147908fd508SShirley Her (SC) } 148908fd508SShirley Her (SC) 149908fd508SShirley Her (SC) static int sdhci_o2_get_cd(struct mmc_host *mmc) 150908fd508SShirley Her (SC) { 151908fd508SShirley Her (SC) struct sdhci_host *host = mmc_priv(mmc); 152908fd508SShirley Her (SC) 1537d440617SShirley Her (SC) if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) 154908fd508SShirley Her (SC) sdhci_o2_enable_internal_clock(host); 155908fd508SShirley Her (SC) 156908fd508SShirley Her (SC) return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 157908fd508SShirley Her (SC) } 158908fd508SShirley Her (SC) 159908fd508SShirley Her (SC) static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) 160908fd508SShirley Her (SC) { 161908fd508SShirley Her (SC) u32 scratch_32; 162908fd508SShirley Her (SC) 163908fd508SShirley Her (SC) pci_read_config_dword(chip->pdev, 164908fd508SShirley Her (SC) O2_SD_PLL_SETTING, &scratch_32); 165908fd508SShirley Her (SC) 166908fd508SShirley Her (SC) scratch_32 &= 0x0000FFFF; 167908fd508SShirley Her (SC) scratch_32 |= value; 168908fd508SShirley Her (SC) 169908fd508SShirley Her (SC) pci_write_config_dword(chip->pdev, 170908fd508SShirley Her (SC) O2_SD_PLL_SETTING, scratch_32); 171908fd508SShirley Her (SC) } 172908fd508SShirley Her (SC) 1737d440617SShirley Her (SC) static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) 1747d440617SShirley Her (SC) { 1757d440617SShirley Her (SC) return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 1767d440617SShirley Her (SC) } 1777d440617SShirley Her (SC) 1787d440617SShirley Her (SC) /* 1797d440617SShirley Her (SC) * This function is used to detect dll lock status. 1807d440617SShirley Her (SC) * Since the dll lock status bit will toggle randomly 1817d440617SShirley Her (SC) * with very short interval which needs to be polled 1827d440617SShirley Her (SC) * as fast as possible. Set sleep_us as 1 microsecond. 1837d440617SShirley Her (SC) */ 1847d440617SShirley Her (SC) static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) 1857d440617SShirley Her (SC) { 1867d440617SShirley Her (SC) u32 scratch32 = 0; 1877d440617SShirley Her (SC) 1887d440617SShirley Her (SC) return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 1897d440617SShirley Her (SC) scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); 1907d440617SShirley Her (SC) } 1917d440617SShirley Her (SC) 1920086fc21Sernest.zhang static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) 1930086fc21Sernest.zhang { 1940086fc21Sernest.zhang u16 reg; 1950086fc21Sernest.zhang 1960086fc21Sernest.zhang /* enable hardware tuning */ 1970086fc21Sernest.zhang reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); 1980086fc21Sernest.zhang reg &= ~O2_SD_HW_TUNING_DISABLE; 1990086fc21Sernest.zhang sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); 2000086fc21Sernest.zhang } 2010086fc21Sernest.zhang 2020086fc21Sernest.zhang static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) 2030086fc21Sernest.zhang { 2040086fc21Sernest.zhang int i; 2050086fc21Sernest.zhang 2067b7d897eSshirley her sdhci_send_tuning(host, opcode); 2070086fc21Sernest.zhang 2080086fc21Sernest.zhang for (i = 0; i < 150; i++) { 2090086fc21Sernest.zhang u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2100086fc21Sernest.zhang 2110086fc21Sernest.zhang if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 2120086fc21Sernest.zhang if (ctrl & SDHCI_CTRL_TUNED_CLK) { 2130086fc21Sernest.zhang host->tuning_done = true; 2140086fc21Sernest.zhang return; 2150086fc21Sernest.zhang } 2160086fc21Sernest.zhang pr_warn("%s: HW tuning failed !\n", 2170086fc21Sernest.zhang mmc_hostname(host->mmc)); 2180086fc21Sernest.zhang break; 2190086fc21Sernest.zhang } 2200086fc21Sernest.zhang 2210086fc21Sernest.zhang mdelay(1); 2220086fc21Sernest.zhang } 2230086fc21Sernest.zhang 2240086fc21Sernest.zhang pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 2250086fc21Sernest.zhang mmc_hostname(host->mmc)); 2260086fc21Sernest.zhang sdhci_reset_tuning(host); 2270086fc21Sernest.zhang } 2280086fc21Sernest.zhang 2297d440617SShirley Her (SC) /* 2307d440617SShirley Her (SC) * This function is used to fix o2 dll shift issue. 2317d440617SShirley Her (SC) * It isn't necessary to detect card present before recovery. 2327d440617SShirley Her (SC) * Firstly, it is used by bht emmc card, which is embedded. 2337d440617SShirley Her (SC) * Second, before call recovery card present will be detected 2347d440617SShirley Her (SC) * outside of the execute tuning function. 2357d440617SShirley Her (SC) */ 2367d440617SShirley Her (SC) static int sdhci_o2_dll_recovery(struct sdhci_host *host) 2377d440617SShirley Her (SC) { 2387d440617SShirley Her (SC) int ret = 0; 2397d440617SShirley Her (SC) u8 scratch_8 = 0; 2407d440617SShirley Her (SC) u32 scratch_32 = 0; 2417d440617SShirley Her (SC) struct sdhci_pci_slot *slot = sdhci_priv(host); 2427d440617SShirley Her (SC) struct sdhci_pci_chip *chip = slot->chip; 2437d440617SShirley Her (SC) struct o2_host *o2_host = sdhci_pci_priv(slot); 2447d440617SShirley Her (SC) 2457d440617SShirley Her (SC) /* UnLock WP */ 2467d440617SShirley Her (SC) pci_read_config_byte(chip->pdev, 2477d440617SShirley Her (SC) O2_SD_LOCK_WP, &scratch_8); 2487d440617SShirley Her (SC) scratch_8 &= 0x7f; 2497d440617SShirley Her (SC) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 2507d440617SShirley Her (SC) while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { 2517d440617SShirley Her (SC) /* Disable clock */ 2527d440617SShirley Her (SC) sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); 2537d440617SShirley Her (SC) 2547d440617SShirley Her (SC) /* PLL software reset */ 2557d440617SShirley Her (SC) scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); 2567d440617SShirley Her (SC) scratch_32 |= O2_PLL_SOFT_RESET; 2577d440617SShirley Her (SC) sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); 2587d440617SShirley Her (SC) 2597d440617SShirley Her (SC) pci_read_config_dword(chip->pdev, 2607d440617SShirley Her (SC) O2_SD_FUNC_REG4, 2617d440617SShirley Her (SC) &scratch_32); 2627d440617SShirley Her (SC) /* Enable Base Clk setting change */ 2637d440617SShirley Her (SC) scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 2647d440617SShirley Her (SC) pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); 2657d440617SShirley Her (SC) o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); 2667d440617SShirley Her (SC) 2677d440617SShirley Her (SC) /* Enable internal clock */ 2687d440617SShirley Her (SC) scratch_8 = SDHCI_CLOCK_INT_EN; 2697d440617SShirley Her (SC) sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); 2707d440617SShirley Her (SC) 2717d440617SShirley Her (SC) if (sdhci_o2_get_cd(host->mmc)) { 2727d440617SShirley Her (SC) /* 2737d440617SShirley Her (SC) * need wait at least 5ms for dll status stable, 2747d440617SShirley Her (SC) * after enable internal clock 2757d440617SShirley Her (SC) */ 2767d440617SShirley Her (SC) usleep_range(5000, 6000); 2777d440617SShirley Her (SC) if (sdhci_o2_wait_dll_detect_lock(host)) { 2787d440617SShirley Her (SC) scratch_8 |= SDHCI_CLOCK_CARD_EN; 2797d440617SShirley Her (SC) sdhci_writeb(host, scratch_8, 2807d440617SShirley Her (SC) SDHCI_CLOCK_CONTROL); 2817d440617SShirley Her (SC) ret = 1; 2827d440617SShirley Her (SC) } else { 2837d440617SShirley Her (SC) pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", 2847d440617SShirley Her (SC) mmc_hostname(host->mmc), 2857d440617SShirley Her (SC) o2_host->dll_adjust_count); 2867d440617SShirley Her (SC) } 2877d440617SShirley Her (SC) } else { 2887d440617SShirley Her (SC) pr_err("%s: card present detect failed.\n", 2897d440617SShirley Her (SC) mmc_hostname(host->mmc)); 2907d440617SShirley Her (SC) break; 2917d440617SShirley Her (SC) } 2927d440617SShirley Her (SC) 2937d440617SShirley Her (SC) o2_host->dll_adjust_count++; 2947d440617SShirley Her (SC) } 2957d440617SShirley Her (SC) if (!ret && o2_host->dll_adjust_count == DMDN_SZ) 2967d440617SShirley Her (SC) pr_err("%s: DLL adjust over max times\n", 2977d440617SShirley Her (SC) mmc_hostname(host->mmc)); 2987d440617SShirley Her (SC) /* Lock WP */ 2997d440617SShirley Her (SC) pci_read_config_byte(chip->pdev, 3007d440617SShirley Her (SC) O2_SD_LOCK_WP, &scratch_8); 3017d440617SShirley Her (SC) scratch_8 |= 0x80; 3027d440617SShirley Her (SC) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 3037d440617SShirley Her (SC) return ret; 3047d440617SShirley Her (SC) } 3057d440617SShirley Her (SC) 3060086fc21Sernest.zhang static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 3070086fc21Sernest.zhang { 3080086fc21Sernest.zhang struct sdhci_host *host = mmc_priv(mmc); 309*4be33cf1SFred Ai struct sdhci_pci_slot *slot = sdhci_priv(host); 310*4be33cf1SFred Ai struct sdhci_pci_chip *chip = slot->chip; 3110086fc21Sernest.zhang int current_bus_width = 0; 3121ad9f880SShirley Her u32 scratch32 = 0; 3131ad9f880SShirley Her u16 scratch = 0; 314*4be33cf1SFred Ai u8 scratch_8 = 0; 315*4be33cf1SFred Ai u32 reg_val; 3160086fc21Sernest.zhang 3170086fc21Sernest.zhang /* 3180086fc21Sernest.zhang * This handler only implements the eMMC tuning that is specific to 3190086fc21Sernest.zhang * this controller. Fall back to the standard method for other TIMING. 3200086fc21Sernest.zhang */ 3217b7d897eSshirley her if ((host->timing != MMC_TIMING_MMC_HS200) && 3227b7d897eSshirley her (host->timing != MMC_TIMING_UHS_SDR104)) 3230086fc21Sernest.zhang return sdhci_execute_tuning(mmc, opcode); 3240086fc21Sernest.zhang 3257b7d897eSshirley her if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && 3267b7d897eSshirley her (opcode != MMC_SEND_TUNING_BLOCK))) 3270086fc21Sernest.zhang return -EINVAL; 3281ad9f880SShirley Her 3291ad9f880SShirley Her /* Force power mode enter L0 */ 3301ad9f880SShirley Her scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 3311ad9f880SShirley Her scratch |= O2_SD_PWR_FORCE_L0; 3321ad9f880SShirley Her sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 3331ad9f880SShirley Her 334*4be33cf1SFred Ai /* Stop clk */ 335*4be33cf1SFred Ai reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 336*4be33cf1SFred Ai reg_val &= ~SDHCI_CLOCK_CARD_EN; 337*4be33cf1SFred Ai sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 338*4be33cf1SFred Ai 339*4be33cf1SFred Ai /* UnLock WP */ 340*4be33cf1SFred Ai pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 341*4be33cf1SFred Ai scratch_8 &= 0x7f; 342*4be33cf1SFred Ai pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 343*4be33cf1SFred Ai 344*4be33cf1SFred Ai /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ 345*4be33cf1SFred Ai pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); 346*4be33cf1SFred Ai reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 347*4be33cf1SFred Ai reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); 348*4be33cf1SFred Ai pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); 349*4be33cf1SFred Ai 350*4be33cf1SFred Ai /* Lock WP */ 351*4be33cf1SFred Ai pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); 352*4be33cf1SFred Ai scratch_8 |= 0x80; 353*4be33cf1SFred Ai pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); 354*4be33cf1SFred Ai 355*4be33cf1SFred Ai /* Start clk */ 356*4be33cf1SFred Ai reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 357*4be33cf1SFred Ai reg_val |= SDHCI_CLOCK_CARD_EN; 358*4be33cf1SFred Ai sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); 359*4be33cf1SFred Ai 3601ad9f880SShirley Her /* wait DLL lock, timeout value 5ms */ 3611ad9f880SShirley Her if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, 3621ad9f880SShirley Her scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) 3631ad9f880SShirley Her pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", 3641ad9f880SShirley Her mmc_hostname(host->mmc)); 3657d440617SShirley Her (SC) /* 3667d440617SShirley Her (SC) * Judge the tuning reason, whether caused by dll shift 3677d440617SShirley Her (SC) * If cause by dll shift, should call sdhci_o2_dll_recovery 3687d440617SShirley Her (SC) */ 3697d440617SShirley Her (SC) if (!sdhci_o2_wait_dll_detect_lock(host)) 3707d440617SShirley Her (SC) if (!sdhci_o2_dll_recovery(host)) { 3717d440617SShirley Her (SC) pr_err("%s: o2 dll recovery failed\n", 3727d440617SShirley Her (SC) mmc_hostname(host->mmc)); 3737d440617SShirley Her (SC) return -EINVAL; 3747d440617SShirley Her (SC) } 3750086fc21Sernest.zhang /* 3760086fc21Sernest.zhang * o2 sdhci host didn't support 8bit emmc tuning 3770086fc21Sernest.zhang */ 3780086fc21Sernest.zhang if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { 3790086fc21Sernest.zhang current_bus_width = mmc->ios.bus_width; 3800f7b79a4SRaul E Rangel mmc->ios.bus_width = MMC_BUS_WIDTH_4; 3810086fc21Sernest.zhang sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); 3820086fc21Sernest.zhang } 3830086fc21Sernest.zhang 3840086fc21Sernest.zhang sdhci_o2_set_tuning_mode(host); 3850086fc21Sernest.zhang 3860086fc21Sernest.zhang sdhci_start_tuning(host); 3870086fc21Sernest.zhang 3880086fc21Sernest.zhang __sdhci_o2_execute_tuning(host, opcode); 3890086fc21Sernest.zhang 3900086fc21Sernest.zhang sdhci_end_tuning(host); 3910086fc21Sernest.zhang 3920f7b79a4SRaul E Rangel if (current_bus_width == MMC_BUS_WIDTH_8) { 3930f7b79a4SRaul E Rangel mmc->ios.bus_width = MMC_BUS_WIDTH_8; 3940086fc21Sernest.zhang sdhci_set_bus_width(host, current_bus_width); 3950f7b79a4SRaul E Rangel } 3960086fc21Sernest.zhang 3971ad9f880SShirley Her /* Cancel force power mode enter L0 */ 3981ad9f880SShirley Her scratch = sdhci_readw(host, O2_SD_MISC_CTRL); 3991ad9f880SShirley Her scratch &= ~(O2_SD_PWR_FORCE_L0); 4001ad9f880SShirley Her sdhci_writew(host, scratch, O2_SD_MISC_CTRL); 4011ad9f880SShirley Her 4027b7d897eSshirley her sdhci_reset(host, SDHCI_RESET_CMD); 4037b7d897eSshirley her sdhci_reset(host, SDHCI_RESET_DATA); 4047b7d897eSshirley her 4050086fc21Sernest.zhang host->flags &= ~SDHCI_HS400_TUNING; 4060086fc21Sernest.zhang return 0; 4070086fc21Sernest.zhang } 40801acf691SAdam Lee 409706adf6bSPeter Guo static void o2_pci_led_enable(struct sdhci_pci_chip *chip) 410706adf6bSPeter Guo { 411706adf6bSPeter Guo int ret; 412706adf6bSPeter Guo u32 scratch_32; 413706adf6bSPeter Guo 414706adf6bSPeter Guo /* Set led of SD host function enable */ 415706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 416706adf6bSPeter Guo O2_SD_FUNC_REG0, &scratch_32); 417706adf6bSPeter Guo if (ret) 418706adf6bSPeter Guo return; 419706adf6bSPeter Guo 420706adf6bSPeter Guo scratch_32 &= ~O2_SD_FREG0_LEDOFF; 421706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 422706adf6bSPeter Guo O2_SD_FUNC_REG0, scratch_32); 423706adf6bSPeter Guo 424706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 425706adf6bSPeter Guo O2_SD_TEST_REG, &scratch_32); 426706adf6bSPeter Guo if (ret) 427706adf6bSPeter Guo return; 428706adf6bSPeter Guo 429706adf6bSPeter Guo scratch_32 |= O2_SD_LED_ENABLE; 430706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 431706adf6bSPeter Guo O2_SD_TEST_REG, scratch_32); 432706adf6bSPeter Guo } 433706adf6bSPeter Guo 434f0cbd780SBen Hutchings static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) 43501acf691SAdam Lee { 43601acf691SAdam Lee u32 scratch_32; 43701acf691SAdam Lee int ret; 43801acf691SAdam Lee /* Improve write performance for SD3.0 */ 43901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); 44001acf691SAdam Lee if (ret) 44101acf691SAdam Lee return; 44201acf691SAdam Lee scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); 44301acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); 44401acf691SAdam Lee 44501acf691SAdam Lee /* Enable Link abnormal reset generating Reset */ 44601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); 44701acf691SAdam Lee if (ret) 44801acf691SAdam Lee return; 44901acf691SAdam Lee scratch_32 &= ~((1 << 19) | (1 << 11)); 45001acf691SAdam Lee scratch_32 |= (1 << 10); 45101acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); 45201acf691SAdam Lee 45301acf691SAdam Lee /* set card power over current protection */ 45401acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); 45501acf691SAdam Lee if (ret) 45601acf691SAdam Lee return; 45701acf691SAdam Lee scratch_32 |= (1 << 4); 45801acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); 45901acf691SAdam Lee 46001acf691SAdam Lee /* adjust the output delay for SD mode */ 46101acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); 46201acf691SAdam Lee 46301acf691SAdam Lee /* Set the output voltage setting of Aux 1.2v LDO */ 46401acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); 46501acf691SAdam Lee if (ret) 46601acf691SAdam Lee return; 46701acf691SAdam Lee scratch_32 &= ~(3 << 12); 46801acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); 46901acf691SAdam Lee 47001acf691SAdam Lee /* Set Max power supply capability of SD host */ 47101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); 47201acf691SAdam Lee if (ret) 47301acf691SAdam Lee return; 47401acf691SAdam Lee scratch_32 &= ~(0x01FE); 47501acf691SAdam Lee scratch_32 |= 0x00CC; 47601acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); 47701acf691SAdam Lee /* Set DLL Tuning Window */ 47801acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 47901acf691SAdam Lee O2_SD_TUNING_CTRL, &scratch_32); 48001acf691SAdam Lee if (ret) 48101acf691SAdam Lee return; 48201acf691SAdam Lee scratch_32 &= ~(0x000000FF); 48301acf691SAdam Lee scratch_32 |= 0x00000066; 48401acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); 48501acf691SAdam Lee 48601acf691SAdam Lee /* Set UHS2 T_EIDLE */ 48701acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 48801acf691SAdam Lee O2_SD_UHS2_L1_CTRL, &scratch_32); 48901acf691SAdam Lee if (ret) 49001acf691SAdam Lee return; 49101acf691SAdam Lee scratch_32 &= ~(0x000000FC); 49201acf691SAdam Lee scratch_32 |= 0x00000084; 49301acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); 49401acf691SAdam Lee 49501acf691SAdam Lee /* Set UHS2 Termination */ 49601acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); 49701acf691SAdam Lee if (ret) 49801acf691SAdam Lee return; 49901acf691SAdam Lee scratch_32 &= ~((1 << 21) | (1 << 30)); 50001acf691SAdam Lee 50101acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); 50201acf691SAdam Lee 50301acf691SAdam Lee /* Set L1 Entrance Timer */ 50401acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); 50501acf691SAdam Lee if (ret) 50601acf691SAdam Lee return; 50701acf691SAdam Lee scratch_32 &= ~(0xf0000000); 50801acf691SAdam Lee scratch_32 |= 0x30000000; 50901acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); 51001acf691SAdam Lee 51101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 51201acf691SAdam Lee O2_SD_MISC_CTRL4, &scratch_32); 51301acf691SAdam Lee if (ret) 51401acf691SAdam Lee return; 51501acf691SAdam Lee scratch_32 &= ~(0x000f0000); 51601acf691SAdam Lee scratch_32 |= 0x00080000; 51701acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); 51801acf691SAdam Lee } 51901acf691SAdam Lee 52002a3c0bdSernest.zhang static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, 52102a3c0bdSernest.zhang struct sdhci_host *host) 52202a3c0bdSernest.zhang { 52302a3c0bdSernest.zhang int ret; 52402a3c0bdSernest.zhang 52502a3c0bdSernest.zhang ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); 52602a3c0bdSernest.zhang if (!ret) { 5270818d197SColin Ian King pr_info("%s: unsupported MSI, use INTx irq\n", 52802a3c0bdSernest.zhang mmc_hostname(host->mmc)); 52902a3c0bdSernest.zhang return; 53002a3c0bdSernest.zhang } 53102a3c0bdSernest.zhang 53202a3c0bdSernest.zhang ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, 53302a3c0bdSernest.zhang PCI_IRQ_MSI | PCI_IRQ_MSIX); 53402a3c0bdSernest.zhang if (ret < 0) { 53502a3c0bdSernest.zhang pr_err("%s: enable PCI MSI failed, err=%d\n", 53602a3c0bdSernest.zhang mmc_hostname(host->mmc), ret); 53702a3c0bdSernest.zhang return; 53802a3c0bdSernest.zhang } 53902a3c0bdSernest.zhang 54002a3c0bdSernest.zhang host->irq = pci_irq_vector(chip->pdev, 0); 54102a3c0bdSernest.zhang } 54202a3c0bdSernest.zhang 54369d91ed1SErnest Zhang(WH) static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) 54469d91ed1SErnest Zhang(WH) { 54569d91ed1SErnest Zhang(WH) /* Enable internal clock */ 54669d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_INT_EN; 54769d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 54869d91ed1SErnest Zhang(WH) 5497d440617SShirley Her (SC) sdhci_o2_enable_internal_clock(host); 55069d91ed1SErnest Zhang(WH) if (sdhci_o2_get_cd(host->mmc)) { 55169d91ed1SErnest Zhang(WH) clk |= SDHCI_CLOCK_CARD_EN; 55269d91ed1SErnest Zhang(WH) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 55369d91ed1SErnest Zhang(WH) } 55469d91ed1SErnest Zhang(WH) } 55569d91ed1SErnest Zhang(WH) 556580b946eSZou Wei static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) 55769d91ed1SErnest Zhang(WH) { 55869d91ed1SErnest Zhang(WH) u16 clk; 5597b7d897eSshirley her u8 scratch; 5607b7d897eSshirley her u32 scratch_32; 5617b7d897eSshirley her struct sdhci_pci_slot *slot = sdhci_priv(host); 5627b7d897eSshirley her struct sdhci_pci_chip *chip = slot->chip; 56369d91ed1SErnest Zhang(WH) 56469d91ed1SErnest Zhang(WH) host->mmc->actual_clock = 0; 56569d91ed1SErnest Zhang(WH) 56669d91ed1SErnest Zhang(WH) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 56769d91ed1SErnest Zhang(WH) 56869d91ed1SErnest Zhang(WH) if (clock == 0) 56969d91ed1SErnest Zhang(WH) return; 57069d91ed1SErnest Zhang(WH) 571*4be33cf1SFred Ai /* UnLock WP */ 5727b7d897eSshirley her pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 5737b7d897eSshirley her scratch &= 0x7f; 5747b7d897eSshirley her pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 5757b7d897eSshirley her 576*4be33cf1SFred Ai if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { 5777b7d897eSshirley her pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); 5787b7d897eSshirley her 5797b7d897eSshirley her if ((scratch_32 & 0xFFFF0000) != 0x2c280000) 5807b7d897eSshirley her o2_pci_set_baseclk(chip, 0x2c280000); 581*4be33cf1SFred Ai } 5827b7d897eSshirley her 583*4be33cf1SFred Ai pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); 584*4be33cf1SFred Ai scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); 585*4be33cf1SFred Ai pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); 586*4be33cf1SFred Ai 587*4be33cf1SFred Ai /* Lock WP */ 5887b7d897eSshirley her pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 5897b7d897eSshirley her scratch |= 0x80; 5907b7d897eSshirley her pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 5917b7d897eSshirley her 59269d91ed1SErnest Zhang(WH) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 59369d91ed1SErnest Zhang(WH) sdhci_o2_enable_clk(host, clk); 59469d91ed1SErnest Zhang(WH) } 59569d91ed1SErnest Zhang(WH) 596580b946eSZou Wei static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) 59701acf691SAdam Lee { 59801acf691SAdam Lee struct sdhci_pci_chip *chip; 59901acf691SAdam Lee struct sdhci_host *host; 6007d440617SShirley Her (SC) struct o2_host *o2_host = sdhci_pci_priv(slot); 601de23f0b7SRaul E Rangel u32 reg, caps; 60257322d54Sernest.zhang int ret; 60301acf691SAdam Lee 60401acf691SAdam Lee chip = slot->chip; 60501acf691SAdam Lee host = slot->host; 606de23f0b7SRaul E Rangel 6077d440617SShirley Her (SC) o2_host->dll_adjust_count = 0; 608de23f0b7SRaul E Rangel caps = sdhci_readl(host, SDHCI_CAPABILITIES); 609de23f0b7SRaul E Rangel 610de23f0b7SRaul E Rangel /* 611de23f0b7SRaul E Rangel * mmc_select_bus_width() will test the bus to determine the actual bus 612de23f0b7SRaul E Rangel * width. 613de23f0b7SRaul E Rangel */ 614de23f0b7SRaul E Rangel if (caps & SDHCI_CAN_DO_8BIT) 615de23f0b7SRaul E Rangel host->mmc->caps |= MMC_CAP_8_BIT_DATA; 616de23f0b7SRaul E Rangel 61701acf691SAdam Lee switch (chip->pdev->device) { 61801acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 61901acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 62001acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 62101acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 62201acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 62301acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); 62401acf691SAdam Lee if (reg & 0x1) 62501acf691SAdam Lee host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 62601acf691SAdam Lee 62702a3c0bdSernest.zhang sdhci_pci_o2_enable_msi(chip, host); 62802a3c0bdSernest.zhang 62957322d54Sernest.zhang if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { 63057322d54Sernest.zhang ret = pci_read_config_dword(chip->pdev, 63157322d54Sernest.zhang O2_SD_MISC_SETTING, ®); 63257322d54Sernest.zhang if (ret) 63357322d54Sernest.zhang return -EIO; 63457322d54Sernest.zhang if (reg & (1 << 4)) { 63557322d54Sernest.zhang pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", 63657322d54Sernest.zhang mmc_hostname(host->mmc)); 63757322d54Sernest.zhang host->flags &= ~SDHCI_SIGNALING_330; 63857322d54Sernest.zhang host->flags |= SDHCI_SIGNALING_180; 63957322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SD; 64057322d54Sernest.zhang host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 64169d91ed1SErnest Zhang(WH) pci_write_config_dword(chip->pdev, 64269d91ed1SErnest Zhang(WH) O2_SD_DETECT_SETTING, 3); 64357322d54Sernest.zhang } 64469d91ed1SErnest Zhang(WH) 64569d91ed1SErnest Zhang(WH) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 64657322d54Sernest.zhang } 64757322d54Sernest.zhang 648cdd2b769Sshirley her if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { 649cdd2b769Sshirley her slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; 650cdd2b769Sshirley her host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 651cdd2b769Sshirley her host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 652cdd2b769Sshirley her } 653cdd2b769Sshirley her 6540086fc21Sernest.zhang host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; 6550086fc21Sernest.zhang 65601acf691SAdam Lee if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) 65701acf691SAdam Lee break; 65801acf691SAdam Lee /* set dll watch dog timer */ 65901acf691SAdam Lee reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); 66001acf691SAdam Lee reg |= (1 << 12); 66101acf691SAdam Lee sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); 66201acf691SAdam Lee 66301acf691SAdam Lee break; 66401acf691SAdam Lee default: 66501acf691SAdam Lee break; 66601acf691SAdam Lee } 66701acf691SAdam Lee 66801acf691SAdam Lee return 0; 66901acf691SAdam Lee } 67001acf691SAdam Lee 671580b946eSZou Wei static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) 67201acf691SAdam Lee { 67301acf691SAdam Lee int ret; 67401acf691SAdam Lee u8 scratch; 67501acf691SAdam Lee u32 scratch_32; 67601acf691SAdam Lee 67701acf691SAdam Lee switch (chip->pdev->device) { 67801acf691SAdam Lee case PCI_DEVICE_ID_O2_8220: 67901acf691SAdam Lee case PCI_DEVICE_ID_O2_8221: 68001acf691SAdam Lee case PCI_DEVICE_ID_O2_8320: 68101acf691SAdam Lee case PCI_DEVICE_ID_O2_8321: 68201acf691SAdam Lee /* This extra setup is required due to broken ADMA. */ 68301acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 68401acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 68501acf691SAdam Lee if (ret) 68601acf691SAdam Lee return ret; 68701acf691SAdam Lee scratch &= 0x7f; 68801acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 68901acf691SAdam Lee 69001acf691SAdam Lee /* Set Multi 3 to VCC3V# */ 69101acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); 69201acf691SAdam Lee 69301acf691SAdam Lee /* Disable CLK_REQ# support after media DET */ 69401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 69501acf691SAdam Lee O2_SD_CLKREQ, &scratch); 69601acf691SAdam Lee if (ret) 69701acf691SAdam Lee return ret; 69801acf691SAdam Lee scratch |= 0x20; 69901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 70001acf691SAdam Lee 70101acf691SAdam Lee /* Choose capabilities, enable SDMA. We have to write 0x01 70201acf691SAdam Lee * to the capabilities register first to unlock it. 70301acf691SAdam Lee */ 70401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 70501acf691SAdam Lee if (ret) 70601acf691SAdam Lee return ret; 70701acf691SAdam Lee scratch |= 0x01; 70801acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 70901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); 71001acf691SAdam Lee 71101acf691SAdam Lee /* Disable ADMA1/2 */ 71201acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); 71301acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); 71401acf691SAdam Lee 71501acf691SAdam Lee /* Disable the infinite transfer mode */ 71601acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 71701acf691SAdam Lee O2_SD_INF_MOD, &scratch); 71801acf691SAdam Lee if (ret) 71901acf691SAdam Lee return ret; 72001acf691SAdam Lee scratch |= 0x08; 72101acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 72201acf691SAdam Lee 72301acf691SAdam Lee /* Lock WP */ 72401acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 72501acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 72601acf691SAdam Lee if (ret) 72701acf691SAdam Lee return ret; 72801acf691SAdam Lee scratch |= 0x80; 72901acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 73001acf691SAdam Lee break; 73101acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS0: 73201acf691SAdam Lee case PCI_DEVICE_ID_O2_SDS1: 73301acf691SAdam Lee case PCI_DEVICE_ID_O2_FUJIN2: 73401acf691SAdam Lee /* UnLock WP */ 73501acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 73601acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 73701acf691SAdam Lee if (ret) 73801acf691SAdam Lee return ret; 73901acf691SAdam Lee 74001acf691SAdam Lee scratch &= 0x7f; 74101acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 74201acf691SAdam Lee 743706adf6bSPeter Guo /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ 744706adf6bSPeter Guo if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { 745706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 746706adf6bSPeter Guo O2_SD_FUNC_REG0, 747706adf6bSPeter Guo &scratch_32); 748d599005aSDinghao Liu if (ret) 749d599005aSDinghao Liu return ret; 750706adf6bSPeter Guo scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 751706adf6bSPeter Guo 752706adf6bSPeter Guo /* Check Whether subId is 0x11 or 0x12 */ 753706adf6bSPeter Guo if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { 7543665ff03Sernest.zhang scratch_32 = 0x25100000; 755706adf6bSPeter Guo 756706adf6bSPeter Guo o2_pci_set_baseclk(chip, scratch_32); 757706adf6bSPeter Guo ret = pci_read_config_dword(chip->pdev, 758706adf6bSPeter Guo O2_SD_FUNC_REG4, 759706adf6bSPeter Guo &scratch_32); 760d599005aSDinghao Liu if (ret) 761d599005aSDinghao Liu return ret; 762706adf6bSPeter Guo 763706adf6bSPeter Guo /* Enable Base Clk setting change */ 764706adf6bSPeter Guo scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; 765706adf6bSPeter Guo pci_write_config_dword(chip->pdev, 766706adf6bSPeter Guo O2_SD_FUNC_REG4, 767706adf6bSPeter Guo scratch_32); 768706adf6bSPeter Guo 769706adf6bSPeter Guo /* Set Tuning Window to 4 */ 770706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 771706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x44); 772706adf6bSPeter Guo 773706adf6bSPeter Guo break; 774706adf6bSPeter Guo } 775706adf6bSPeter Guo } 776706adf6bSPeter Guo 777706adf6bSPeter Guo /* Enable 8520 led function */ 778706adf6bSPeter Guo o2_pci_led_enable(chip); 779706adf6bSPeter Guo 78001acf691SAdam Lee /* Set timeout CLK */ 78101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 78201acf691SAdam Lee O2_SD_CLK_SETTING, &scratch_32); 78301acf691SAdam Lee if (ret) 78401acf691SAdam Lee return ret; 78501acf691SAdam Lee 78601acf691SAdam Lee scratch_32 &= ~(0xFF00); 78701acf691SAdam Lee scratch_32 |= 0x07E0C800; 78801acf691SAdam Lee pci_write_config_dword(chip->pdev, 78901acf691SAdam Lee O2_SD_CLK_SETTING, scratch_32); 79001acf691SAdam Lee 79101acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 79201acf691SAdam Lee O2_SD_CLKREQ, &scratch_32); 79301acf691SAdam Lee if (ret) 79401acf691SAdam Lee return ret; 79501acf691SAdam Lee scratch_32 |= 0x3; 79601acf691SAdam Lee pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 79701acf691SAdam Lee 79801acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 79901acf691SAdam Lee O2_SD_PLL_SETTING, &scratch_32); 80001acf691SAdam Lee if (ret) 80101acf691SAdam Lee return ret; 80201acf691SAdam Lee 80301acf691SAdam Lee scratch_32 &= ~(0x1F3F070E); 80401acf691SAdam Lee scratch_32 |= 0x18270106; 80501acf691SAdam Lee pci_write_config_dword(chip->pdev, 80601acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 80701acf691SAdam Lee 80801acf691SAdam Lee /* Disable UHS1 funciton */ 80901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 81001acf691SAdam Lee O2_SD_CAP_REG2, &scratch_32); 81101acf691SAdam Lee if (ret) 81201acf691SAdam Lee return ret; 81301acf691SAdam Lee scratch_32 &= ~(0xE0); 81401acf691SAdam Lee pci_write_config_dword(chip->pdev, 81501acf691SAdam Lee O2_SD_CAP_REG2, scratch_32); 81601acf691SAdam Lee 81701acf691SAdam Lee if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) 81801acf691SAdam Lee sdhci_pci_o2_fujin2_pci_init(chip); 81901acf691SAdam Lee 82001acf691SAdam Lee /* Lock WP */ 82101acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 82201acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 82301acf691SAdam Lee if (ret) 82401acf691SAdam Lee return ret; 82501acf691SAdam Lee scratch |= 0x80; 82601acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 82701acf691SAdam Lee break; 82801acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD0: 82901acf691SAdam Lee case PCI_DEVICE_ID_O2_SEABIRD1: 83001acf691SAdam Lee /* UnLock WP */ 83101acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 83201acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 83301acf691SAdam Lee if (ret) 83401acf691SAdam Lee return ret; 83501acf691SAdam Lee 83601acf691SAdam Lee scratch &= 0x7f; 83701acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 83801acf691SAdam Lee 83901acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 840706adf6bSPeter Guo O2_SD_PLL_SETTING, &scratch_32); 841d599005aSDinghao Liu if (ret) 842d599005aSDinghao Liu return ret; 84301acf691SAdam Lee 84401acf691SAdam Lee if ((scratch_32 & 0xff000000) == 0x01000000) { 84501acf691SAdam Lee scratch_32 &= 0x0000FFFF; 84601acf691SAdam Lee scratch_32 |= 0x1F340000; 84701acf691SAdam Lee 84801acf691SAdam Lee pci_write_config_dword(chip->pdev, 84901acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 85001acf691SAdam Lee } else { 85101acf691SAdam Lee scratch_32 &= 0x0000FFFF; 8523665ff03Sernest.zhang scratch_32 |= 0x25100000; 85301acf691SAdam Lee 85401acf691SAdam Lee pci_write_config_dword(chip->pdev, 85501acf691SAdam Lee O2_SD_PLL_SETTING, scratch_32); 85601acf691SAdam Lee 85701acf691SAdam Lee ret = pci_read_config_dword(chip->pdev, 85801acf691SAdam Lee O2_SD_FUNC_REG4, 85901acf691SAdam Lee &scratch_32); 860d599005aSDinghao Liu if (ret) 861d599005aSDinghao Liu return ret; 86201acf691SAdam Lee scratch_32 |= (1 << 22); 86301acf691SAdam Lee pci_write_config_dword(chip->pdev, 86401acf691SAdam Lee O2_SD_FUNC_REG4, scratch_32); 86501acf691SAdam Lee } 86601acf691SAdam Lee 867706adf6bSPeter Guo /* Set Tuning Windows to 5 */ 868706adf6bSPeter Guo pci_write_config_byte(chip->pdev, 869706adf6bSPeter Guo O2_SD_TUNING_CTRL, 0x55); 87001acf691SAdam Lee /* Lock WP */ 87101acf691SAdam Lee ret = pci_read_config_byte(chip->pdev, 87201acf691SAdam Lee O2_SD_LOCK_WP, &scratch); 87301acf691SAdam Lee if (ret) 87401acf691SAdam Lee return ret; 87501acf691SAdam Lee scratch |= 0x80; 87601acf691SAdam Lee pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 87701acf691SAdam Lee break; 87801acf691SAdam Lee } 87901acf691SAdam Lee 88001acf691SAdam Lee return 0; 88101acf691SAdam Lee } 88201acf691SAdam Lee 883b7813f0fSAdrian Hunter #ifdef CONFIG_PM_SLEEP 884580b946eSZou Wei static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) 88501acf691SAdam Lee { 88601acf691SAdam Lee sdhci_pci_o2_probe(chip); 88730cf2803SAdrian Hunter return sdhci_pci_resume_host(chip); 88801acf691SAdam Lee } 889b7813f0fSAdrian Hunter #endif 890328be8beSErnest Zhang(WH) 89169d91ed1SErnest Zhang(WH) static const struct sdhci_ops sdhci_pci_o2_ops = { 89269d91ed1SErnest Zhang(WH) .set_clock = sdhci_pci_o2_set_clock, 89369d91ed1SErnest Zhang(WH) .enable_dma = sdhci_pci_enable_dma, 89469d91ed1SErnest Zhang(WH) .set_bus_width = sdhci_set_bus_width, 89569d91ed1SErnest Zhang(WH) .reset = sdhci_reset, 89669d91ed1SErnest Zhang(WH) .set_uhs_signaling = sdhci_set_uhs_signaling, 89769d91ed1SErnest Zhang(WH) }; 89869d91ed1SErnest Zhang(WH) 899328be8beSErnest Zhang(WH) const struct sdhci_pci_fixes sdhci_o2 = { 900328be8beSErnest Zhang(WH) .probe = sdhci_pci_o2_probe, 901328be8beSErnest Zhang(WH) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 90249baa01cSDaniel Drake .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, 903328be8beSErnest Zhang(WH) .probe_slot = sdhci_pci_o2_probe_slot, 904328be8beSErnest Zhang(WH) #ifdef CONFIG_PM_SLEEP 905328be8beSErnest Zhang(WH) .resume = sdhci_pci_o2_resume, 906328be8beSErnest Zhang(WH) #endif 90769d91ed1SErnest Zhang(WH) .ops = &sdhci_pci_o2_ops, 9087d440617SShirley Her (SC) .priv_size = sizeof(struct o2_host), 909328be8beSErnest Zhang(WH) }; 910